diff mbox

[9/9] tcg: remove #ifdef #endif around TCGOpcode tests

Message ID 1348084823-18277-10-git-send-email-aurelien@aurel32.net
State New
Headers show

Commit Message

Aurelien Jarno Sept. 19, 2012, 8 p.m. UTC 
Commit 25c4d9cc changed all TCGOpcode enums to be available, so we don't
need to #ifdef #endif the one that are available only on some targets.
This makes the code easier to read.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
 tcg/tcg.c |   16 +---------------
 1 file changed, 1 insertion(+), 15 deletions(-)

Comments

Richard Henderson Sept. 19, 2012, 9:50 p.m. UTC | #1 
On 09/19/2012 01:00 PM, Aurelien Jarno wrote:
> Commit 25c4d9cc changed all TCGOpcode enums to be available, so we don't
> need to #ifdef #endif the one that are available only on some targets.
> This makes the code easier to read.
> 
> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

Reviewed-by: Richard Henderson <rth@twiddle.net>


r~
diff mbox

Patch

diff --git a/tcg/tcg.c b/tcg/tcg.c
index b8a1bec..57fca70 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -937,11 +937,7 @@  void tcg_dump_ops(TCGContext *s)
                                                        args[nb_oargs + i]));
                 }
             }
-        } else if (c == INDEX_op_movi_i32 
-#if TCG_TARGET_REG_BITS == 64
-                   || c == INDEX_op_movi_i64
-#endif
-                   ) {
+        } else if (c == INDEX_op_movi_i32 || c == INDEX_op_movi_i64) {
             tcg_target_ulong val;
             TCGHelperInfo *th;
 
@@ -991,17 +987,11 @@  void tcg_dump_ops(TCGContext *s)
             }
             switch (c) {
             case INDEX_op_brcond_i32:
-#if TCG_TARGET_REG_BITS == 32
             case INDEX_op_brcond2_i32:
-#elif TCG_TARGET_REG_BITS == 64
             case INDEX_op_brcond_i64:
-#endif
             case INDEX_op_setcond_i32:
-#if TCG_TARGET_REG_BITS == 32
             case INDEX_op_setcond2_i32:
-#elif TCG_TARGET_REG_BITS == 64
             case INDEX_op_setcond_i64:
-#endif
                 if (args[k] < ARRAY_SIZE(cond_name) && cond_name[args[k]]) {
                     qemu_log(",%s", cond_name[args[k++]]);
                 } else {
@@ -2103,16 +2093,12 @@  static inline int tcg_gen_code_common(TCGContext *s, uint8_t *gen_code_buf,
 #endif
         switch(opc) {
         case INDEX_op_mov_i32:
-#if TCG_TARGET_REG_BITS == 64
         case INDEX_op_mov_i64:
-#endif
             dead_args = s->op_dead_args[op_index];
             tcg_reg_alloc_mov(s, def, args, dead_args);
             break;
         case INDEX_op_movi_i32:
-#if TCG_TARGET_REG_BITS == 64
         case INDEX_op_movi_i64:
-#endif
             tcg_reg_alloc_movi(s, args);
             break;
         case INDEX_op_debug_insn_start: