[ARM] Cleanup: Replace GET_CODE comparisons with predicates

Message ID	000f01cd8c22$d394e660$7abeb320$@tkachov@arm.com
State	New
Headers	show Return-Path: <gcc-patches-return-326041-incoming=patchwork.ozlabs.org@gcc.gnu.org> Comment: DKIM? See http://www.dkim.org Comment: DomainKeys? See http://antispam.yahoo.com/domainkeys DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=default; d=gcc.gnu.org; h=Received:Received:X-SWARE-Spam-Status:X-Spam-Check-By:Received:Received:Received:From:To:Cc:Subject:Date:Message-ID:MIME-Version:X-MC-Unique:Content-Type:X-IsSubscribed:Mailing-List:Precedence:List-Id:List-Unsubscribe:List-Archive:List-Post:List-Help:Sender:Delivered-To; b=LU5Y+UYS/Ki9lPkJtfXcQ2+nIicwzKuQJZ00H+xEgPIG+CkejYxsrxOiu7Cgbk 5RRIsI2FOqptxIPDiNsCKJkoZldVlgBMyi4JELLbDMc4Lak8giFoR+Qs9oz52VQW YqqPFF+FbztDymfD/enqoHB2GifqTgs3zKRwDv32ut4n4=; From: "Kyrylo Tkachov" <kyrylo.tkachov@arm.com> To: <gcc-patches@gcc.gnu.org> Cc: "Ramana Radhakrishnan" <Ramana.Radhakrishnan@arm.com> Subject: [PATCH, ARM] Cleanup: Replace GET_CODE comparisons with predicates Date: Thu, 6 Sep 2012 12:29:06 +0100 Message-ID: <000f01cd8c22$d394e660$7abeb320$@tkachov@arm.com> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="----=_NextPart_000_0010_01CD8C2B.35594E60" Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk Sender: gcc-patches-owner@gcc.gnu.org

--- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -2337,7 +2337,7 @@ use_return_insn (int iscond, rtx sibling) /* ... or for a tail-call argument ... */ if (sibling) { - gcc_assert (GET_CODE (sibling) == CALL_INSN); + gcc_assert (CALL_P (sibling)); if (find_regno_fusage (sibling, USE, 3)) return 0; @@ -2558,7 +2558,7 @@ arm_split_constant (enum rtx_code code, enum machine_mode mode, rtx insn, cond = NULL_RTX; if (subtargets || code == SET - || (GET_CODE (target) == REG && GET_CODE (source) == REG + || (REG_P (target) && REG_P (source) && REGNO (target) != REGNO (source))) { /* After arm_reorg has been called, we can't fix up expensive @@ -2990,7 +2990,7 @@ arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond, if (generate) { if (mode == SImode && i == 16) - /* Use UXTH in preference to UBFX, since on Thumb2 it's a + /* Use UXTH in preference to UBFX, since on Thumb2 it's a smaller insn. */ emit_constant_insn (cond, gen_zero_extendhisi2 @@ -3530,7 +3530,7 @@ arm_canonicalize_comparison (enum rtx_code code, rtx *op0, rtx *op1) { /* Missing comparison. First try to use an available comparison. */ - if (GET_CODE (*op1) == CONST_INT) + if (CONST_INT_P (*op1)) { i = INTVAL (*op1); switch (code) @@ -3583,7 +3583,7 @@ arm_canonicalize_comparison (enum rtx_code code, rtx *op0, rtx *op1) /* Comparisons smaller than DImode. Only adjust comparisons against an out-of-range constant. */ - if (GET_CODE (*op1) != CONST_INT + if (!CONST_INT_P (*op1) || const_ok_for_arm (INTVAL (*op1)) || const_ok_for_arm (- INTVAL (*op1))) return code; @@ -4160,7 +4160,7 @@ aapcs_vfp_sub_candidate (const_tree type, enum machine_mode *modep) tree index = TYPE_DOMAIN (type); /* Can't handle incomplete types. */ - if (!COMPLETE_TYPE_P(type)) + if (!COMPLETE_TYPE_P (type)) return -1; count = aapcs_vfp_sub_candidate (TREE_TYPE (type), modep); @@ -4192,7 +4192,7 @@ aapcs_vfp_sub_candidate (const_tree type, enum machine_mode *modep) tree field; /* Can't handle incomplete types. */ - if (!COMPLETE_TYPE_P(type)) + if (!COMPLETE_TYPE_P (type)) return -1; for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field)) @@ -4224,7 +4224,7 @@ aapcs_vfp_sub_candidate (const_tree type, enum machine_mode *modep) tree field; /* Can't handle incomplete types. */ - if (!COMPLETE_TYPE_P(type)) + if (!COMPLETE_TYPE_P (type)) return -1; for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field)) @@ -5442,7 +5442,7 @@ legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg) && GET_CODE (XEXP (XEXP (orig, 0), 0)) == UNSPEC && XINT (XEXP (XEXP (orig, 0), 0), 1) == UNSPEC_TLS) { - gcc_assert (GET_CODE (XEXP (XEXP (orig, 0), 1)) == CONST_INT); + gcc_assert (CONST_INT_P (XEXP (XEXP (orig, 0), 1))); return orig; } @@ -5458,7 +5458,7 @@ legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg) offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, base == reg ? 0 : reg); - if (GET_CODE (offset) == CONST_INT) + if (CONST_INT_P (offset)) { /* The base register doesn't really matter, we only want to test the index for the appropriate mode. */ @@ -5468,7 +5468,7 @@ legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg) offset = force_reg (Pmode, offset); } - if (GET_CODE (offset) == CONST_INT) + if (CONST_INT_P (offset)) return plus_constant (Pmode, base, INTVAL (offset)); } @@ -5649,7 +5649,7 @@ arm_address_register_rtx_p (rtx x, int strict_p) { int regno; - if (GET_CODE (x) != REG) + if (!REG_P (x)) return 0; regno = REGNO (x); @@ -5716,7 +5716,7 @@ arm_legitimate_address_outer_p (enum machine_mode mode, rtx x, RTX_CODE outer, to fixup invalid register choices. */ if (use_ldrd && GET_CODE (x) == POST_MODIFY - && GET_CODE (addend) == REG) + && REG_P (addend)) return 0; return ((use_ldrd || GET_MODE_SIZE (mode) <= 4) @@ -5730,7 +5730,7 @@ arm_legitimate_address_outer_p (enum machine_mode mode, rtx x, RTX_CODE outer, || (code == CONST && GET_CODE (XEXP (x, 0)) == PLUS && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF - && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))) + && CONST_INT_P (XEXP (XEXP (x, 0), 1))))) return 1; else if (mode == TImode || (TARGET_NEON && VALID_NEON_STRUCT_MODE (mode))) @@ -5742,7 +5742,7 @@ arm_legitimate_address_outer_p (enum machine_mode mode, rtx x, RTX_CODE outer, rtx xop1 = XEXP (x, 1); return ((arm_address_register_rtx_p (xop0, strict_p) - && ((GET_CODE(xop1) == CONST_INT + && ((CONST_INT_P (xop1) && arm_legitimate_index_p (mode, xop1, outer, strict_p)) || (!strict_p && will_be_in_index_register (xop1)))) || (arm_address_register_rtx_p (xop1, strict_p) @@ -5800,7 +5800,7 @@ thumb2_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p) rtx addend = XEXP (XEXP (x, 1), 1); HOST_WIDE_INT offset; - if (GET_CODE (addend) != CONST_INT) + if (!CONST_INT_P (addend)) return 0; offset = INTVAL(addend); @@ -5818,7 +5818,7 @@ thumb2_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p) || (code == CONST && GET_CODE (XEXP (x, 0)) == PLUS && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF - && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))) + && CONST_INT_P (XEXP (XEXP (x, 0), 1))))) return 1; else if (mode == TImode || (TARGET_NEON && VALID_NEON_STRUCT_MODE (mode))) @@ -5930,7 +5930,7 @@ arm_legitimate_index_p (enum machine_mode mode, rtx index, RTX_CODE outer, rtx op = XEXP (index, 1); return (arm_address_register_rtx_p (XEXP (index, 0), strict_p) - && GET_CODE (op) == CONST_INT + && CONST_INT_P (op) && INTVAL (op) > 0 && INTVAL (op) <= 31); } @@ -5962,7 +5962,7 @@ thumb2_index_mul_operand (rtx op) { HOST_WIDE_INT val; - if (GET_CODE(op) != CONST_INT) + if (!CONST_INT_P (op)) return false; val = INTVAL(op); @@ -6052,7 +6052,7 @@ thumb2_legitimate_index_p (enum machine_mode mode, rtx index, int strict_p) rtx op = XEXP (index, 1); return (arm_address_register_rtx_p (XEXP (index, 0), strict_p) - && GET_CODE (op) == CONST_INT + && CONST_INT_P (op) && INTVAL (op) > 0 && INTVAL (op) <= 3); } @@ -6068,7 +6068,7 @@ thumb1_base_register_rtx_p (rtx x, enum machine_mode mode, int strict_p) { int regno; - if (GET_CODE (x) != REG) + if (!REG_P (x)) return 0; regno = REGNO (x); @@ -6142,7 +6142,7 @@ thumb1_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p) || (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF - && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))) + && CONST_INT_P (XEXP (XEXP (x, 0), 1))))) return 1; /* Post-inc indexing only supported for SImode and larger. */ @@ -6167,7 +6167,7 @@ thumb1_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p) /* REG+const has 5-7 bit offset for non-SP registers. */ else if ((thumb1_index_register_rtx_p (XEXP (x, 0), strict_p) || XEXP (x, 0) == arg_pointer_rtx) - && GET_CODE (XEXP (x, 1)) == CONST_INT + && CONST_INT_P (XEXP (x, 1)) && thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1)))) return 1; @@ -6175,23 +6175,23 @@ thumb1_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p) larger is supported. */ /* ??? Should probably check for DI/DFmode overflow here just like GO_IF_LEGITIMATE_OFFSET does. */ - else if (GET_CODE (XEXP (x, 0)) == REG + else if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) == STACK_POINTER_REGNUM && GET_MODE_SIZE (mode) >= 4 - && GET_CODE (XEXP (x, 1)) == CONST_INT + && CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) + GET_MODE_SIZE (mode) <= 1024 && (INTVAL (XEXP (x, 1)) & 3) == 0) return 1; - else if (GET_CODE (XEXP (x, 0)) == REG + else if (REG_P (XEXP (x, 0)) && (REGNO (XEXP (x, 0)) == FRAME_POINTER_REGNUM || REGNO (XEXP (x, 0)) == ARG_POINTER_REGNUM || (REGNO (XEXP (x, 0)) >= FIRST_VIRTUAL_REGISTER && REGNO (XEXP (x, 0)) <= LAST_VIRTUAL_POINTER_REGISTER)) && GET_MODE_SIZE (mode) >= 4 - && GET_CODE (XEXP (x, 1)) == CONST_INT + && CONST_INT_P (XEXP (x, 1)) && (INTVAL (XEXP (x, 1)) & 3) == 0) return 1; } @@ -6495,7 +6495,7 @@ arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode) xop1 = force_reg (SImode, xop1); if (ARM_BASE_REGISTER_RTX_P (xop0) - && GET_CODE (xop1) == CONST_INT) + && CONST_INT_P (xop1)) { HOST_WIDE_INT n, low_n; rtx base_reg, val; @@ -6551,7 +6551,7 @@ arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode) with absolute addresses which often allows for the base register to be factorized for multiple adjacent memory references, and it might even allows for the mini pool to be avoided entirely. */ - else if (GET_CODE (x) == CONST_INT && optimize > 0) + else if (CONST_INT_P (x) && optimize > 0) { unsigned int bits; HOST_WIDE_INT mask, base, index; @@ -6598,7 +6598,7 @@ thumb_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode) return legitimize_tls_address (x, NULL_RTX); if (GET_CODE (x) == PLUS - && GET_CODE (XEXP (x, 1)) == CONST_INT + && CONST_INT_P (XEXP (x, 1)) && (INTVAL (XEXP (x, 1)) >= 32 * GET_MODE_SIZE (mode) || INTVAL (XEXP (x, 1)) < 0)) { @@ -6668,9 +6668,9 @@ arm_legitimize_reload_address (rtx *p, /* We must recognize output that we have already generated ourselves. */ if (GET_CODE (*p) == PLUS && GET_CODE (XEXP (*p, 0)) == PLUS - && GET_CODE (XEXP (XEXP (*p, 0), 0)) == REG - && GET_CODE (XEXP (XEXP (*p, 0), 1)) == CONST_INT - && GET_CODE (XEXP (*p, 1)) == CONST_INT) + && REG_P (XEXP (XEXP (*p, 0), 0)) + && CONST_INT_P (XEXP (XEXP (*p, 0), 1)) + && CONST_INT_P (XEXP (*p, 1))) { push_reload (XEXP (*p, 0), NULL_RTX, &XEXP (*p, 0), NULL, MODE_BASE_REG_CLASS (mode), GET_MODE (*p), @@ -6679,13 +6679,13 @@ arm_legitimize_reload_address (rtx *p, } if (GET_CODE (*p) == PLUS - && GET_CODE (XEXP (*p, 0)) == REG + && REG_P (XEXP (*p, 0)) && ARM_REGNO_OK_FOR_BASE_P (REGNO (XEXP (*p, 0))) /* If the base register is equivalent to a constant, let the generic code handle it. Otherwise we will run into problems if a future reload pass decides to rematerialize the constant. */ && !reg_equiv_constant (ORIGINAL_REGNO (XEXP (*p, 0))) - && GET_CODE (XEXP (*p, 1)) == CONST_INT) + && CONST_INT_P (XEXP (*p, 1))) { HOST_WIDE_INT val = INTVAL (XEXP (*p, 1)); HOST_WIDE_INT low, high; @@ -6854,7 +6854,7 @@ thumb_legitimize_reload_address (rtx *x_p, && GET_MODE_SIZE (mode) < 4 && REG_P (XEXP (x, 0)) && XEXP (x, 0) == stack_pointer_rtx - && GET_CODE (XEXP (x, 1)) == CONST_INT + && CONST_INT_P (XEXP (x, 1)) && !thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1)))) { rtx orig_x = x; @@ -6952,8 +6952,8 @@ arm_legitimate_constant_p_1 (enum machine_mode mode, rtx x) static bool thumb_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x) { - return (GET_CODE (x) == CONST_INT - || GET_CODE (x) == CONST_DOUBLE + return (CONST_INT_P (x) + || CONST_DOUBLE_P (x) || CONSTANT_ADDRESS_P (x) || flag_pic); } @@ -6985,11 +6985,11 @@ arm_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x) } #define REG_OR_SUBREG_REG(X) \ - (GET_CODE (X) == REG \ - || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG)) + (REG_P (X) \ + || (GET_CODE (X) == SUBREG && REG_P (SUBREG_REG (X)))) #define REG_OR_SUBREG_RTX(X) \ - (GET_CODE (X) == REG ? (X) : SUBREG_REG (X)) + (REG_P (X) ? (X) : SUBREG_REG (X)) static inline int thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer) @@ -7011,7 +7011,7 @@ thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer) return COSTS_N_INSNS (1); case MULT: - if (GET_CODE (XEXP (x, 1)) == CONST_INT) + if (CONST_INT_P (XEXP (x, 1))) { int cycles = 0; unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1)); @@ -7027,8 +7027,8 @@ thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer) case SET: return (COSTS_N_INSNS (1) - + 4 * ((GET_CODE (SET_SRC (x)) == MEM) - + GET_CODE (SET_DEST (x)) == MEM)); + + 4 * ((MEM_P (SET_SRC (x))) + + MEM_P (SET_DEST (x)))); case CONST_INT: if (outer == SET) @@ -7144,9 +7144,9 @@ arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed) return false; case ROTATE: - if (GET_CODE (XEXP (x, 1)) == REG) + if (REG_P (XEXP (x, 1))) *total = COSTS_N_INSNS (1); /* Need to subtract from 32 */ - else if (GET_CODE (XEXP (x, 1)) != CONST_INT) + else if (!CONST_INT_P (XEXP (x, 1))) *total = rtx_cost (XEXP (x, 1), code, 1, speed); /* Fall through */ @@ -7170,7 +7170,7 @@ arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed) /* Increase the cost of complex shifts because they aren't any faster, and reduce dual issue opportunities. */ if (arm_tune_cortex_a9 - && outer != SET && GET_CODE (XEXP (x, 1)) != CONST_INT) + && outer != SET && !CONST_INT_P (XEXP (x, 1))) ++*total; return true; @@ -7179,14 +7179,14 @@ arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed) if (mode == DImode) { *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); - if (GET_CODE (XEXP (x, 0)) == CONST_INT + if (CONST_INT_P (XEXP (x, 0)) && const_ok_for_arm (INTVAL (XEXP (x, 0)))) { *total += rtx_cost (XEXP (x, 1), code, 1, speed); return true; } - if (GET_CODE (XEXP (x, 1)) == CONST_INT + if (CONST_INT_P (XEXP (x, 1)) && const_ok_for_arm (INTVAL (XEXP (x, 1)))) { *total += rtx_cost (XEXP (x, 0), code, 0, speed); @@ -7203,14 +7203,14 @@ arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed) || (mode == DFmode && !TARGET_VFP_SINGLE))) { *total = COSTS_N_INSNS (1); - if (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE + if (CONST_DOUBLE_P (XEXP (x, 0)) && arm_const_double_rtx (XEXP (x, 0))) { *total += rtx_cost (XEXP (x, 1), code, 1, speed); return true; } - if (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE + if (CONST_DOUBLE_P (XEXP (x, 1)) && arm_const_double_rtx (XEXP (x, 1))) { *total += rtx_cost (XEXP (x, 0), code, 0, speed); @@ -7224,7 +7224,7 @@ arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed) } *total = COSTS_N_INSNS (1); - if (GET_CODE (XEXP (x, 0)) == CONST_INT + if (CONST_INT_P (XEXP (x, 0)) && const_ok_for_arm (INTVAL (XEXP (x, 0)))) { *total += rtx_cost (XEXP (x, 1), code, 1, speed); @@ -7262,7 +7262,7 @@ arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed) || GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == RTX_COMM_COMPARE) { *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code, 0, speed); - if (GET_CODE (XEXP (XEXP (x, 1), 0)) == REG + if (REG_P (XEXP (XEXP (x, 1), 0)) && REGNO (XEXP (XEXP (x, 1), 0)) != CC_REGNUM) *total += COSTS_N_INSNS (1); @@ -7300,7 +7300,7 @@ arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed) || (mode == DFmode && !TARGET_VFP_SINGLE))) { *total = COSTS_N_INSNS (1); - if (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE + if (CONST_DOUBLE_P (XEXP (x, 1)) && arm_const_double_rtx (XEXP (x, 1))) { *total += rtx_cost (XEXP (x, 0), code, 0, speed); @@ -7318,7 +7318,7 @@ arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed) || GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == RTX_COMM_COMPARE) { *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 1), code, 1, speed); - if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG + if (REG_P (XEXP (XEXP (x, 0), 0)) && REGNO (XEXP (XEXP (x, 0), 0)) != CC_REGNUM) *total += COSTS_N_INSNS (1); return true; @@ -7335,13 +7335,13 @@ arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed) operand. */ if (REG_OR_SUBREG_REG (XEXP (x, 0)) && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0))) - && GET_CODE (XEXP (x, 1)) != CONST_INT) + && !CONST_INT_P (XEXP (x, 1))) *total = COSTS_N_INSNS (1); if (mode == DImode) { *total += COSTS_N_INSNS (2); - if (GET_CODE (XEXP (x, 1)) == CONST_INT + if (CONST_INT_P (XEXP (x, 1)) && const_ok_for_op (INTVAL (XEXP (x, 1)), code)) { *total += rtx_cost (XEXP (x, 0), code, 0, speed); @@ -7352,7 +7352,7 @@ arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed) } *total += COSTS_N_INSNS (1); - if (GET_CODE (XEXP (x, 1)) == CONST_INT + if (CONST_INT_P (XEXP (x, 1)) && const_ok_for_op (INTVAL (XEXP (x, 1)), code)) { *total += rtx_cost (XEXP (x, 0), code, 0, speed); @@ -7432,7 +7432,7 @@ arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed) { *total += rtx_cost (XEXP (XEXP (x, 0), 0), subcode, 0, speed); /* Register shifts cost an extra cycle. */ - if (GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT) + if (!CONST_INT_P (XEXP (XEXP (x, 0), 1))) *total += COSTS_N_INSNS (1) + rtx_cost (XEXP (XEXP (x, 0), 1), subcode, 1, speed); return true; @@ -7452,7 +7452,7 @@ arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed) if (!((GET_RTX_CLASS (GET_CODE (operand)) == RTX_COMPARE || GET_RTX_CLASS (GET_CODE (operand)) == RTX_COMM_COMPARE) - && GET_CODE (XEXP (operand, 0)) == REG + && REG_P (XEXP (operand, 0)) && REGNO (XEXP (operand, 0)) == CC_REGNUM)) *total += COSTS_N_INSNS (1); *total += (rtx_cost (XEXP (x, 1), code, 1, speed) @@ -7468,7 +7468,7 @@ arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed) goto scc_insn; case GE: - if ((GET_CODE (XEXP (x, 0)) != REG || REGNO (XEXP (x, 0)) != CC_REGNUM) + if ((!REG_P (XEXP (x, 0)) || REGNO (XEXP (x, 0)) != CC_REGNUM) && mode == SImode && XEXP (x, 1) == const0_rtx) { *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code, 0, speed); @@ -7477,7 +7477,7 @@ arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed) goto scc_insn; case LT: - if ((GET_CODE (XEXP (x, 0)) != REG || REGNO (XEXP (x, 0)) != CC_REGNUM) + if ((!REG_P (XEXP (x, 0)) || REGNO (XEXP (x, 0)) != CC_REGNUM) && mode == SImode && XEXP (x, 1) == const0_rtx) { *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code, 0, speed); @@ -7504,21 +7504,21 @@ arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed) performed, then they cost 2 instructions. Otherwise they need an additional comparison before them. */ *total = COSTS_N_INSNS (2); - if (GET_CODE (XEXP (x, 0)) == REG && REGNO (XEXP (x, 0)) == CC_REGNUM) + if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) == CC_REGNUM) { return true; } /* Fall through */ case COMPARE: - if (GET_CODE (XEXP (x, 0)) == REG && REGNO (XEXP (x, 0)) == CC_REGNUM) + if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) == CC_REGNUM) { *total = 0; return true; } *total += COSTS_N_INSNS (1); - if (GET_CODE (XEXP (x, 1)) == CONST_INT + if (CONST_INT_P (XEXP (x, 1)) && const_ok_for_op (INTVAL (XEXP (x, 1)), code)) { *total += rtx_cost (XEXP (x, 0), code, 0, speed); @@ -7550,7 +7550,7 @@ arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed) case SMIN: case SMAX: *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code, 0, speed); - if (GET_CODE (XEXP (x, 1)) != CONST_INT + if (!CONST_INT_P (XEXP (x, 1)) || !const_ok_for_arm (INTVAL (XEXP (x, 1)))) *total += rtx_cost (XEXP (x, 1), code, 1, speed); return true; @@ -7667,7 +7667,7 @@ arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed) case SET: return false; - + case UNSPEC: /* We cost this as high as our memory costs to allow this to be hoisted from loops. */ @@ -7716,7 +7716,7 @@ thumb1_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer) return COSTS_N_INSNS (1); case MULT: - if (GET_CODE (XEXP (x, 1)) == CONST_INT) + if (CONST_INT_P (XEXP (x, 1))) { /* Thumb1 mul instruction can't operate on const. We must Load it into a register first. */ @@ -7727,8 +7727,8 @@ thumb1_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer) case SET: return (COSTS_N_INSNS (1) - + 4 * ((GET_CODE (SET_SRC (x)) == MEM) - + GET_CODE (SET_DEST (x)) == MEM)); + + 4 * ((MEM_P (SET_SRC (x))) + + MEM_P (SET_DEST (x)))); case CONST_INT: if (outer == SET) @@ -7804,14 +7804,14 @@ thumb1_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer) { case QImode: return (1 + (mode == DImode ? 4 : 0) - + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); + + (MEM_P (XEXP (x, 0)) ? 10 : 0)); case HImode: return (4 + (mode == DImode ? 4 : 0) - + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); + + (MEM_P (XEXP (x, 0)) ? 10 : 0)); case SImode: - return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); + return (1 + (MEM_P (XEXP (x, 0)) ? 10 : 0)); default: return 99; @@ -7861,7 +7861,7 @@ arm_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, return false; case ROTATE: - if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG) + if (mode == SImode && REG_P (XEXP (x, 1))) { *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code, 0, false); return true; @@ -7871,7 +7871,7 @@ arm_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, case ASHIFT: case LSHIFTRT: case ASHIFTRT: - if (mode == DImode && GET_CODE (XEXP (x, 1)) == CONST_INT) + if (mode == DImode && CONST_INT_P (XEXP (x, 1))) { *total = COSTS_N_INSNS (3) + rtx_cost (XEXP (x, 0), code, 0, false); return true; @@ -7880,7 +7880,7 @@ arm_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, { *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code, 0, false); /* Slightly disparage register shifts, but not by much. */ - if (GET_CODE (XEXP (x, 1)) != CONST_INT) + if (!CONST_INT_P (XEXP (x, 1))) *total += 1 + rtx_cost (XEXP (x, 1), code, 1, false); return true; } @@ -8097,7 +8097,7 @@ arm_slowmul_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, return false; } - if (GET_CODE (XEXP (x, 1)) == CONST_INT) + if (CONST_INT_P (XEXP (x, 1))) { unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1)) & (unsigned HOST_WIDE_INT) 0xffffffff); @@ -8163,7 +8163,7 @@ arm_fastmul_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, return false; } - if (GET_CODE (XEXP (x, 1)) == CONST_INT) + if (CONST_INT_P (XEXP (x, 1))) { unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1)) & (unsigned HOST_WIDE_INT) 0xffffffff); @@ -8255,7 +8255,7 @@ arm_xscale_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, return false; } - if (GET_CODE (XEXP (x, 1)) == CONST_INT) + if (CONST_INT_P (XEXP (x, 1))) { /* If operand 1 is a constant we can more accurately calculate the cost of the multiply. The multiplier can @@ -8383,7 +8383,7 @@ arm_arm_address_cost (rtx x) if (c == PLUS) { - if (GET_CODE (XEXP (x, 1)) == CONST_INT) + if (CONST_INT_P (XEXP (x, 1))) return 2; if (ARITHMETIC_P (XEXP (x, 0)) || ARITHMETIC_P (XEXP (x, 1))) @@ -8403,8 +8403,8 @@ arm_thumb_address_cost (rtx x) if (c == REG) return 1; if (c == PLUS - && GET_CODE (XEXP (x, 0)) == REG - && GET_CODE (XEXP (x, 1)) == CONST_INT) + && REG_P (XEXP (x, 0)) + && CONST_INT_P (XEXP (x, 1))) return 1; return 2; @@ -8654,13 +8654,13 @@ arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost) /* Call insns don't incur a stall, even if they follow a load. */ if (REG_NOTE_KIND (link) == 0 - && GET_CODE (insn) == CALL_INSN) + && CALL_P (insn)) return 1; if ((i_pat = single_set (insn)) != NULL - && GET_CODE (SET_SRC (i_pat)) == MEM + && MEM_P (SET_SRC (i_pat)) && (d_pat = single_set (dep)) != NULL - && GET_CODE (SET_DEST (d_pat)) == MEM) + && MEM_P (SET_DEST (d_pat))) { rtx src_mem = XEXP (SET_SRC (i_pat), 0); /* This is a load after a store, there is no conflict if the load reads @@ -8755,7 +8755,7 @@ vfp3_const_double_index (rtx x) HOST_WIDE_INT m1, m2; int point_pos = 2 * HOST_BITS_PER_WIDE_INT - 1; - if (!TARGET_VFP3 || GET_CODE (x) != CONST_DOUBLE) + if (!TARGET_VFP3 || !CONST_DOUBLE_P (x)) return -1; REAL_VALUE_FROM_CONST_DOUBLE (r, x); @@ -8958,12 +8958,12 @@ neon_valid_immediate (rtx op, enum machine_mode mode, int inverse, unsigned HOST_WIDE_INT elpart; unsigned int part, parts; - if (GET_CODE (el) == CONST_INT) + if (CONST_INT_P (el)) { elpart = INTVAL (el); parts = 1; } - else if (GET_CODE (el) == CONST_DOUBLE) + else if (CONST_DOUBLE_P (el)) { elpart = CONST_DOUBLE_LOW (el); parts = 2; @@ -8979,7 +8979,7 @@ neon_valid_immediate (rtx op, enum machine_mode mode, int inverse, bytes[idx++] = (elpart & 0xff) ^ invmask; elpart >>= BITS_PER_UNIT; } - if (GET_CODE (el) == CONST_DOUBLE) + if (CONST_DOUBLE_P (el)) elpart = CONST_DOUBLE_HIGH (el); } } @@ -9153,9 +9153,9 @@ neon_immediate_valid_for_shift (rtx op, enum machine_mode mode, rtx el = CONST_VECTOR_ELT (op, i); unsigned HOST_WIDE_INT elpart; - if (GET_CODE (el) == CONST_INT) + if (CONST_INT_P (el)) elpart = INTVAL (el); - else if (GET_CODE (el) == CONST_DOUBLE) + else if (CONST_DOUBLE_P (el)) return 0; else gcc_unreachable (); @@ -9325,7 +9325,7 @@ neon_make_constant (rtx vals) for (i = 0; i < n_elts; ++i) { rtx x = XVECEXP (vals, 0, i); - if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) + if (CONST_INT_P (x) || CONST_DOUBLE_P (x)) n_const++; } if (n_const == n_elts) @@ -9466,7 +9466,7 @@ bounds_check (rtx operand, HOST_WIDE_INT low, HOST_WIDE_INT high, { HOST_WIDE_INT lane; - gcc_assert (GET_CODE (operand) == CONST_INT); + gcc_assert (CONST_INT_P (operand)); lane = INTVAL (operand); @@ -9523,7 +9523,7 @@ arm_coproc_mem_operand (rtx op, bool wb) return FALSE; /* Constants are converted into offsets from labels. */ - if (GET_CODE (op) != MEM) + if (!MEM_P (op)) return FALSE; ind = XEXP (op, 0); @@ -9533,11 +9533,11 @@ arm_coproc_mem_operand (rtx op, bool wb) || (GET_CODE (ind) == CONST && GET_CODE (XEXP (ind, 0)) == PLUS && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF - && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT))) + && CONST_INT_P (XEXP (XEXP (ind, 0), 1))))) return TRUE; /* Match: (mem (reg)). */ - if (GET_CODE (ind) == REG) + if (REG_P (ind)) return arm_address_register_rtx_p (ind, 0); /* Autoincremment addressing modes. POST_INC and PRE_DEC are @@ -9562,9 +9562,9 @@ arm_coproc_mem_operand (rtx op, bool wb) (plus (reg) (const)). */ if (GET_CODE (ind) == PLUS - && GET_CODE (XEXP (ind, 0)) == REG + && REG_P (XEXP (ind, 0)) && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode) - && GET_CODE (XEXP (ind, 1)) == CONST_INT + && CONST_INT_P (XEXP (ind, 1)) && INTVAL (XEXP (ind, 1)) > -1024 && INTVAL (XEXP (ind, 1)) < 1024 && (INTVAL (XEXP (ind, 1)) & 3) == 0) @@ -9595,7 +9595,7 @@ neon_vector_mem_operand (rtx op, int type) return FALSE; /* Constants are converted into offsets from labels. */ - if (GET_CODE (op) != MEM) + if (!MEM_P (op)) return FALSE; ind = XEXP (op, 0); @@ -9605,11 +9605,11 @@ neon_vector_mem_operand (rtx op, int type) || (GET_CODE (ind) == CONST && GET_CODE (XEXP (ind, 0)) == PLUS && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF - && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT))) + && CONST_INT_P (XEXP (XEXP (ind, 0), 1))))) return TRUE; /* Match: (mem (reg)). */ - if (GET_CODE (ind) == REG) + if (REG_P (ind)) return arm_address_register_rtx_p (ind, 0); /* Allow post-increment with Neon registers. */ @@ -9624,9 +9624,9 @@ neon_vector_mem_operand (rtx op, int type) (const)). */ if (type == 0 && GET_CODE (ind) == PLUS - && GET_CODE (XEXP (ind, 0)) == REG + && REG_P (XEXP (ind, 0)) && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode) - && GET_CODE (XEXP (ind, 1)) == CONST_INT + && CONST_INT_P (XEXP (ind, 1)) && INTVAL (XEXP (ind, 1)) > -1024 && INTVAL (XEXP (ind, 1)) < 1016 && (INTVAL (XEXP (ind, 1)) & 3) == 0) @@ -9653,7 +9653,7 @@ neon_struct_mem_operand (rtx op) return FALSE; /* Constants are converted into offsets from labels. */ - if (GET_CODE (op) != MEM) + if (!MEM_P (op)) return FALSE; ind = XEXP (op, 0); @@ -9663,11 +9663,11 @@ neon_struct_mem_operand (rtx op) || (GET_CODE (ind) == CONST && GET_CODE (XEXP (ind, 0)) == PLUS && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF - && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT))) + && CONST_INT_P (XEXP (XEXP (ind, 0), 1))))) return TRUE; /* Match: (mem (reg)). */ - if (GET_CODE (ind) == REG) + if (REG_P (ind)) return arm_address_register_rtx_p (ind, 0); /* vldm/vstm allows POST_INC (ia) and PRE_DEC (db). */ @@ -9902,12 +9902,12 @@ adjacent_mem_locations (rtx a, rtx b) if (volatile_refs_p (a) || volatile_refs_p (b)) return 0; - if ((GET_CODE (XEXP (a, 0)) == REG + if ((REG_P (XEXP (a, 0)) || (GET_CODE (XEXP (a, 0)) == PLUS - && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT)) - && (GET_CODE (XEXP (b, 0)) == REG + && CONST_INT_P (XEXP (XEXP (a, 0), 1)))) + && (REG_P (XEXP (b, 0)) || (GET_CODE (XEXP (b, 0)) == PLUS - && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT))) + && CONST_INT_P (XEXP (XEXP (b, 0), 1))))) { HOST_WIDE_INT val0 = 0, val1 = 0; rtx reg0, reg1; @@ -10291,7 +10291,7 @@ load_multiple_sequence (rtx *operands, int nops, int *regs, int *saved_order, if (GET_CODE (operands[nops + i]) == SUBREG) operands[nops + i] = alter_subreg (operands + (nops + i)); - gcc_assert (GET_CODE (operands[nops + i]) == MEM); + gcc_assert (MEM_P (operands[nops + i])); /* Don't reorder volatile memory references; it doesn't seem worth looking for the case where the order is ok anyway. */ @@ -10300,16 +10300,15 @@ load_multiple_sequence (rtx *operands, int nops, int *regs, int *saved_order, offset = const0_rtx; - if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG + if ((REG_P (reg = XEXP (operands[nops + i], 0)) || (GET_CODE (reg) == SUBREG - && GET_CODE (reg = SUBREG_REG (reg)) == REG)) + && REG_P (reg = SUBREG_REG (reg)))) || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS - && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0)) - == REG) + && ((REG_P (reg = XEXP (XEXP (operands[nops + i], 0), 0))) || (GET_CODE (reg) == SUBREG - && GET_CODE (reg = SUBREG_REG (reg)) == REG)) - && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1)) - == CONST_INT))) + && REG_P (reg = SUBREG_REG (reg)))) + && (CONST_INT_P (offset + = XEXP (XEXP (operands[nops + i], 0), 1))))) { if (i == 0) { @@ -10322,7 +10321,7 @@ load_multiple_sequence (rtx *operands, int nops, int *regs, int *saved_order, /* Not addressed from the same base register. */ return 0; - unsorted_regs[i] = (GET_CODE (operands[i]) == REG + unsorted_regs[i] = (REG_P (operands[i]) ? REGNO (operands[i]) : REGNO (SUBREG_REG (operands[i]))); @@ -10444,7 +10443,7 @@ store_multiple_sequence (rtx *operands, int nops, int nops_total, if (GET_CODE (operands[nops + i]) == SUBREG) operands[nops + i] = alter_subreg (operands + (nops + i)); - gcc_assert (GET_CODE (operands[nops + i]) == MEM); + gcc_assert (MEM_P (operands[nops + i])); /* Don't reorder volatile memory references; it doesn't seem worth looking for the case where the order is ok anyway. */ @@ -10453,18 +10452,17 @@ store_multiple_sequence (rtx *operands, int nops, int nops_total, offset = const0_rtx; - if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG + if ((REG_P (reg = XEXP (operands[nops + i], 0)) || (GET_CODE (reg) == SUBREG - && GET_CODE (reg = SUBREG_REG (reg)) == REG)) + && REG_P (reg = SUBREG_REG (reg)))) || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS - && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0)) - == REG) + && ((REG_P (reg = XEXP (XEXP (operands[nops + i], 0), 0))) || (GET_CODE (reg) == SUBREG - && GET_CODE (reg = SUBREG_REG (reg)) == REG)) - && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1)) - == CONST_INT))) + && REG_P (reg = SUBREG_REG (reg)))) + && (CONST_INT_P (offset + = XEXP (XEXP (operands[nops + i], 0), 1))))) { - unsorted_reg_rtxs[i] = (GET_CODE (operands[i]) == REG + unsorted_reg_rtxs[i] = (REG_P (operands[i]) ? operands[i] : SUBREG_REG (operands[i])); unsorted_regs[i] = REGNO (unsorted_reg_rtxs[i]); @@ -10950,7 +10948,7 @@ gen_const_stm_seq (rtx *operands, int nops) unaligned copies on processors which support unaligned semantics for those instructions. INTERLEAVE_FACTOR can be used to attempt to hide load latency (using more registers) by doing e.g. load/load/store/store for a factor of 2. - An interleave factor of 1 (the minimum) will perform no interleaving. + An interleave factor of 1 (the minimum) will perform no interleaving. Load/store multiple are used for aligned addresses where possible. */ static void @@ -11285,8 +11283,8 @@ arm_gen_movmemqi (rtx *operands) rtx part_bytes_reg = NULL; rtx mem; - if (GET_CODE (operands[2]) != CONST_INT - || GET_CODE (operands[3]) != CONST_INT + if (!CONST_INT_P (operands[2]) + || !CONST_INT_P (operands[3]) || INTVAL (operands[2]) > 64) return 0; @@ -11631,13 +11629,13 @@ arm_select_cc_mode (enum rtx_code op, rtx x, rtx y) equalities and unsigned inequalities). */ if (GET_MODE (x) == SImode && GET_CODE (x) == ASHIFT - && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24 + && CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) == 24 && GET_CODE (XEXP (x, 0)) == SUBREG - && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM + && MEM_P (SUBREG_REG (XEXP (x, 0))) && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode && (op == EQ || op == NE || op == GEU || op == GTU || op == LTU || op == LEU) - && GET_CODE (y) == CONST_INT) + && CONST_INT_P (y)) return CC_Zmode; /* A construct for a conditional compare, if the false arm contains @@ -11827,7 +11825,7 @@ arm_reload_in_hi (rtx *operands) ref = SUBREG_REG (ref); } - if (GET_CODE (ref) == REG) + if (REG_P (ref)) { /* We have a pseudo which has been spilt onto the stack; there are two cases here: the first where there is a simple @@ -11847,7 +11845,7 @@ arm_reload_in_hi (rtx *operands) /* Handle the case where the address is too complex to be offset by 1. */ if (GET_CODE (base) == MINUS - || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT)) + || (GET_CODE (base) == PLUS && !CONST_INT_P (XEXP (base, 1)))) { rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); @@ -11944,7 +11942,7 @@ arm_reload_out_hi (rtx *operands) ref = SUBREG_REG (ref); } - if (GET_CODE (ref) == REG) + if (REG_P (ref)) { /* We have a pseudo which has been spilt onto the stack; there are two cases here: the first where there is a simple @@ -11966,7 +11964,7 @@ arm_reload_out_hi (rtx *operands) /* Handle the case where the address is too complex to be offset by 1. */ if (GET_CODE (base) == MINUS - || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT)) + || (GET_CODE (base) == PLUS && !CONST_INT_P (XEXP (base, 1)))) { rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); @@ -12351,7 +12349,7 @@ is_jump_table (rtx insn) && ((table = next_real_insn (JUMP_LABEL (insn))) == next_real_insn (insn)) && table != NULL - && GET_CODE (table) == JUMP_INSN + && JUMP_P (table) && (GET_CODE (PATTERN (table)) == ADDR_VEC || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC)) return table; @@ -12497,7 +12495,7 @@ add_minipool_forward_ref (Mfix *fix) { if (GET_CODE (fix->value) == GET_CODE (mp->value) && fix->mode == mp->mode - && (GET_CODE (fix->value) != CODE_LABEL + && (!LABEL_P (fix->value) || (CODE_LABEL_NUMBER (fix->value) == CODE_LABEL_NUMBER (mp->value))) && rtx_equal_p (fix->value, mp->value)) @@ -12674,7 +12672,7 @@ add_minipool_backward_ref (Mfix *fix) { if (GET_CODE (fix->value) == GET_CODE (mp->value) && fix->mode == mp->mode - && (GET_CODE (fix->value) != CODE_LABEL + && (!LABEL_P (fix->value) || (CODE_LABEL_NUMBER (fix->value) == CODE_LABEL_NUMBER (mp->value))) && rtx_equal_p (fix->value, mp->value) @@ -12906,7 +12904,7 @@ arm_barrier_cost (rtx insn) int base_cost = 50; rtx next = next_nonnote_insn (insn); - if (next != NULL && GET_CODE (next) == CODE_LABEL) + if (next != NULL && LABEL_P (next)) base_cost -= 20; switch (GET_CODE (insn)) @@ -12957,7 +12955,7 @@ create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address) /* This code shouldn't have been called if there was a natural barrier within range. */ - gcc_assert (GET_CODE (from) != BARRIER); + gcc_assert (!BARRIER_P (from)); /* Count the length of this insn. This must stay in sync with the code that pushes minipool fixes. */ @@ -13124,8 +13122,8 @@ arm_const_double_inline_cost (rtx val) lowpart = gen_lowpart (SImode, val); highpart = gen_highpart_mode (SImode, mode, val); - gcc_assert (GET_CODE (lowpart) == CONST_INT); - gcc_assert (GET_CODE (highpart) == CONST_INT); + gcc_assert (CONST_INT_P (lowpart)); + gcc_assert (CONST_INT_P (highpart)); return (arm_gen_constant (SET, SImode, NULL_RTX, INTVAL (lowpart), NULL_RTX, NULL_RTX, 0, 0) @@ -13151,7 +13149,7 @@ arm_const_double_by_parts (rtx val) part = gen_highpart_mode (SImode, mode, val); - gcc_assert (GET_CODE (part) == CONST_INT); + gcc_assert (CONST_INT_P (part)); if (const_ok_for_arm (INTVAL (part)) || const_ok_for_arm (~INTVAL (part))) @@ -13159,7 +13157,7 @@ arm_const_double_by_parts (rtx val) part = gen_lowpart (SImode, val); - gcc_assert (GET_CODE (part) == CONST_INT); + gcc_assert (CONST_INT_P (part)); if (const_ok_for_arm (INTVAL (part)) || const_ok_for_arm (~INTVAL (part))) @@ -13181,14 +13179,14 @@ arm_const_double_by_immediates (rtx val) part = gen_highpart_mode (SImode, mode, val); - gcc_assert (GET_CODE (part) == CONST_INT); + gcc_assert (CONST_INT_P (part)); if (!const_ok_for_arm (INTVAL (part))) return false; part = gen_lowpart (SImode, val); - gcc_assert (GET_CODE (part) == CONST_INT); + gcc_assert (CONST_INT_P (part)); if (!const_ok_for_arm (INTVAL (part))) return false; @@ -13236,7 +13234,7 @@ note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes) push_minipool_fix (insn, address, recog_data.operand_loc[opno], recog_data.operand_mode[opno], op); } - else if (GET_CODE (op) == MEM + else if (MEM_P (op) && GET_CODE (XEXP (op, 0)) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0))) { @@ -13336,7 +13334,7 @@ thumb2_reorg (void) break; case MINUS: - /* RSBS <Rd>,<Rn>,#0 + /* RSBS <Rd>,<Rn>,#0 Not handled here: see NEG below. */ /* SUBS <Rd>,<Rn>,#<imm3> SUBS <Rdn>,#<imm8> @@ -13475,13 +13473,13 @@ arm_reorg (void) /* The first insn must always be a note, or the code below won't scan it properly. */ insn = get_insns (); - gcc_assert (GET_CODE (insn) == NOTE); + gcc_assert (NOTE_P (insn)); minipool_pad = 0; /* Scan all the insns and record the operands that will need fixing. */ for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn)) { - if (GET_CODE (insn) == BARRIER) + if (BARRIER_P (insn)) push_minipool_barrier (insn, address); else if (INSN_P (insn)) { @@ -13517,7 +13515,7 @@ arm_reorg (void) Mfix * this_fix; /* Skip any further barriers before the next fix. */ - while (fix && GET_CODE (fix->insn) == BARRIER) + while (fix && BARRIER_P (fix->insn)) fix = fix->next; /* No more fixes. */ @@ -13528,7 +13526,7 @@ arm_reorg (void) for (ftmp = fix; ftmp; ftmp = ftmp->next) { - if (GET_CODE (ftmp->insn) == BARRIER) + if (BARRIER_P (ftmp->insn)) { if (ftmp->address >= minipool_vector_head->max_address) break; @@ -13588,7 +13586,7 @@ arm_reorg (void) while (ftmp) { - if (GET_CODE (ftmp->insn) != BARRIER + if (!BARRIER_P (ftmp->insn) && ((ftmp->minipool = add_minipool_backward_ref (ftmp)) == NULL)) break; @@ -13600,7 +13598,7 @@ arm_reorg (void) up and adding the constants to the pool itself. */ for (this_fix = fix; this_fix && ftmp != this_fix; this_fix = this_fix->next) - if (GET_CODE (this_fix->insn) != BARRIER) + if (!BARRIER_P (this_fix->insn)) { rtx addr = plus_constant (Pmode, @@ -13743,7 +13741,7 @@ vfp_output_fstmd (rtx * operands) strcpy (pattern, "fstmfdd%?\t%m0!, {%P1"); p = strlen (pattern); - gcc_assert (GET_CODE (operands[1]) == REG); + gcc_assert (REG_P (operands[1])); base = (REGNO (operands[1]) - FIRST_VFP_REGNUM) / 2; for (i = 1; i < XVECLEN (operands[2], 0); i++) @@ -14084,7 +14082,7 @@ output_move_double (rtx *operands, bool emit, int *count) FIXME: IWMMXT allows offsets larger than ldrd can handle, fix these up with a pair of ldr. */ if (TARGET_THUMB2 - || GET_CODE (otherops[2]) != CONST_INT + || !CONST_INT_P (otherops[2]) || (INTVAL (otherops[2]) > -256 && INTVAL (otherops[2]) < 256)) { @@ -14110,7 +14108,7 @@ output_move_double (rtx *operands, bool emit, int *count) FIXME: IWMMXT allows offsets larger than ldrd can handle, fix these up with a pair of ldr. */ if (TARGET_THUMB2 - || GET_CODE (otherops[2]) != CONST_INT + || !CONST_INT_P (otherops[2]) || (INTVAL (otherops[2]) > -256 && INTVAL (otherops[2]) < 256)) { @@ -14164,7 +14162,7 @@ output_move_double (rtx *operands, bool emit, int *count) if (GET_CODE (XEXP (operands[1], 0)) == PLUS) { - if (GET_CODE (otherops[2]) == CONST_INT && !TARGET_LDRD) + if (CONST_INT_P (otherops[2]) && !TARGET_LDRD) { switch ((int) INTVAL (otherops[2])) { @@ -14189,9 +14187,9 @@ output_move_double (rtx *operands, bool emit, int *count) otherops[0] = gen_rtx_REG(SImode, REGNO(operands[0]) + 1); operands[1] = otherops[0]; if (TARGET_LDRD - && (GET_CODE (otherops[2]) == REG + && (REG_P (otherops[2]) || TARGET_THUMB2 - || (GET_CODE (otherops[2]) == CONST_INT + || (CONST_INT_P (otherops[2]) && INTVAL (otherops[2]) > -256 && INTVAL (otherops[2]) < 256))) { @@ -14227,7 +14225,7 @@ output_move_double (rtx *operands, bool emit, int *count) return ""; } - if (GET_CODE (otherops[2]) == CONST_INT) + if (CONST_INT_P (otherops[2])) { if (emit) { @@ -14344,7 +14342,7 @@ output_move_double (rtx *operands, bool emit, int *count) /* IWMMXT allows offsets larger than ldrd can handle, fix these up with a pair of ldr. */ if (!TARGET_THUMB2 - && GET_CODE (otherops[2]) == CONST_INT + && CONST_INT_P (otherops[2]) && (INTVAL(otherops[2]) <= -256 || INTVAL(otherops[2]) >= 256)) { @@ -14383,7 +14381,7 @@ output_move_double (rtx *operands, bool emit, int *count) case PLUS: otherops[2] = XEXP (XEXP (operands[0], 0), 1); - if (GET_CODE (otherops[2]) == CONST_INT && !TARGET_LDRD) + if (CONST_INT_P (otherops[2]) && !TARGET_LDRD) { switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1))) { @@ -14408,9 +14406,9 @@ output_move_double (rtx *operands, bool emit, int *count) } } if (TARGET_LDRD - && (GET_CODE (otherops[2]) == REG + && (REG_P (otherops[2]) || TARGET_THUMB2 - || (GET_CODE (otherops[2]) == CONST_INT + || (CONST_INT_P (otherops[2]) && INTVAL (otherops[2]) > -256 && INTVAL (otherops[2]) < 256))) { @@ -14760,10 +14758,10 @@ arm_address_offset_is_imm (rtx insn) addr = XEXP (mem, 0); - if (GET_CODE (addr) == REG + if (REG_P (addr) || (GET_CODE (addr) == PLUS - && GET_CODE (XEXP (addr, 0)) == REG - && GET_CODE (XEXP (addr, 1)) == CONST_INT)) + && REG_P (XEXP (addr, 0)) + && CONST_INT_P (XEXP (addr, 1)))) return 1; else return 0; @@ -16909,7 +16907,7 @@ arm_print_operand (FILE *stream, rtx x, int code) return; case 'B': - if (GET_CODE (x) == CONST_INT) + if (CONST_INT_P (x)) { HOST_WIDE_INT val; val = ARM_SIGN_EXTEND (~INTVAL (x)); @@ -16990,14 +16988,14 @@ arm_print_operand (FILE *stream, rtx x, int code) The 'Q' and 'R' constraints are also available for 64-bit constants. */ case 'Q': - if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) + if (CONST_INT_P (x) || CONST_DOUBLE_P (x)) { rtx part = gen_lowpart (SImode, x); fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, INTVAL (part)); return; } - if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) + if (!REG_P (x) || REGNO (x) > LAST_ARM_REGNUM) { output_operand_lossage ("invalid operand for code '%c'", code); return; @@ -17007,7 +17005,7 @@ arm_print_operand (FILE *stream, rtx x, int code) return; case 'R': - if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) + if (CONST_INT_P (x) || CONST_DOUBLE_P (x)) { enum machine_mode mode = GET_MODE (x); rtx part; @@ -17019,7 +17017,7 @@ arm_print_operand (FILE *stream, rtx x, int code) return; } - if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) + if (!REG_P (x) || REGNO (x) > LAST_ARM_REGNUM) { output_operand_lossage ("invalid operand for code '%c'", code); return; @@ -17029,7 +17027,7 @@ arm_print_operand (FILE *stream, rtx x, int code) return; case 'H': - if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) + if (!REG_P (x) || REGNO (x) > LAST_ARM_REGNUM) { output_operand_lossage ("invalid operand for code '%c'", code); return; @@ -17039,7 +17037,7 @@ arm_print_operand (FILE *stream, rtx x, int code) return; case 'J': - if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) + if (!REG_P (x) || REGNO (x) > LAST_ARM_REGNUM) { output_operand_lossage ("invalid operand for code '%c'", code); return; @@ -17049,7 +17047,7 @@ arm_print_operand (FILE *stream, rtx x, int code) return; case 'K': - if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) + if (!REG_P (x) || REGNO (x) > LAST_ARM_REGNUM) { output_operand_lossage ("invalid operand for code '%c'", code); return; @@ -17060,7 +17058,7 @@ arm_print_operand (FILE *stream, rtx x, int code) case 'm': asm_fprintf (stream, "%r", - GET_CODE (XEXP (x, 0)) == REG + REG_P (XEXP (x, 0)) ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0))); return; @@ -17128,7 +17126,7 @@ arm_print_operand (FILE *stream, rtx x, int code) return; case 'U': - if (GET_CODE (x) != REG + if (!REG_P (x) || REGNO (x) < FIRST_IWMMXT_GR_REGNUM || REGNO (x) > LAST_IWMMXT_GR_REGNUM) /* Bad value for wCG register number. */ @@ -17143,7 +17141,7 @@ arm_print_operand (FILE *stream, rtx x, int code) /* Print an iWMMXt control register name. */ case 'w': - if (GET_CODE (x) != CONST_INT + if (!CONST_INT_P (x) || INTVAL (x) < 0 || INTVAL (x) >= 16) /* Bad value for wC register number. */ @@ -17173,7 +17171,7 @@ arm_print_operand (FILE *stream, rtx x, int code) int mode = GET_MODE (x); int regno; - if (GET_MODE_SIZE (mode) != 8 || GET_CODE (x) != REG) + if (GET_MODE_SIZE (mode) != 8 || !REG_P (x)) { output_operand_lossage ("invalid operand for code '%c'", code); return; @@ -17204,7 +17202,7 @@ arm_print_operand (FILE *stream, rtx x, int code) return; } - if (GET_CODE (x) != REG + if (!REG_P (x) || !IS_VFP_REGNUM (REGNO (x))) { output_operand_lossage ("invalid operand for code '%c'", code); @@ -17234,7 +17232,7 @@ arm_print_operand (FILE *stream, rtx x, int code) int regno; if ((GET_MODE_SIZE (mode) != 16 - && GET_MODE_SIZE (mode) != 32) || GET_CODE (x) != REG) + && GET_MODE_SIZE (mode) != 32) || !REG_P (x)) { output_operand_lossage ("invalid operand for code '%c'", code); return; @@ -17314,7 +17312,7 @@ arm_print_operand (FILE *stream, rtx x, int code) bool postinc = FALSE; unsigned align, memsize, align_bits; - gcc_assert (GET_CODE (x) == MEM); + gcc_assert (MEM_P (x)); addr = XEXP (x, 0); if (GET_CODE (addr) == POST_INC) { @@ -17353,9 +17351,9 @@ arm_print_operand (FILE *stream, rtx x, int code) { rtx addr; - gcc_assert (GET_CODE (x) == MEM); + gcc_assert (MEM_P (x)); addr = XEXP (x, 0); - gcc_assert (GET_CODE (addr) == REG); + gcc_assert (REG_P (addr)); asm_fprintf (stream, "[%r]", REGNO (addr)); } return; @@ -17366,7 +17364,7 @@ arm_print_operand (FILE *stream, rtx x, int code) int mode = GET_MODE (x); int regno; - if (GET_MODE_SIZE (mode) != 4 || GET_CODE (x) != REG) + if (GET_MODE_SIZE (mode) != 4 || !REG_P (x)) { output_operand_lossage ("invalid operand for code '%c'", code); return; @@ -17385,7 +17383,7 @@ arm_print_operand (FILE *stream, rtx x, int code) return; case 'v': - gcc_assert (GET_CODE (x) == CONST_DOUBLE); + gcc_assert (CONST_DOUBLE_P (x)); fprintf (stream, "#%d", vfp3_const_double_for_fract_bits (x)); return; @@ -17396,7 +17394,7 @@ arm_print_operand (FILE *stream, rtx x, int code) int mode = GET_MODE (x); int regno; - if (GET_MODE_SIZE (mode) != 2 || GET_CODE (x) != REG) + if (GET_MODE_SIZE (mode) != 2 || !REG_P (x)) { output_operand_lossage ("invalid operand for code '%c'", code); return; @@ -17467,15 +17465,15 @@ arm_print_operand_address (FILE *stream, rtx x) { int is_minus = GET_CODE (x) == MINUS; - if (GET_CODE (x) == REG) + if (REG_P (x)) asm_fprintf (stream, "[%r]", REGNO (x)); else if (GET_CODE (x) == PLUS || is_minus) { rtx base = XEXP (x, 0); rtx index = XEXP (x, 1); HOST_WIDE_INT offset = 0; - if (GET_CODE (base) != REG - || (GET_CODE (index) == REG && REGNO (index) == SP_REGNUM)) + if (!REG_P (base) + || (REG_P (index) && REGNO (index) == SP_REGNUM)) { /* Ensure that BASE is a register. */ /* (one of them must be). */ @@ -17523,7 +17521,7 @@ arm_print_operand_address (FILE *stream, rtx x) { extern enum machine_mode output_memory_reference_mode; - gcc_assert (GET_CODE (XEXP (x, 0)) == REG); + gcc_assert (REG_P (XEXP (x, 0))); if (GET_CODE (x) == PRE_DEC || GET_CODE (x) == PRE_INC) asm_fprintf (stream, "[%r, #%s%d]!", @@ -17539,7 +17537,7 @@ arm_print_operand_address (FILE *stream, rtx x) else if (GET_CODE (x) == PRE_MODIFY) { asm_fprintf (stream, "[%r, ", REGNO (XEXP (x, 0))); - if (GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT) + if (CONST_INT_P (XEXP (XEXP (x, 1), 1))) asm_fprintf (stream, "#%wd]!", INTVAL (XEXP (XEXP (x, 1), 1))); else @@ -17549,7 +17547,7 @@ arm_print_operand_address (FILE *stream, rtx x) else if (GET_CODE (x) == POST_MODIFY) { asm_fprintf (stream, "[%r], ", REGNO (XEXP (x, 0))); - if (GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT) + if (CONST_INT_P (XEXP (XEXP (x, 1), 1))) asm_fprintf (stream, "#%wd", INTVAL (XEXP (XEXP (x, 1), 1))); else @@ -17560,14 +17558,14 @@ arm_print_operand_address (FILE *stream, rtx x) } else { - if (GET_CODE (x) == REG) + if (REG_P (x)) asm_fprintf (stream, "[%r]", REGNO (x)); else if (GET_CODE (x) == POST_INC) asm_fprintf (stream, "%r!", REGNO (XEXP (x, 0))); else if (GET_CODE (x) == PLUS) { - gcc_assert (GET_CODE (XEXP (x, 0)) == REG); - if (GET_CODE (XEXP (x, 1)) == CONST_INT) + gcc_assert (REG_P (XEXP (x, 0))); + if (CONST_INT_P (XEXP (x, 1))) asm_fprintf (stream, "[%r, #%wd]", REGNO (XEXP (x, 0)), INTVAL (XEXP (x, 1))); @@ -17930,7 +17928,7 @@ thumb2_final_prescan_insn (rtx insn) return; /* Conditional jumps are implemented directly. */ - if (GET_CODE (insn) == JUMP_INSN) + if (JUMP_P (insn)) return; predicate = COND_EXEC_TEST (body); @@ -17947,7 +17945,7 @@ thumb2_final_prescan_insn (rtx insn) /* Jumping into the middle of an IT block is illegal, so a label or barrier terminates the block. */ - if (GET_CODE (insn) != INSN && GET_CODE(insn) != JUMP_INSN) + if (!NONJUMP_INSN_P (insn) && !JUMP_P (insn)) break; body = PATTERN (insn); @@ -17976,7 +17974,7 @@ thumb2_final_prescan_insn (rtx insn) arm_condexec_masklen += n; /* A jump must be the last instruction in a conditional block. */ - if (GET_CODE(insn) == JUMP_INSN) + if (JUMP_P (insn)) break; } /* Restore recog_data (getting the attributes of other insns can @@ -18024,12 +18022,12 @@ arm_final_prescan_insn (rtx insn) if (simplejump_p (insn)) { start_insn = next_nonnote_insn (start_insn); - if (GET_CODE (start_insn) == BARRIER) + if (BARRIER_P (start_insn)) { /* XXX Isn't this always a barrier? */ start_insn = next_nonnote_insn (start_insn); } - if (GET_CODE (start_insn) == CODE_LABEL + if (LABEL_P (start_insn) && CODE_LABEL_NUMBER (start_insn) == arm_target_label && LABEL_NUSES (start_insn) == 1) reverse = TRUE; @@ -18039,9 +18037,9 @@ arm_final_prescan_insn (rtx insn) else if (ANY_RETURN_P (body)) { start_insn = next_nonnote_insn (start_insn); - if (GET_CODE (start_insn) == BARRIER) + if (BARRIER_P (start_insn)) start_insn = next_nonnote_insn (start_insn); - if (GET_CODE (start_insn) == CODE_LABEL + if (LABEL_P (start_insn) && CODE_LABEL_NUMBER (start_insn) == arm_target_label && LABEL_NUSES (start_insn) == 1) { @@ -18057,7 +18055,7 @@ arm_final_prescan_insn (rtx insn) } gcc_assert (!arm_ccfsm_state || reverse); - if (GET_CODE (insn) != JUMP_INSN) + if (!JUMP_P (insn)) return; /* This jump might be paralleled with a clobber of the condition codes @@ -18158,7 +18156,7 @@ arm_final_prescan_insn (rtx insn) if the following two insns are a barrier and the target label. */ this_insn = next_nonnote_insn (this_insn); - if (this_insn && GET_CODE (this_insn) == BARRIER) + if (this_insn && BARRIER_P (this_insn)) this_insn = next_nonnote_insn (this_insn); if (this_insn && this_insn == label @@ -18244,8 +18242,8 @@ arm_final_prescan_insn (rtx insn) { this_insn = next_nonnote_insn (this_insn); gcc_assert (!this_insn - || (GET_CODE (this_insn) != BARRIER - && GET_CODE (this_insn) != CODE_LABEL)); + || (!BARRIER_P (this_insn) + && !LABEL_P (this_insn))); } if (!this_insn) { @@ -18444,7 +18442,7 @@ arm_debugger_arg_offset (int value, rtx addr) return 0; /* We can only cope with the case where the address is held in a register. */ - if (GET_CODE (addr) != REG) + if (!REG_P (addr)) return 0; /* If we are using the frame pointer to point at the argument, then @@ -18491,13 +18489,13 @@ arm_debugger_arg_offset (int value, rtx addr) for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) { - if ( GET_CODE (insn) == INSN + if ( NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == SET && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr) && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS - && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG + && REG_P (XEXP (XEXP (PATTERN (insn), 1), 0)) && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM - && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT + && CONST_INT_P (XEXP (XEXP (PATTERN (insn), 1), 1)) ) { value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1)); @@ -20872,7 +20870,7 @@ arm_expand_builtin (tree exp, op0 = expand_normal (arg0); op1 = expand_normal (arg1); op2 = expand_normal (arg2); - if (GET_CODE (op2) == CONST_INT) + if (CONST_INT_P (op2)) { icode = CODE_FOR_iwmmxt_waligni; tmode = insn_data[icode].operand[0].mode; @@ -21814,7 +21812,7 @@ thumb_far_jump_used_p (void) insn with the far jump attribute set. */ for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) { - if (GET_CODE (insn) == JUMP_INSN + if (JUMP_P (insn) /* Ignore tablejump patterns. */ && GET_CODE (PATTERN (insn)) != ADDR_VEC && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC @@ -22982,7 +22980,7 @@ thumb1_output_interwork (void) const char * name; FILE *f = asm_out_file; - gcc_assert (GET_CODE (DECL_RTL (current_function_decl)) == MEM); + gcc_assert (MEM_P (DECL_RTL (current_function_decl))); gcc_assert (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0)) == SYMBOL_REF); name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); @@ -23026,8 +23024,8 @@ thumb_load_double_from_address (rtx *operands) rtx arg1; rtx arg2; - gcc_assert (GET_CODE (operands[0]) == REG); - gcc_assert (GET_CODE (operands[1]) == MEM); + gcc_assert (REG_P (operands[0])); + gcc_assert (MEM_P (operands[1])); /* Get the memory address. */ addr = XEXP (operands[1], 0); @@ -23067,10 +23065,10 @@ thumb_load_double_from_address (rtx *operands) else base = arg1, offset = arg2; - gcc_assert (GET_CODE (base) == REG); + gcc_assert (REG_P (base)); /* Catch the case of <address> = <reg> + <reg> */ - if (GET_CODE (offset) == REG) + if (REG_P (offset)) { int reg_offset = REGNO (offset); int reg_base = REGNO (base); @@ -23670,10 +23668,10 @@ arm_output_load_gr (rtx *operands) rtx wcgr; rtx sum; - if (GET_CODE (operands [1]) != MEM + if (!MEM_P (operands [1]) || GET_CODE (sum = XEXP (operands [1], 0)) != PLUS - || GET_CODE (reg = XEXP (sum, 0)) != REG - || GET_CODE (offset = XEXP (sum, 1)) != CONST_INT + || !REG_P (reg = XEXP (sum, 0)) + || !CONST_INT_P (offset = XEXP (sum, 1)) || ((INTVAL (offset) < 1024) && (INTVAL (offset) > -1024))) return "wldrw%?\t%0, %1"; @@ -23808,7 +23806,7 @@ arm_no_early_alu_shift_dep (rtx producer, rtx consumer) /* This is either an actual independent shift, or a shift applied to the first operand of another operation. We want the whole shift operation. */ - if (GET_CODE (early_op) == REG) + if (REG_P (early_op)) early_op = op; return !reg_overlap_mentioned_p (value, early_op); @@ -23841,7 +23839,7 @@ arm_no_early_alu_shift_value_dep (rtx producer, rtx consumer) /* This is either an actual independent shift, or a shift applied to the first operand of another operation. We want the value being shifted, in either case. */ - if (GET_CODE (early_op) != REG) + if (!REG_P (early_op)) early_op = XEXP (early_op, 0); return !reg_overlap_mentioned_p (value, early_op); @@ -24341,7 +24339,7 @@ arm_unwind_emit_sequence (FILE * asm_out_file, rtx p) /* First insn will adjust the stack pointer. */ if (GET_CODE (e) != SET - || GET_CODE (XEXP (e, 0)) != REG + || !REG_P (XEXP (e, 0)) || REGNO (XEXP (e, 0)) != SP_REGNUM || GET_CODE (XEXP (e, 1)) != PLUS) abort (); @@ -24385,8 +24383,8 @@ arm_unwind_emit_sequence (FILE * asm_out_file, rtx p) Where <addr> is (reg:SP) or (plus (reg:SP) (const_int)). */ e = XVECEXP (p, 0, i); if (GET_CODE (e) != SET - || GET_CODE (XEXP (e, 0)) != MEM - || GET_CODE (XEXP (e, 1)) != REG) + || !MEM_P (XEXP (e, 0)) + || !REG_P (XEXP (e, 1))) abort (); reg = REGNO (XEXP (e, 1)); @@ -24408,14 +24406,14 @@ arm_unwind_emit_sequence (FILE * asm_out_file, rtx p) if (GET_CODE (e) == PLUS) { offset += reg_size; - if (GET_CODE (XEXP (e, 0)) != REG + if (!REG_P (XEXP (e, 0)) || REGNO (XEXP (e, 0)) != SP_REGNUM - || GET_CODE (XEXP (e, 1)) != CONST_INT + || !CONST_INT_P (XEXP (e, 1)) || offset != INTVAL (XEXP (e, 1))) abort (); } else if (i != 1 - || GET_CODE (e) != REG + || !REG_P (e) || REGNO (e) != SP_REGNUM) abort (); #endif @@ -24439,7 +24437,7 @@ arm_unwind_emit_set (FILE * asm_out_file, rtx p) case MEM: /* Pushing a single register. */ if (GET_CODE (XEXP (e0, 0)) != PRE_DEC - || GET_CODE (XEXP (XEXP (e0, 0), 0)) != REG + || !REG_P (XEXP (XEXP (e0, 0), 0)) || REGNO (XEXP (XEXP (e0, 0), 0)) != SP_REGNUM) abort (); @@ -24456,9 +24454,9 @@ arm_unwind_emit_set (FILE * asm_out_file, rtx p) { /* A stack increment. */ if (GET_CODE (e1) != PLUS - || GET_CODE (XEXP (e1, 0)) != REG + || !REG_P (XEXP (e1, 0)) || REGNO (XEXP (e1, 0)) != SP_REGNUM - || GET_CODE (XEXP (e1, 1)) != CONST_INT) + || !CONST_INT_P (XEXP (e1, 1))) abort (); asm_fprintf (asm_out_file, "\t.pad #%wd\n", @@ -24470,8 +24468,8 @@ arm_unwind_emit_set (FILE * asm_out_file, rtx p) if (GET_CODE (e1) == PLUS) { - if (GET_CODE (XEXP (e1, 0)) != REG - || GET_CODE (XEXP (e1, 1)) != CONST_INT) + if (!REG_P (XEXP (e1, 0)) + || !CONST_INT_P (XEXP (e1, 1))) abort (); reg = REGNO (XEXP (e1, 0)); offset = INTVAL (XEXP (e1, 1)); @@ -24479,7 +24477,7 @@ arm_unwind_emit_set (FILE * asm_out_file, rtx p) HARD_FRAME_POINTER_REGNUM, reg, offset); } - else if (GET_CODE (e1) == REG) + else if (REG_P (e1)) { reg = REGNO (e1); asm_fprintf (asm_out_file, "\t.setfp %r, %r\n", @@ -24488,15 +24486,15 @@ arm_unwind_emit_set (FILE * asm_out_file, rtx p) else abort (); } - else if (GET_CODE (e1) == REG && REGNO (e1) == SP_REGNUM) + else if (REG_P (e1) && REGNO (e1) == SP_REGNUM) { /* Move from sp to reg. */ asm_fprintf (asm_out_file, "\t.movsp %r\n", REGNO (e0)); } else if (GET_CODE (e1) == PLUS - && GET_CODE (XEXP (e1, 0)) == REG + && REG_P (XEXP (e1, 0)) && REGNO (XEXP (e1, 0)) == SP_REGNUM - && GET_CODE (XEXP (e1, 1)) == CONST_INT) + && CONST_INT_P (XEXP (e1, 1))) { /* Set reg to offset from sp. */ asm_fprintf (asm_out_file, "\t.movsp %r, #%d\n", @@ -24606,7 +24604,7 @@ arm_output_ttype (rtx x) fputs ("\t.word\t", asm_out_file); output_addr_const (asm_out_file, x); /* Use special relocations for symbol references. */ - if (GET_CODE (x) != CONST_INT) + if (!CONST_INT_P (x)) fputs ("(TARGET2)", asm_out_file); fputc ('\n', asm_out_file); @@ -25293,7 +25291,7 @@ vfp3_const_double_for_fract_bits (rtx operand) { REAL_VALUE_TYPE r0; - if (GET_CODE (operand) != CONST_DOUBLE) + if (!CONST_DOUBLE_P (operand)) return 0; REAL_VALUE_FROM_CONST_DOUBLE (r0, operand); @@ -26109,7 +26107,7 @@ arm_vectorize_vec_perm_const_ok (enum machine_mode vmode, bool arm_autoinc_modes_ok_p (enum machine_mode mode, enum arm_auto_incmodes code) { - /* If we are soft float and we do not have ldrd + /* If we are soft float and we do not have ldrd then all auto increment forms are ok. */ if (TARGET_SOFT_FLOAT && (TARGET_LDRD || GET_MODE_SIZE (mode) <= 4)) return true; @@ -26124,7 +26122,7 @@ arm_autoinc_modes_ok_p (enum machine_mode mode, enum arm_auto_incmodes code) { if (code != ARM_PRE_DEC) return true; - else + else return false; } @@ -26132,7 +26130,7 @@ arm_autoinc_modes_ok_p (enum machine_mode mode, enum arm_auto_incmodes code) case ARM_POST_DEC: case ARM_PRE_INC: - /* Without LDRD and mode size greater than + /* Without LDRD and mode size greater than word size, there is no point in auto-incrementing because ldm and stm will not have these forms. */ if (!TARGET_LDRD && GET_MODE_SIZE (mode) > 4) @@ -26406,7 +26404,7 @@ arm_emit_coreregs_64bit_shift (enum rtx_code code, rtx out, rtx in, } -/* Returns true if a valid comparison operation and makes +/* Returns true if a valid comparison operation and makes the operands in a form that is valid. */ bool arm_validize_comparison (rtx *comparison, rtx * op1, rtx * op2) @@ -26439,7 +26437,7 @@ arm_validize_comparison (rtx *comparison, rtx * op1, rtx * op2) if (!cmpdi_operand (*op2, mode)) *op2 = force_reg (mode, *op2); return true; - + case SFmode: case DFmode: if (!arm_float_compare_operand (*op1, mode)) @@ -26450,7 +26448,7 @@ arm_validize_comparison (rtx *comparison, rtx * op1, rtx * op2) default: break; } - + return false; } diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 8acde0e..5f34f2a 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -1262,8 +1262,8 @@ enum reg_class && CONSTANT_P (X)) \ ? GENERAL_REGS : \ (((MODE) == HImode && ! arm_arch4 \ - && (GET_CODE (X) == MEM \ - || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \ + && (MEM_P (X) \ + || ((REG_P (X) || GET_CODE (X) == SUBREG) \ && true_regnum (X) == -1))) \ ? GENERAL_REGS : NO_REGS) \ : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))) @@ -1909,10 +1909,10 @@ enum arm_auto_incmodes REG_OK_FOR_INDEX_P (X) #define ARM_BASE_REGISTER_RTX_P(X) \ - (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X)) + (REG_P (X) && ARM_REG_OK_FOR_BASE_P (X)) #define ARM_INDEX_REGISTER_RTX_P(X) \ - (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X)) + (REG_P (X) && ARM_REG_OK_FOR_INDEX_P (X)) /* Specify the machine mode that this machine uses for the index in the tablejump instruction. */ diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 6a642bf..a60e659 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -607,9 +607,9 @@ " if (TARGET_THUMB1) { - if (GET_CODE (operands[1]) != REG) + if (!REG_P (operands[1])) operands[1] = force_reg (DImode, operands[1]); - if (GET_CODE (operands[2]) != REG) + if (!REG_P (operands[2])) operands[2] = force_reg (DImode, operands[2]); } " @@ -716,7 +716,7 @@ (match_operand:SI 2 "reg_or_int_operand" "")))] "TARGET_EITHER" " - if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT) + if (TARGET_32BIT && CONST_INT_P (operands[2])) { arm_split_constant (PLUS, SImode, NULL_RTX, INTVAL (operands[2]), operands[0], operands[1], @@ -764,7 +764,7 @@ subw%?\\t%0, %1, #%n2 #" "TARGET_32BIT - && GET_CODE (operands[2]) == CONST_INT + && CONST_INT_P (operands[2]) && !const_ok_for_op (INTVAL (operands[2]), PLUS) && (reload_completed || !arm_eliminable_register (operands[1]))" [(clobber (const_int 0))] @@ -799,7 +799,7 @@ \"#\" }; if ((which_alternative == 2 || which_alternative == 6) - && GET_CODE (operands[2]) == CONST_INT + && CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 0) return \"sub\\t%0, %1, #%n2\"; return asms[which_alternative]; @@ -1111,9 +1111,9 @@ " if (TARGET_THUMB1) { - if (GET_CODE (operands[1]) != REG) + if (!REG_P (operands[1])) operands[1] = force_reg (DImode, operands[1]); - if (GET_CODE (operands[2]) != REG) + if (!REG_P (operands[2])) operands[2] = force_reg (DImode, operands[2]); } " @@ -1207,7 +1207,7 @@ (match_operand:SI 2 "s_register_operand" "")))] "TARGET_EITHER" " - if (GET_CODE (operands[1]) == CONST_INT) + if (CONST_INT_P (operands[1])) { if (TARGET_32BIT) { @@ -1242,7 +1242,7 @@ sub%?\\t%0, %1, %2 sub%?\\t%0, %1, %2 #" - "&& (GET_CODE (operands[1]) == CONST_INT + "&& (CONST_INT_P (operands[1]) && !const_ok_for_arm (INTVAL (operands[1])))" [(clobber (const_int 0))] " @@ -2097,7 +2097,7 @@ " if (TARGET_32BIT) { - if (GET_CODE (operands[2]) == CONST_INT) + if (CONST_INT_P (operands[2])) { if (INTVAL (operands[2]) == 255 && arm_arch6) { @@ -2116,7 +2116,7 @@ } else /* TARGET_THUMB1 */ { - if (GET_CODE (operands[2]) != CONST_INT) + if (!CONST_INT_P (operands[2])) { rtx tmp = force_reg (SImode, operands[2]); if (rtx_equal_p (operands[0], operands[1])) @@ -2179,7 +2179,7 @@ bic%?\\t%0, %1, #%B2 #" "TARGET_32BIT - && GET_CODE (operands[2]) == CONST_INT + && CONST_INT_P (operands[2]) && !(const_ok_for_arm (INTVAL (operands[2])) || const_ok_for_arm (~INTVAL (operands[2])))" [(clobber (const_int 0))] @@ -2512,7 +2512,7 @@ { bool use_bfi = TRUE; - if (GET_CODE (operands[3]) == CONST_INT) + if (CONST_INT_P (operands[3])) { HOST_WIDE_INT val = INTVAL (operands[3]) & mask; @@ -2530,7 +2530,7 @@ if (use_bfi) { - if (GET_CODE (operands[3]) != REG) + if (!REG_P (operands[3])) operands[3] = force_reg (SImode, operands[3]); emit_insn (gen_insv_t2 (operands[0], operands[1], operands[2], @@ -2558,7 +2558,7 @@ else subtarget = target; - if (GET_CODE (operands[3]) == CONST_INT) + if (CONST_INT_P (operands[3])) { /* Since we are inserting a known constant, we may be able to reduce the number of bits that we have to clear so that @@ -2625,7 +2625,7 @@ /* Mask out any bits in operand[3] that are not needed. */ emit_insn (gen_andsi3 (op1, operands[3], op0)); - if (GET_CODE (op0) == CONST_INT + if (CONST_INT_P (op0) && (const_ok_for_arm (mask << start_bit) || const_ok_for_arm (~(mask << start_bit)))) { @@ -2634,7 +2634,7 @@ } else { - if (GET_CODE (op0) == CONST_INT) + if (CONST_INT_P (op0)) { rtx tmp = gen_reg_rtx (SImode); @@ -2871,7 +2871,7 @@ (match_operand:SI 2 "reg_or_int_operand" "")))] "TARGET_EITHER" " - if (GET_CODE (operands[2]) == CONST_INT) + if (CONST_INT_P (operands[2])) { if (TARGET_32BIT) { @@ -2905,7 +2905,7 @@ orn%?\\t%0, %1, #%B2 #" "TARGET_32BIT - && GET_CODE (operands[2]) == CONST_INT + && CONST_INT_P (operands[2]) && !(const_ok_for_arm (INTVAL (operands[2])) || (TARGET_THUMB2 && const_ok_for_arm (~INTVAL (operands[2]))))" [(clobber (const_int 0))] @@ -3010,7 +3010,7 @@ (xor:SI (match_operand:SI 1 "s_register_operand" "") (match_operand:SI 2 "reg_or_int_operand" "")))] "TARGET_EITHER" - "if (GET_CODE (operands[2]) == CONST_INT) + "if (CONST_INT_P (operands[2])) { if (TARGET_32BIT) { @@ -3042,7 +3042,7 @@ eor%?\\t%0, %1, %2 #" "TARGET_32BIT - && GET_CODE (operands[2]) == CONST_INT + && CONST_INT_P (operands[2]) && !const_ok_for_arm (INTVAL (operands[2]))" [(clobber (const_int 0))] { @@ -3542,7 +3542,7 @@ (match_operand:SI 2 "arm_rhs_operand" "")))] "TARGET_EITHER" " - if (GET_CODE (operands[2]) == CONST_INT + if (CONST_INT_P (operands[2]) && ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31) { emit_insn (gen_movsi (operands[0], const0_rtx)); @@ -3617,7 +3617,7 @@ (match_operand:SI 2 "arm_rhs_operand" "")))] "TARGET_EITHER" " - if (GET_CODE (operands[2]) == CONST_INT + if (CONST_INT_P (operands[2]) && ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31) operands[2] = GEN_INT (31); " @@ -3689,7 +3689,7 @@ (match_operand:SI 2 "arm_rhs_operand" "")))] "TARGET_EITHER" " - if (GET_CODE (operands[2]) == CONST_INT + if (CONST_INT_P (operands[2]) && ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31) { emit_insn (gen_movsi (operands[0], const0_rtx)); @@ -3713,7 +3713,7 @@ (match_operand:SI 2 "reg_or_int_operand" "")))] "TARGET_32BIT" " - if (GET_CODE (operands[2]) == CONST_INT) + if (CONST_INT_P (operands[2])) operands[2] = GEN_INT ((32 - INTVAL (operands[2])) % 32); else { @@ -3732,13 +3732,13 @@ " if (TARGET_32BIT) { - if (GET_CODE (operands[2]) == CONST_INT + if (CONST_INT_P (operands[2]) && ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31) operands[2] = GEN_INT (INTVAL (operands[2]) % 32); } else /* TARGET_THUMB1 */ { - if (GET_CODE (operands [2]) == CONST_INT) + if (CONST_INT_P (operands [2])) operands [2] = force_reg (SImode, operands[2]); } " @@ -4595,7 +4595,7 @@ rtx a = XEXP (mem, 0); /* This can happen due to bugs in reload. */ - if (GET_CODE (a) == REG && REGNO (a) == SP_REGNUM) + if (REG_P (a) && REGNO (a) == SP_REGNUM) { rtx ops[2]; ops[0] = operands[0]; @@ -4653,7 +4653,7 @@ (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))] "TARGET_EITHER" { - if (TARGET_ARM && !arm_arch6 && GET_CODE (operands[1]) != MEM) + if (TARGET_ARM && !arm_arch6 && !MEM_P (operands[1])) { emit_insn (gen_andsi3 (operands[0], gen_lowpart (SImode, operands[1]), @@ -4746,7 +4746,7 @@ [(set (match_operand:SI 0 "s_register_operand" "") (zero_extend:SI (subreg:QI (match_operand:SI 1 "" "") 0))) (clobber (match_operand:SI 2 "s_register_operand" ""))] - "TARGET_32BIT && (GET_CODE (operands[1]) != MEM) && ! BYTES_BIG_ENDIAN" + "TARGET_32BIT && (!MEM_P (operands[1])) && ! BYTES_BIG_ENDIAN" [(set (match_dup 2) (match_dup 1)) (set (match_dup 0) (and:SI (match_dup 2) (const_int 255)))] "" @@ -4756,7 +4756,7 @@ [(set (match_operand:SI 0 "s_register_operand" "") (zero_extend:SI (subreg:QI (match_operand:SI 1 "" "") 3))) (clobber (match_operand:SI 2 "s_register_operand" ""))] - "TARGET_32BIT && (GET_CODE (operands[1]) != MEM) && BYTES_BIG_ENDIAN" + "TARGET_32BIT && (!MEM_P (operands[1])) && BYTES_BIG_ENDIAN" [(set (match_dup 2) (match_dup 1)) (set (match_dup 0) (and:SI (match_dup 2) (const_int 255)))] "" @@ -4872,10 +4872,10 @@ rtx b = XEXP (mem, 1); if (GET_CODE (a) == LABEL_REF - && GET_CODE (b) == CONST_INT) + && CONST_INT_P (b)) return \"ldr\\t%0, %1\"; - if (GET_CODE (b) == REG) + if (REG_P (b)) return \"ldrsh\\t%0, %1\"; ops[1] = a; @@ -4887,7 +4887,7 @@ ops[2] = const0_rtx; } - gcc_assert (GET_CODE (ops[1]) == REG); + gcc_assert (REG_P (ops[1])); ops[0] = operands[0]; if (reg_mentioned_p (operands[2], ops[1])) @@ -4998,7 +4998,7 @@ "TARGET_ARM" " { - if (arm_arch4 && GET_CODE (operands[1]) == MEM) + if (arm_arch4 && MEM_P (operands[1])) { emit_insn (gen_rtx_SET (VOIDmode, operands[0], @@ -5235,11 +5235,11 @@ ;;{ ;; rtx insn; ;; -;; if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) +;; if (MEM_P (operands[0]) && MEM_P (operands[1])) ;; operands[1] = copy_to_reg (operands[1]); -;; if (GET_CODE (operands[0]) == MEM) +;; if (MEM_P (operands[0])) ;; insn = gen_storeti (XEXP (operands[0], 0), operands[1]); -;; else if (GET_CODE (operands[1]) == MEM) +;; else if (MEM_P (operands[1])) ;; insn = gen_loadti (operands[0], XEXP (operands[1], 0)); ;; else ;; FAIL; @@ -5280,7 +5280,7 @@ " if (can_create_pseudo_p ()) { - if (GET_CODE (operands[0]) != REG) + if (!REG_P (operands[0])) operands[1] = force_reg (DImode, operands[1]); } " @@ -5462,10 +5462,10 @@ if (TARGET_32BIT) { /* Everything except mem = const or mem = mem can be done easily. */ - if (GET_CODE (operands[0]) == MEM) + if (MEM_P (operands[0])) operands[1] = force_reg (SImode, operands[1]); if (arm_general_register_operand (operands[0], SImode) - && GET_CODE (operands[1]) == CONST_INT + && CONST_INT_P (operands[1]) && !(const_ok_for_arm (INTVAL (operands[1])) || const_ok_for_arm (~INTVAL (operands[1])))) { @@ -5479,7 +5479,7 @@ { if (can_create_pseudo_p ()) { - if (GET_CODE (operands[0]) != REG) + if (!REG_P (operands[0])) operands[1] = force_reg (SImode, operands[1]); } } @@ -5886,7 +5886,7 @@ rtx addr = XEXP (op1, 0); enum rtx_code code = GET_CODE (addr); - if ((code == PLUS && GET_CODE (XEXP (addr, 1)) != CONST_INT) + if ((code == PLUS && !CONST_INT_P (XEXP (addr, 1))) || code == MINUS) op1 = replace_equiv_address (operands[1], force_reg (SImode, addr)); @@ -5911,7 +5911,7 @@ rtx addr = XEXP (op1, 0); enum rtx_code code = GET_CODE (addr); - if ((code == PLUS && GET_CODE (XEXP (addr, 1)) != CONST_INT) + if ((code == PLUS && !CONST_INT_P (XEXP (addr, 1))) || code == MINUS) op1 = replace_equiv_address (op1, force_reg (SImode, addr)); @@ -5937,7 +5937,7 @@ rtx op0 = operands[0]; enum rtx_code code = GET_CODE (addr); - if ((code == PLUS && GET_CODE (XEXP (addr, 1)) != CONST_INT) + if ((code == PLUS && !CONST_INT_P (XEXP (addr, 1))) || code == MINUS) op0 = replace_equiv_address (op0, force_reg (SImode, addr)); @@ -5991,18 +5991,18 @@ { if (can_create_pseudo_p ()) { - if (GET_CODE (operands[0]) == MEM) + if (MEM_P (operands[0])) { if (arm_arch4) { emit_insn (gen_storehi_single_op (operands[0], operands[1])); DONE; } - if (GET_CODE (operands[1]) == CONST_INT) + if (CONST_INT_P (operands[1])) emit_insn (gen_storeinthi (operands[0], operands[1])); else { - if (GET_CODE (operands[1]) == MEM) + if (MEM_P (operands[1])) operands[1] = force_reg (HImode, operands[1]); if (BYTES_BIG_ENDIAN) emit_insn (gen_storehi_bigend (operands[1], operands[0])); @@ -6012,7 +6012,7 @@ DONE; } /* Sign extend a constant, and keep it in an SImode reg. */ - else if (GET_CODE (operands[1]) == CONST_INT) + else if (CONST_INT_P (operands[1])) { rtx reg = gen_reg_rtx (SImode); HOST_WIDE_INT val = INTVAL (operands[1]) & 0xffff; @@ -6034,7 +6034,7 @@ operands[1] = gen_lowpart (HImode, reg); } else if (arm_arch4 && optimize && can_create_pseudo_p () - && GET_CODE (operands[1]) == MEM) + && MEM_P (operands[1])) { rtx reg = gen_reg_rtx (SImode); @@ -6043,18 +6043,17 @@ } else if (!arm_arch4) { - if (GET_CODE (operands[1]) == MEM) + if (MEM_P (operands[1])) { rtx base; rtx offset = const0_rtx; rtx reg = gen_reg_rtx (SImode); - if ((GET_CODE (base = XEXP (operands[1], 0)) == REG + if ((REG_P (base = XEXP (operands[1], 0)) || (GET_CODE (base) == PLUS - && (GET_CODE (offset = XEXP (base, 1)) - == CONST_INT) + && (CONST_INT_P (offset = XEXP (base, 1))) && ((INTVAL(offset) & 1) != 1) - && GET_CODE (base = XEXP (base, 0)) == REG)) + && REG_P (base = XEXP (base, 0)))) && REGNO_POINTER_ALIGN (REGNO (base)) >= 32) { rtx new_rtx; @@ -6080,13 +6079,13 @@ } } /* Handle loading a large integer during reload. */ - else if (GET_CODE (operands[1]) == CONST_INT + else if (CONST_INT_P (operands[1]) && !const_ok_for_arm (INTVAL (operands[1])) && !const_ok_for_arm (~INTVAL (operands[1]))) { /* Writing a constant to memory needs a scratch, which should be handled with SECONDARY_RELOADs. */ - gcc_assert (GET_CODE (operands[0]) == REG); + gcc_assert (REG_P (operands[0])); operands[0] = gen_rtx_SUBREG (SImode, operands[0], 0); emit_insn (gen_movsi (operands[0], operands[1])); @@ -6098,10 +6097,10 @@ /* Thumb-2 can do everything except mem=mem and mem=const easily. */ if (can_create_pseudo_p ()) { - if (GET_CODE (operands[0]) != REG) + if (!REG_P (operands[0])) operands[1] = force_reg (HImode, operands[1]); /* Zero extend a constant, and keep it in an SImode reg. */ - else if (GET_CODE (operands[1]) == CONST_INT) + else if (CONST_INT_P (operands[1])) { rtx reg = gen_reg_rtx (SImode); HOST_WIDE_INT val = INTVAL (operands[1]) & 0xffff; @@ -6115,7 +6114,7 @@ { if (can_create_pseudo_p ()) { - if (GET_CODE (operands[1]) == CONST_INT) + if (CONST_INT_P (operands[1])) { rtx reg = gen_reg_rtx (SImode); @@ -6131,21 +6130,21 @@ fixup_stack_1, by checking for other kinds of invalid addresses, e.g. a bare reference to a virtual register. This may confuse the alpha though, which must handle this case differently. */ - if (GET_CODE (operands[0]) == MEM + if (MEM_P (operands[0]) && !memory_address_p (GET_MODE (operands[0]), XEXP (operands[0], 0))) operands[0] = replace_equiv_address (operands[0], copy_to_reg (XEXP (operands[0], 0))); - if (GET_CODE (operands[1]) == MEM + if (MEM_P (operands[1]) && !memory_address_p (GET_MODE (operands[1]), XEXP (operands[1], 0))) operands[1] = replace_equiv_address (operands[1], copy_to_reg (XEXP (operands[1], 0))); - if (GET_CODE (operands[1]) == MEM && optimize > 0) + if (MEM_P (operands[1]) && optimize > 0) { rtx reg = gen_reg_rtx (SImode); @@ -6153,17 +6152,17 @@ operands[1] = gen_lowpart (HImode, reg); } - if (GET_CODE (operands[0]) == MEM) + if (MEM_P (operands[0])) operands[1] = force_reg (HImode, operands[1]); } - else if (GET_CODE (operands[1]) == CONST_INT + else if (CONST_INT_P (operands[1]) && !satisfies_constraint_I (operands[1])) { /* Handle loading a large integer during reload. */ /* Writing a constant to memory needs a scratch, which should be handled with SECONDARY_RELOADs. */ - gcc_assert (GET_CODE (operands[0]) == REG); + gcc_assert (REG_P (operands[0])); operands[0] = gen_rtx_SUBREG (SImode, operands[0], 0); emit_insn (gen_movsi (operands[0], operands[1])); @@ -6192,7 +6191,7 @@ /* The stack pointer can end up being taken as an index register. Catch this case here and deal with it. */ if (GET_CODE (XEXP (operands[1], 0)) == PLUS - && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG + && REG_P (XEXP (XEXP (operands[1], 0), 0)) && REGNO (XEXP (XEXP (operands[1], 0), 0)) == SP_REGNUM) { rtx ops[2]; @@ -6347,7 +6346,7 @@ if (can_create_pseudo_p ()) { - if (GET_CODE (operands[1]) == CONST_INT) + if (CONST_INT_P (operands[1])) { rtx reg = gen_reg_rtx (SImode); @@ -6370,13 +6369,13 @@ fixup_stack_1, by checking for other kinds of invalid addresses, e.g. a bare reference to a virtual register. This may confuse the alpha though, which must handle this case differently. */ - if (GET_CODE (operands[0]) == MEM + if (MEM_P (operands[0]) && !memory_address_p (GET_MODE (operands[0]), XEXP (operands[0], 0))) operands[0] = replace_equiv_address (operands[0], copy_to_reg (XEXP (operands[0], 0))); - if (GET_CODE (operands[1]) == MEM + if (MEM_P (operands[1]) && !memory_address_p (GET_MODE (operands[1]), XEXP (operands[1], 0))) operands[1] @@ -6384,7 +6383,7 @@ copy_to_reg (XEXP (operands[1], 0))); } - if (GET_CODE (operands[1]) == MEM && optimize > 0) + if (MEM_P (operands[1]) && optimize > 0) { rtx reg = gen_reg_rtx (SImode); @@ -6392,18 +6391,18 @@ operands[1] = gen_lowpart (QImode, reg); } - if (GET_CODE (operands[0]) == MEM) + if (MEM_P (operands[0])) operands[1] = force_reg (QImode, operands[1]); } else if (TARGET_THUMB - && GET_CODE (operands[1]) == CONST_INT + && CONST_INT_P (operands[1]) && !satisfies_constraint_I (operands[1])) { /* Handle loading a large integer during reload. */ /* Writing a constant to memory needs a scratch, which should be handled with SECONDARY_RELOADs. */ - gcc_assert (GET_CODE (operands[0]) == REG); + gcc_assert (REG_P (operands[0])); operands[0] = gen_rtx_SUBREG (SImode, operands[0], 0); emit_insn (gen_movsi (operands[0], operands[1])); @@ -6460,14 +6459,14 @@ " if (TARGET_32BIT) { - if (GET_CODE (operands[0]) == MEM) + if (MEM_P (operands[0])) operands[1] = force_reg (HFmode, operands[1]); } else /* TARGET_THUMB1 */ { if (can_create_pseudo_p ()) { - if (GET_CODE (operands[0]) != REG) + if (!REG_P (operands[0])) operands[1] = force_reg (HFmode, operands[1]); } } @@ -6531,13 +6530,13 @@ case 1: { rtx addr; - gcc_assert (GET_CODE(operands[1]) == MEM); + gcc_assert (MEM_P (operands[1])); addr = XEXP (operands[1], 0); if (GET_CODE (addr) == LABEL_REF || (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS && GET_CODE (XEXP (XEXP (addr, 0), 0)) == LABEL_REF - && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)) + && CONST_INT_P (XEXP (XEXP (addr, 0), 1)))) { /* Constant pool entry. */ return \"ldr\\t%0, %1\"; @@ -6561,14 +6560,14 @@ " if (TARGET_32BIT) { - if (GET_CODE (operands[0]) == MEM) + if (MEM_P (operands[0])) operands[1] = force_reg (SFmode, operands[1]); } else /* TARGET_THUMB1 */ { if (can_create_pseudo_p ()) { - if (GET_CODE (operands[0]) != REG) + if (!REG_P (operands[0])) operands[1] = force_reg (SFmode, operands[1]); } } @@ -6582,7 +6581,7 @@ (match_operand:SF 1 "immediate_operand" ""))] "TARGET_EITHER && reload_completed - && GET_CODE (operands[1]) == CONST_DOUBLE" + && CONST_DOUBLE_P (operands[1])" [(set (match_dup 2) (match_dup 3))] " operands[2] = gen_lowpart (SImode, operands[0]); @@ -6597,7 +6596,7 @@ (match_operand:SF 1 "general_operand" "r,mE,r"))] "TARGET_32BIT && TARGET_SOFT_FLOAT - && (GET_CODE (operands[0]) != MEM + && (!MEM_P (operands[0]) || register_operand (operands[1], SFmode))" "@ mov%?\\t%0, %1 @@ -6640,14 +6639,14 @@ " if (TARGET_32BIT) { - if (GET_CODE (operands[0]) == MEM) + if (MEM_P (operands[0])) operands[1] = force_reg (DFmode, operands[1]); } else /* TARGET_THUMB */ { if (can_create_pseudo_p ()) { - if (GET_CODE (operands[0]) != REG) + if (!REG_P (operands[0])) operands[1] = force_reg (DFmode, operands[1]); } } @@ -6778,11 +6777,11 @@ HOST_WIDE_INT offset = 0; /* Support only fixed point registers. */ - if (GET_CODE (operands[2]) != CONST_INT + if (!CONST_INT_P (operands[2]) || INTVAL (operands[2]) > 14 || INTVAL (operands[2]) < 2 - || GET_CODE (operands[1]) != MEM - || GET_CODE (operands[0]) != REG + || !MEM_P (operands[1]) + || !REG_P (operands[0]) || REGNO (operands[0]) > (LAST_ARM_REGNUM - 1) || REGNO (operands[0]) + INTVAL (operands[2]) > LAST_ARM_REGNUM) FAIL; @@ -6803,11 +6802,11 @@ HOST_WIDE_INT offset = 0; /* Support only fixed point registers. */ - if (GET_CODE (operands[2]) != CONST_INT + if (!CONST_INT_P (operands[2]) || INTVAL (operands[2]) > 14 || INTVAL (operands[2]) < 2 - || GET_CODE (operands[1]) != REG - || GET_CODE (operands[0]) != MEM + || !REG_P (operands[1]) + || !MEM_P (operands[0]) || REGNO (operands[1]) > (LAST_ARM_REGNUM - 1) || REGNO (operands[1]) + INTVAL (operands[2]) > LAST_ARM_REGNUM) FAIL; @@ -6999,7 +6998,7 @@ gcc_assert (GET_MODE (operands[1]) == DImode || GET_MODE (operands[2]) == DImode); - if (!arm_validize_comparison (&operands[0], &operands[1], &operands[2])) + if (!arm_validize_comparison (&operands[0], &operands[1], &operands[2])) FAIL; emit_jump_insn (gen_cbranch_cc (operands[0], operands[1], operands[2], operands[3])); @@ -7430,7 +7429,7 @@ cond[1] = operands[2]; cond[2] = operands[3]; - if (GET_CODE (cond[2]) == CONST_INT && INTVAL (cond[2]) < 0) + if (CONST_INT_P (cond[2]) && INTVAL (cond[2]) < 0) output_asm_insn (\"sub\\t%0, %1, #%n2\", cond); else output_asm_insn (\"add\\t%0, %1, %2\", cond); @@ -9849,13 +9848,13 @@ if (GET_CODE (operands[5]) == LT && (operands[4] == const0_rtx)) { - if (which_alternative != 1 && GET_CODE (operands[1]) == REG) + if (which_alternative != 1 && REG_P (operands[1])) { if (operands[2] == const0_rtx) return \"and\\t%0, %1, %3, asr #31\"; return \"ands\\t%0, %1, %3, asr #32\;movcc\\t%0, %2\"; } - else if (which_alternative != 0 && GET_CODE (operands[2]) == REG) + else if (which_alternative != 0 && REG_P (operands[2])) { if (operands[1] == const0_rtx) return \"bic\\t%0, %2, %3, asr #31\"; @@ -9868,13 +9867,13 @@ if (GET_CODE (operands[5]) == GE && (operands[4] == const0_rtx)) { - if (which_alternative != 1 && GET_CODE (operands[1]) == REG) + if (which_alternative != 1 && REG_P (operands[1])) { if (operands[2] == const0_rtx) return \"bic\\t%0, %1, %3, asr #31\"; return \"bics\\t%0, %1, %3, asr #32\;movcs\\t%0, %2\"; } - else if (which_alternative != 0 && GET_CODE (operands[2]) == REG) + else if (which_alternative != 0 && REG_P (operands[2])) { if (operands[1] == const0_rtx) return \"and\\t%0, %2, %3, asr #31\"; @@ -9883,7 +9882,7 @@ /* The only case that falls through to here is when both ops 1 & 2 are constants. */ } - if (GET_CODE (operands[4]) == CONST_INT + if (CONST_INT_P (operands[4]) && !const_ok_for_arm (INTVAL (operands[4]))) output_asm_insn (\"cmn\\t%3, #%n4\", operands); else @@ -10023,8 +10022,8 @@ everything is in registers then we can do this in two instructions. */ if (operands[3] == const0_rtx && GET_CODE (operands[7]) != AND - && GET_CODE (operands[5]) == REG - && GET_CODE (operands[1]) == REG + && REG_P (operands[5]) + && REG_P (operands[1]) && REGNO (operands[1]) == REGNO (operands[4]) && REGNO (operands[4]) != REGNO (operands[0])) { @@ -10033,7 +10032,7 @@ else if (GET_CODE (operands[6]) == GE) return \"bic\\t%0, %5, %2, asr #31\;%I7\\t%0, %4, %0\"; } - if (GET_CODE (operands[3]) == CONST_INT + if (CONST_INT_P (operands[3]) && !const_ok_for_arm (INTVAL (operands[3]))) output_asm_insn (\"cmn\\t%2, #%n3\", operands); else @@ -10081,8 +10080,8 @@ everything is in registers then we can do this in two instructions */ if (operands[5] == const0_rtx && GET_CODE (operands[7]) != AND - && GET_CODE (operands[3]) == REG - && GET_CODE (operands[1]) == REG + && REG_P (operands[3]) + && REG_P (operands[1]) && REGNO (operands[1]) == REGNO (operands[2]) && REGNO (operands[2]) != REGNO (operands[0])) { @@ -10092,7 +10091,7 @@ return \"bic\\t%0, %3, %4, asr #31\;%I7\\t%0, %2, %0\"; } - if (GET_CODE (operands[5]) == CONST_INT + if (CONST_INT_P (operands[5]) && !const_ok_for_arm (INTVAL (operands[5]))) output_asm_insn (\"cmn\\t%4, #%n5\", operands); else @@ -10677,7 +10676,7 @@ " { cfun->machine->eh_epilogue_sp_ofs = operands[1]; - if (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != 2) + if (!REG_P (operands[2]) || REGNO (operands[2]) != 2) { rtx ra = gen_rtx_REG (Pmode, 2); diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index a929546..faf9090 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -255,7 +255,7 @@ { if (can_create_pseudo_p ()) { - if (GET_CODE (operands[0]) != REG) + if (!REG_P (operands[0])) operands[1] = force_reg (TImode, operands[1]); } }) @@ -267,7 +267,7 @@ { if (can_create_pseudo_p ()) { - if (GET_CODE (operands[0]) != REG) + if (!REG_P (operands[0])) operands[1] = force_reg (<MODE>mode, operands[1]); } }) diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md index 8ae26ca..e7eb7b3 100644 --- a/gcc/config/arm/predicates.md +++ b/gcc/config/arm/predicates.md @@ -26,7 +26,7 @@ /* We don't consider registers whose class is NO_REGS to be a register operand. */ /* XXX might have to check for lo regs only for thumb ??? */ - return (GET_CODE (op) == REG + return (REG_P (op) && (REGNO (op) >= FIRST_PSEUDO_REGISTER || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); }) @@ -55,7 +55,7 @@ if (GET_CODE (op) == SUBREG) op = SUBREG_REG (op); - return (GET_CODE (op) == REG + return (REG_P (op) && (REGNO (op) <= LAST_ARM_REGNUM || REGNO (op) >= FIRST_PSEUDO_REGISTER)); }) @@ -68,7 +68,7 @@ /* We don't consider registers whose class is NO_REGS to be a register operand. */ - return (GET_CODE (op) == REG + return (REG_P (op) && (REGNO (op) >= FIRST_PSEUDO_REGISTER || REGNO_REG_CLASS (REGNO (op)) == VFP_D0_D7_REGS || REGNO_REG_CLASS (REGNO (op)) == VFP_LO_REGS @@ -178,7 +178,7 @@ (and (match_code "mem,reg,subreg") (match_test "(!CONSTANT_P (op) && (true_regnum(op) == -1 - || (GET_CODE (op) == REG + || (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER)))"))) (define_predicate "vfp_compare_operand" @@ -195,7 +195,7 @@ (define_predicate "index_operand" (ior (match_operand 0 "s_register_operand") (and (match_operand 0 "immediate_operand") - (match_test "(GET_CODE (op) != CONST_INT + (match_test "(!CONST_INT_P (op) || (INTVAL (op) < 4096 && INTVAL (op) > -4096))")))) ;; True for operators that can be combined with a shift in ARM state. @@ -223,10 +223,10 @@ (and (ior (ior (and (match_code "mult") (match_test "power_of_two_operand (XEXP (op, 1), mode)")) (and (match_code "rotate") - (match_test "GET_CODE (XEXP (op, 1)) == CONST_INT + (match_test "CONST_INT_P (XEXP (op, 1)) && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32"))) (and (match_code "ashift,ashiftrt,lshiftrt,rotatert") - (match_test "GET_CODE (XEXP (op, 1)) != CONST_INT + (match_test "!CONST_INT_P (XEXP (op, 1)) || ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32"))) (match_test "mode == GET_MODE (op)"))) @@ -235,7 +235,7 @@ (and (ior (and (match_code "mult") (match_test "power_of_two_operand (XEXP (op, 1), mode)")) (and (match_code "ashift,ashiftrt") - (match_test "GET_CODE (XEXP (op, 1)) == CONST_INT + (match_test "CONST_INT_P (XEXP (op, 1)) && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1)) < 32)"))) (match_test "mode == GET_MODE (op)"))) @@ -332,7 +332,7 @@ if (GET_CODE (op) == SUBREG) op = SUBREG_REG (op); - return GET_CODE (op) == MEM && memory_address_p (DImode, XEXP (op, 0)); + return MEM_P (op) && memory_address_p (DImode, XEXP (op, 0)); }) (define_predicate "di_operand" @@ -349,7 +349,7 @@ if (GET_CODE (op) == SUBREG) op = SUBREG_REG (op); - return GET_CODE (op) == MEM && memory_address_p (DFmode, XEXP (op, 0)); + return MEM_P (op) && memory_address_p (DFmode, XEXP (op, 0)); }) (define_predicate "soft_df_operand" @@ -559,7 +559,7 @@ rtx elt = XVECEXP (op, 0, i); int val; - if (GET_CODE (elt) != CONST_INT) + if (!CONST_INT_P (elt)) return false; val = INTVAL (elt); @@ -588,7 +588,7 @@ rtx elt = XVECEXP (op, 0, i); int val; - if (GET_CODE (elt) != CONST_INT) + if (!CONST_INT_P (elt)) return false; val = INTVAL (elt); diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md index fd0bea6..57d1539 100644 --- a/gcc/config/arm/thumb2.md +++ b/gcc/config/arm/thumb2.md @@ -494,13 +494,13 @@ if (GET_CODE (operands[5]) == LT && (operands[4] == const0_rtx)) { - if (which_alternative != 1 && GET_CODE (operands[1]) == REG) + if (which_alternative != 1 && REG_P (operands[1])) { if (operands[2] == const0_rtx) return \"and\\t%0, %1, %3, asr #31\"; return \"ands\\t%0, %1, %3, asr #32\;it\\tcc\;movcc\\t%0, %2\"; } - else if (which_alternative != 0 && GET_CODE (operands[2]) == REG) + else if (which_alternative != 0 && REG_P (operands[2])) { if (operands[1] == const0_rtx) return \"bic\\t%0, %2, %3, asr #31\"; @@ -513,13 +513,13 @@ if (GET_CODE (operands[5]) == GE && (operands[4] == const0_rtx)) { - if (which_alternative != 1 && GET_CODE (operands[1]) == REG) + if (which_alternative != 1 && REG_P (operands[1])) { if (operands[2] == const0_rtx) return \"bic\\t%0, %1, %3, asr #31\"; return \"bics\\t%0, %1, %3, asr #32\;it\\tcs\;movcs\\t%0, %2\"; } - else if (which_alternative != 0 && GET_CODE (operands[2]) == REG) + else if (which_alternative != 0 && REG_P (operands[2])) { if (operands[1] == const0_rtx) return \"and\\t%0, %2, %3, asr #31\"; @@ -528,7 +528,7 @@ /* The only case that falls through to here is when both ops 1 & 2 are constants. */ } - if (GET_CODE (operands[4]) == CONST_INT + if (CONST_INT_P (operands[4]) && !const_ok_for_arm (INTVAL (operands[4]))) output_asm_insn (\"cmn\\t%3, #%n4\", operands); else @@ -680,7 +680,7 @@ (clobber (reg:CC CC_REGNUM))] "TARGET_THUMB2 && reload_completed && ((GET_CODE(operands[3]) != ROTATE && GET_CODE(operands[3]) != ROTATERT) - || REG_P(operands[2]))" + || REG_P (operands[2]))" "* return arm_output_shift(operands, 2);" [(set_attr "predicable" "yes") (set_attr "shift" "1") @@ -709,7 +709,7 @@ "* HOST_WIDE_INT val; - if (GET_CODE (operands[2]) == CONST_INT) + if (CONST_INT_P (operands[2])) val = INTVAL(operands[2]); else val = 0; @@ -773,7 +773,7 @@ "* HOST_WIDE_INT val; - if (GET_CODE (operands[2]) == CONST_INT) + if (CONST_INT_P (operands[2])) val = INTVAL (operands[2]); else val = 0; @@ -797,7 +797,7 @@ "* HOST_WIDE_INT val; - if (GET_CODE (operands[1]) == CONST_INT) + if (CONST_INT_P (operands[1])) val = INTVAL (operands[1]); else val = 0; diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md index 4d903bd..b43e952 100644 --- a/gcc/config/arm/vec-common.md +++ b/gcc/config/arm/vec-common.md @@ -28,7 +28,7 @@ { if (can_create_pseudo_p ()) { - if (GET_CODE (operands[0]) != REG) + if (!REG_P (operands[0])) operands[1] = force_reg (<MODE>mode, operands[1]); else if (TARGET_NEON && CONSTANT_P (operands[1])) {

[ARM] Cleanup: Replace GET_CODE comparisons with predicates

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