| Message ID | 1346099868-7774-3-git-send-email-meadori@codesourcery.com |
|---|---|
| State | New |
| Headers | show |
On 27 August 2012 21:37, Meador Inge <meadori@codesourcery.com> wrote: > The current implementation of the ARM semi-hosting SYS_HEAPINFO > system call assumes that the base address of RAM for all ARM devices > is 0x0. This isn't true for ARMv7-M devices, which uses a base of > 0x20000000 for SRAM. This isn't a v7M specific problem (it applies also for ARM A/R boards where the RAM doesn't start at address zero). So it needs a generic solution, not a v7M specific one. -- PMM
diff --git a/target-arm/arm-semi.c b/target-arm/arm-semi.c index 73bde58..fd90794 100644 --- a/target-arm/arm-semi.c +++ b/target-arm/arm-semi.c @@ -486,7 +486,13 @@ uint32_t do_arm_semihosting(CPUARMState *env) ptr[3] = tswap32(0); /* Stack limit. */ unlock_user(ptr, ARG(0), 16); #else - limit = ram_size; + /* For ARMv7-M use the base address of SRAM as specified by the + architecture. */ + if (arm_feature(env, ARM_FEATURE_M)) { + limit = 0x20000000 + ram_size; + } else { + limit = ram_size; + } if (!(ptr = lock_user(VERIFY_WRITE, ARG(0), 16, 0))) /* FIXME - should this error code be -TARGET_EFAULT ? */ return (uint32_t)-1;
The current implementation of the ARM semi-hosting SYS_HEAPINFO system call assumes that the base address of RAM for all ARM devices is 0x0. This isn't true for ARMv7-M devices, which uses a base of 0x20000000 for SRAM. Signed-off-by: Meador Inge <meadori@codesourcery.com> --- target-arm/arm-semi.c | 8 +++++++- 1 files changed, 7 insertions(+), 1 deletions(-)