[6/7] rs6000: Remove -mabi=ieeelongdouble.

Message ID	2a9f0041a698cb45a4e553b93540e85a8eac3d2f.1345067650.git.segher@kernel.crashing.org
State	New
Headers	show Return-Path: <gcc-patches-return-324581-incoming=patchwork.ozlabs.org@gcc.gnu.org> Comment: DKIM? See http://www.dkim.org Comment: DomainKeys? See http://antispam.yahoo.com/domainkeys DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=default; d=gcc.gnu.org; h=Received:Received:X-SWARE-Spam-Status:X-Spam-Check-By:Received:Received:Received:From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:In-Reply-To:References:X-IsSubscribed:Mailing-List:Precedence:List-Id:List-Unsubscribe:List-Archive:List-Post:List-Help:Sender:Delivered-To; b=ees2m8BoQsvlPZ2pynUwftmx4ohzEsyCyh579HyerW2w8KB1MWYSB+6WYM8Xd8 wWJ3ILOrR0GfEWSFhr/lHyvXF4728MM4XgphSpduHXZrYDpH1uYX65rPWnTE2+gc 85OmjqdfUIbUmV9s4ZHSPSznDbTe5HY1GpLWwqGp2p9i4=; From: Segher Boessenkool <segher@kernel.crashing.org> To: gcc-patches@gcc.gnu.org Cc: dje.gcc@gmail.com, meissner@gcc.gnu.org, Segher Boessenkool <segher@kernel.crashing.org> Subject: [PATCH 6/7] rs6000: Remove -mabi=ieeelongdouble. Date: Wed, 15 Aug 2012 15:29:22 -0700 Message-Id: <2a9f0041a698cb45a4e553b93540e85a8eac3d2f.1345067650.git.segher@kernel.crashing.org> In-Reply-To: <cover.1345067650.git.segher@kernel.crashing.org> References: <cover.1345067650.git.segher@kernel.crashing.org> In-Reply-To: <cover.1345067650.git.segher@kernel.crashing.org> References: <cover.1345067650.git.segher@kernel.crashing.org> Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk Sender: gcc-patches-owner@gcc.gnu.org

diff --git a/gcc/config/rs6000/aix.h b/gcc/config/rs6000/aix.h index 41421a0..dc6dc55 100644 --- a/gcc/config/rs6000/aix.h +++ b/gcc/config/rs6000/aix.h @@ -41,9 +41,6 @@ #undef STACK_BOUNDARY #define STACK_BOUNDARY 128 -#undef TARGET_IEEEQUAD -#define TARGET_IEEEQUAD 0 - /* The AIX linker will discard static constructors in object files before collect has a chance to see them, so scan the object files directly. */ #define COLLECT_EXPORT_LIST diff --git a/gcc/config/rs6000/darwin.h b/gcc/config/rs6000/darwin.h index 17ff675..2e67215 100644 --- a/gcc/config/rs6000/darwin.h +++ b/gcc/config/rs6000/darwin.h @@ -282,10 +282,6 @@ extern int darwin_emit_branch_islands; #undef TARGET_DEFAULT #define TARGET_DEFAULT (MASK_MULTIPLE | MASK_PPC_GFXOPT) -/* Darwin only runs on PowerPC, so short-circuit POWER patterns. */ -#undef TARGET_IEEEQUAD -#define TARGET_IEEEQUAD 0 - /* Since Darwin doesn't do TOCs, stub this out. */ #define ASM_OUTPUT_SPECIAL_POOL_ENTRY_P(X, MODE) ((void)X, (void)MODE, 0) diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 4571c6f..15105c6 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -2686,11 +2686,6 @@ rs6000_option_override_internal (bool global_init_p) rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE; } -#if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD) - if (!global_options_set.x_rs6000_ieeequad) - rs6000_ieeequad = 1; -#endif - /* Disable VSX and Altivec silently if the user switched cpus to power7 in a target attribute or pragma which automatically enables both options, unless the altivec ABI was set. This is set by default for 64-bit, but @@ -2893,7 +2888,7 @@ rs6000_option_override_internal (bool global_init_p) flag_signed_bitfields = 0; #endif - if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD) + if (TARGET_LONG_DOUBLE_128) REAL_MODE_FORMAT (TFmode) = &ibm_extended_format; if (TARGET_TOC) @@ -6986,8 +6981,8 @@ rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode) /* 128-bit constant floating-point values on Darwin should really be loaded as two parts. */ - if (!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 - && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE) + if (TARGET_LONG_DOUBLE_128 && mode == TFmode + && GET_CODE (operands[1]) == CONST_DOUBLE) { rs6000_emit_move (simplify_gen_subreg (DFmode, operands[0], mode, 0), simplify_gen_subreg (DFmode, operands[1], mode, 0), @@ -7350,9 +7345,6 @@ rs6000_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) return true; } - if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && TYPE_MODE (type) == TFmode) - return true; - return false; } @@ -7908,8 +7900,7 @@ rs6000_function_arg_advance_1 (CUMULATIVE_ARGS *cum, enum machine_mode mode, { if (TARGET_HARD_FLOAT && TARGET_FPRS && ((TARGET_SINGLE_FLOAT && mode == SFmode) - || (TARGET_DOUBLE_FLOAT && mode == DFmode) - || (mode == TFmode && !TARGET_IEEEQUAD) + || (TARGET_DOUBLE_FLOAT && mode == DFmode) || mode == TFmode || mode == SDmode || mode == DDmode || mode == TDmode)) { /* _Decimal128 must use an even/odd register pair. This assumes @@ -8489,8 +8480,7 @@ rs6000_function_arg (cumulative_args_t cum_v, enum machine_mode mode, { if (TARGET_HARD_FLOAT && TARGET_FPRS && ((TARGET_SINGLE_FLOAT && mode == SFmode) - || (TARGET_DOUBLE_FLOAT && mode == DFmode) - || (mode == TFmode && !TARGET_IEEEQUAD) + || (TARGET_DOUBLE_FLOAT && mode == DFmode) || mode == TFmode || mode == SDmode || mode == DDmode || mode == TDmode)) { /* _Decimal128 must use an even/odd register pair. This assumes @@ -8708,13 +8698,6 @@ rs6000_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED, enum machine_mode mode, const_tree type, bool named ATTRIBUTE_UNUSED) { - if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && mode == TFmode) - { - if (TARGET_DEBUG_ARG) - fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n"); - return 1; - } - if (!type) return 0; @@ -12657,73 +12640,43 @@ rs6000_common_init_builtins (void) static void rs6000_init_libfuncs (void) { - if (!TARGET_IEEEQUAD) - /* AIX/Darwin/64-bit Linux quad floating point routines. */ - if (!TARGET_XL_COMPAT) - { - set_optab_libfunc (add_optab, TFmode, "__gcc_qadd"); - set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub"); - set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul"); - set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv"); - - if (!(TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE))) - { - set_optab_libfunc (neg_optab, TFmode, "__gcc_qneg"); - set_optab_libfunc (eq_optab, TFmode, "__gcc_qeq"); - set_optab_libfunc (ne_optab, TFmode, "__gcc_qne"); - set_optab_libfunc (gt_optab, TFmode, "__gcc_qgt"); - set_optab_libfunc (ge_optab, TFmode, "__gcc_qge"); - set_optab_libfunc (lt_optab, TFmode, "__gcc_qlt"); - set_optab_libfunc (le_optab, TFmode, "__gcc_qle"); - - set_conv_libfunc (sext_optab, TFmode, SFmode, "__gcc_stoq"); - set_conv_libfunc (sext_optab, TFmode, DFmode, "__gcc_dtoq"); - set_conv_libfunc (trunc_optab, SFmode, TFmode, "__gcc_qtos"); - set_conv_libfunc (trunc_optab, DFmode, TFmode, "__gcc_qtod"); - set_conv_libfunc (sfix_optab, SImode, TFmode, "__gcc_qtoi"); - set_conv_libfunc (ufix_optab, SImode, TFmode, "__gcc_qtou"); - set_conv_libfunc (sfloat_optab, TFmode, SImode, "__gcc_itoq"); - set_conv_libfunc (ufloat_optab, TFmode, SImode, "__gcc_utoq"); - } - - if (!(TARGET_HARD_FLOAT && TARGET_FPRS)) - set_optab_libfunc (unord_optab, TFmode, "__gcc_qunord"); - } - else - { - set_optab_libfunc (add_optab, TFmode, "_xlqadd"); - set_optab_libfunc (sub_optab, TFmode, "_xlqsub"); - set_optab_libfunc (smul_optab, TFmode, "_xlqmul"); - set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv"); - } - else + if (TARGET_XL_COMPAT) { - /* 32-bit SVR4 quad floating point routines. */ + set_optab_libfunc (add_optab, TFmode, "_xlqadd"); + set_optab_libfunc (sub_optab, TFmode, "_xlqsub"); + set_optab_libfunc (smul_optab, TFmode, "_xlqmul"); + set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv"); + + return; + } - set_optab_libfunc (add_optab, TFmode, "_q_add"); - set_optab_libfunc (sub_optab, TFmode, "_q_sub"); - set_optab_libfunc (neg_optab, TFmode, "_q_neg"); - set_optab_libfunc (smul_optab, TFmode, "_q_mul"); - set_optab_libfunc (sdiv_optab, TFmode, "_q_div"); - if (TARGET_PPC_GPOPT) - set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt"); + set_optab_libfunc (add_optab, TFmode, "__gcc_qadd"); + set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub"); + set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul"); + set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv"); - set_optab_libfunc (eq_optab, TFmode, "_q_feq"); - set_optab_libfunc (ne_optab, TFmode, "_q_fne"); - set_optab_libfunc (gt_optab, TFmode, "_q_fgt"); - set_optab_libfunc (ge_optab, TFmode, "_q_fge"); - set_optab_libfunc (lt_optab, TFmode, "_q_flt"); - set_optab_libfunc (le_optab, TFmode, "_q_fle"); + if (!(TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE))) + { + set_optab_libfunc (neg_optab, TFmode, "__gcc_qneg"); + set_optab_libfunc (eq_optab, TFmode, "__gcc_qeq"); + set_optab_libfunc (ne_optab, TFmode, "__gcc_qne"); + set_optab_libfunc (gt_optab, TFmode, "__gcc_qgt"); + set_optab_libfunc (ge_optab, TFmode, "__gcc_qge"); + set_optab_libfunc (lt_optab, TFmode, "__gcc_qlt"); + set_optab_libfunc (le_optab, TFmode, "__gcc_qle"); - set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq"); - set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq"); - set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos"); - set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod"); - set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi"); - set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou"); - set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq"); - set_conv_libfunc (ufloat_optab, TFmode, SImode, "_q_utoq"); + set_conv_libfunc (sext_optab, TFmode, SFmode, "__gcc_stoq"); + set_conv_libfunc (sext_optab, TFmode, DFmode, "__gcc_dtoq"); + set_conv_libfunc (trunc_optab, SFmode, TFmode, "__gcc_qtos"); + set_conv_libfunc (trunc_optab, DFmode, TFmode, "__gcc_qtod"); + set_conv_libfunc (sfix_optab, SImode, TFmode, "__gcc_qtoi"); + set_conv_libfunc (ufix_optab, SImode, TFmode, "__gcc_qtou"); + set_conv_libfunc (sfloat_optab, TFmode, SImode, "__gcc_itoq"); + set_conv_libfunc (ufloat_optab, TFmode, SImode, "__gcc_utoq"); } + + if (!(TARGET_HARD_FLOAT && TARGET_FPRS)) + set_optab_libfunc (unord_optab, TFmode, "__gcc_qunord"); } @@ -14303,7 +14256,7 @@ rs6000_cannot_change_mode_class (enum machine_mode from, if (from_size != to_size) { enum reg_class xclass = (TARGET_VSX) ? VSX_REGS : FLOAT_REGS; - return ((from_size < 8 || to_size < 8 || TARGET_IEEEQUAD) + return ((from_size < 8 || to_size < 8) && reg_classes_intersect_p (xclass, rclass)); } @@ -15671,7 +15624,6 @@ rs6000_generate_compare (rtx cmp, enum machine_mode mode) CLOBBERs to match cmptf_internal2 pattern. */ if (comp_mode == CCFPmode && TARGET_XL_COMPAT && GET_MODE (op0) == TFmode - && !TARGET_IEEEQUAD && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128) emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (10, @@ -24550,8 +24502,7 @@ rs6000_mangle_type (const_tree type) powerpc*-linux where long-double-64 previously was the default. */ if (TYPE_MAIN_VARIANT (type) == long_double_type_node && TARGET_ELF - && TARGET_LONG_DOUBLE_128 - && !TARGET_IEEEQUAD) + && TARGET_LONG_DOUBLE_128) return "g"; /* For all other types, use normal C++ mangling. */ diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index abafbf9..ed3b7b0 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -433,7 +433,6 @@ extern int rs6000_vector_align[]; #endif #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128) -#define TARGET_IEEEQUAD rs6000_ieeequad #define TARGET_ALTIVEC_ABI rs6000_altivec_abi #define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index d5ffd81..3667b36 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -235,8 +235,7 @@ (define_mode_iterator FP [ && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)") (DF "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)") - (TF "!TARGET_IEEEQUAD - && TARGET_HARD_FLOAT + (TF "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE) && TARGET_LONG_DOUBLE_128") (DD "TARGET_DFP") @@ -8407,7 +8406,7 @@ (define_insn "*movdf_softfloat64" (define_expand "movtf" [(set (match_operand:TF 0 "general_operand" "") (match_operand:TF 1 "any_operand" ""))] - "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128" + "TARGET_LONG_DOUBLE_128" "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }") ;; It's important to list Y->r and r->Y before r->r because otherwise @@ -8416,8 +8415,7 @@ (define_expand "movtf" (define_insn_and_split "*movtf_internal" [(set (match_operand:TF 0 "nonimmediate_operand" "=m,d,d,Y,r,r") (match_operand:TF 1 "input_operand" "d,m,d,r,YGHF,r"))] - "!TARGET_IEEEQUAD - && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128 + "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128 && (gpc_reg_operand (operands[0], TFmode) || gpc_reg_operand (operands[1], TFmode))" "#" @@ -8429,8 +8427,7 @@ (define_insn_and_split "*movtf_internal" (define_insn_and_split "*movtf_softfloat" [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=Y,r,r") (match_operand:TF 1 "input_operand" "r,YGHF,r"))] - "!TARGET_IEEEQUAD - && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128 + "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128 && (gpc_reg_operand (operands[0], TFmode) || gpc_reg_operand (operands[1], TFmode))" "#" @@ -8442,8 +8439,7 @@ (define_insn_and_split "*movtf_softfloat" (define_expand "extenddftf2" [(set (match_operand:TF 0 "nonimmediate_operand" "") (float_extend:TF (match_operand:DF 1 "input_operand" "")))] - "!TARGET_IEEEQUAD - && TARGET_HARD_FLOAT + "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE) && TARGET_LONG_DOUBLE_128" { @@ -8458,8 +8454,7 @@ (define_expand "extenddftf2_fprs" [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "") (float_extend:TF (match_operand:DF 1 "input_operand" ""))) (use (match_dup 2))])] - "!TARGET_IEEEQUAD - && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT + "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128" { operands[2] = CONST0_RTX (DFmode); @@ -8472,8 +8467,7 @@ (define_insn_and_split "*extenddftf2_internal" [(set (match_operand:TF 0 "nonimmediate_operand" "=m,Y,d,&d,r") (float_extend:TF (match_operand:DF 1 "input_operand" "d,r,md,md,rmGHF"))) (use (match_operand:DF 2 "zero_reg_mem_operand" "d,r,m,d,n"))] - "!TARGET_IEEEQUAD - && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT + "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128" "#" "&& reload_completed" @@ -8491,9 +8485,7 @@ (define_insn_and_split "*extenddftf2_internal" (define_expand "extendsftf2" [(set (match_operand:TF 0 "nonimmediate_operand" "") (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))] - "!TARGET_IEEEQUAD - && TARGET_HARD_FLOAT - && (TARGET_FPRS || TARGET_E500_DOUBLE) + "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE) && TARGET_LONG_DOUBLE_128" { rtx tmp = gen_reg_rtx (DFmode); @@ -8505,17 +8497,15 @@ (define_expand "extendsftf2" (define_expand "trunctfdf2" [(set (match_operand:DF 0 "gpc_reg_operand" "") (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))] - "!TARGET_IEEEQUAD - && TARGET_HARD_FLOAT - && (TARGET_FPRS || TARGET_E500_DOUBLE) + "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE) && TARGET_LONG_DOUBLE_128" "") (define_insn_and_split "trunctfdf2_internal1" [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d") (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,d")))] - "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT - && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" + "!TARGET_XL_COMPAT && TARGET_HARD_FLOAT && TARGET_FPRS + && TARGET_LONG_DOUBLE_128" "@ # fmr %0,%1" @@ -8530,8 +8520,7 @@ (define_insn_and_split "trunctfdf2_internal1" (define_insn "trunctfdf2_internal2" [(set (match_operand:DF 0 "gpc_reg_operand" "=d") (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "d")))] - "!TARGET_IEEEQUAD && TARGET_XL_COMPAT - && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT + "TARGET_XL_COMPAT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128" "fadd %0,%1,%L1" [(set_attr "type" "fp") @@ -8540,9 +8529,7 @@ (define_insn "trunctfdf2_internal2" (define_expand "trunctfsf2" [(set (match_operand:SF 0 "gpc_reg_operand" "") (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))] - "!TARGET_IEEEQUAD - && TARGET_HARD_FLOAT - && (TARGET_FPRS || TARGET_E500_DOUBLE) + "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE) && TARGET_LONG_DOUBLE_128" { if (TARGET_E500_DOUBLE) @@ -8556,8 +8543,7 @@ (define_insn_and_split "trunctfsf2_fprs" [(set (match_operand:SF 0 "gpc_reg_operand" "=f") (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "d"))) (clobber (match_scratch:DF 2 "=d"))] - "!TARGET_IEEEQUAD - && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT + "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_LONG_DOUBLE_128" "#" "&& reload_completed" @@ -8570,9 +8556,7 @@ (define_insn_and_split "trunctfsf2_fprs" (define_expand "floatsitf2" [(set (match_operand:TF 0 "gpc_reg_operand" "") (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))] - "!TARGET_IEEEQUAD - && TARGET_HARD_FLOAT - && (TARGET_FPRS || TARGET_E500_DOUBLE) + "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE) && TARGET_LONG_DOUBLE_128" { rtx tmp = gen_reg_rtx (DFmode); @@ -8596,8 +8580,8 @@ (define_insn "fix_trunc_helper" (define_expand "fix_trunctfsi2" [(set (match_operand:SI 0 "gpc_reg_operand" "") (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))] - "!TARGET_IEEEQUAD && TARGET_HARD_FLOAT - && (TARGET_FPRS || TARGET_E500_DOUBLE) && TARGET_LONG_DOUBLE_128" + "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE) + && TARGET_LONG_DOUBLE_128" { if (TARGET_E500_DOUBLE) emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1])); @@ -8613,8 +8597,7 @@ (define_expand "fix_trunctfsi2_fprs" (clobber (match_dup 3)) (clobber (match_dup 4)) (clobber (match_dup 5))])] - "!TARGET_IEEEQUAD - && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" + "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" { operands[2] = gen_reg_rtx (DFmode); operands[3] = gen_reg_rtx (DFmode); @@ -8629,8 +8612,7 @@ (define_insn_and_split "*fix_trunctfsi2_internal" (clobber (match_operand:DF 3 "gpc_reg_operand" "=&d")) (clobber (match_operand:DI 4 "gpc_reg_operand" "=d")) (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))] - "!TARGET_IEEEQUAD - && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" + "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" "#" "" [(pc)] @@ -8650,17 +8632,14 @@ (define_insn_and_split "*fix_trunctfsi2_internal" (define_expand "negtf2" [(set (match_operand:TF 0 "gpc_reg_operand" "") (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))] - "!TARGET_IEEEQUAD - && TARGET_HARD_FLOAT - && (TARGET_FPRS || TARGET_E500_DOUBLE) + "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE) && TARGET_LONG_DOUBLE_128" "") (define_insn "negtf2_internal" [(set (match_operand:TF 0 "gpc_reg_operand" "=d") (neg:TF (match_operand:TF 1 "gpc_reg_operand" "d")))] - "!TARGET_IEEEQUAD - && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" + "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" "* { if (REGNO (operands[0]) == REGNO (operands[1]) + 1) @@ -8674,9 +8653,7 @@ (define_insn "negtf2_internal" (define_expand "abstf2" [(set (match_operand:TF 0 "gpc_reg_operand" "") (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))] - "!TARGET_IEEEQUAD - && TARGET_HARD_FLOAT - && (TARGET_FPRS || TARGET_E500_DOUBLE) + "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE) && TARGET_LONG_DOUBLE_128" " { @@ -8704,8 +8681,7 @@ (define_expand "abstf2_internal" (label_ref (match_operand 2 "" "")) (pc))) (set (match_dup 6) (neg:DF (match_dup 6)))] - "!TARGET_IEEEQUAD - && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT + "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128" " { @@ -11687,8 +11663,8 @@ (define_insn "*cmptf_internal1" [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d") (match_operand:TF 2 "gpc_reg_operand" "d")))] - "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT - && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128" + "!TARGET_XL_COMPAT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT + && TARGET_LONG_DOUBLE_128" "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2" [(set_attr "type" "fpcompare") (set_attr "length" "12")]) @@ -11706,8 +11682,8 @@ (define_insn_and_split "*cmptf_internal2" (clobber (match_scratch:DF 9 "=d")) (clobber (match_scratch:DF 10 "=d")) (clobber (match_scratch:GPR 11 "=b"))] - "!TARGET_IEEEQUAD && TARGET_XL_COMPAT - && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128" + "TARGET_XL_COMPAT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT + && TARGET_LONG_DOUBLE_128" "#" "&& reload_completed" [(set (match_dup 3) (match_dup 14)) diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index 878b0fb..2067b8c 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -366,11 +366,8 @@ Target RejectNegative Undocumented Warn(using darwin64 ABI) Var(rs6000_darwin64_ mabi=d32 Target RejectNegative Undocumented Warn(using old darwin ABI) Var(rs6000_darwin64_abi, 0) -mabi=ieeelongdouble -Target RejectNegative Undocumented Warn(using IEEE extended precision long double) Var(rs6000_ieeequad) Save - mabi=ibmlongdouble -Target RejectNegative Undocumented Warn(using IBM extended precision long double) Var(rs6000_ieeequad, 0) +Target RejectNegative Undocumented Ignore mcpu= Target RejectNegative Joined Var(rs6000_cpu_index) Init(-1) Enum(rs6000_cpu_opt_value) Save diff --git a/gcc/config/rs6000/spe.md b/gcc/config/rs6000/spe.md index bf59b6c..a071119 100644 --- a/gcc/config/rs6000/spe.md +++ b/gcc/config/rs6000/spe.md @@ -2511,8 +2511,7 @@ (define_insn "spe_divdf3" (define_insn_and_split "spe_trunctfdf2_internal1" [(set (match_operand:DF 0 "gpc_reg_operand" "=r,?r") (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,r")))] - "!TARGET_IEEEQUAD - && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128" + "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128" "@ # evor %0,%1,%1" @@ -2527,8 +2526,7 @@ (define_insn_and_split "spe_trunctfsf2" [(set (match_operand:SF 0 "gpc_reg_operand" "=r") (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "r"))) (clobber (match_scratch:DF 2 "=r"))] - "!TARGET_IEEEQUAD - && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128" + "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128" "#" "&& reload_completed" [(set (match_dup 2) @@ -2541,8 +2539,7 @@ (define_insn "spe_extenddftf2" [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=r,?r,r,o") (float_extend:TF (match_operand:DF 1 "input_operand" "0,r,m,r"))) (clobber (match_scratch:DF 2 "=X,X,X,&r"))] - "!TARGET_IEEEQUAD - && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128" + "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128" "@ evxor %L0,%L0,%L0 evor %0,%1,%1\;evxor %L0,%L0,%L0 @@ -2556,8 +2553,7 @@ (define_expand "spe_fix_trunctfsi2" (clobber (match_dup 2)) (clobber (match_dup 3)) (clobber (match_dup 4))])] - "!TARGET_IEEEQUAD - && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128" + "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128" { operands[2] = gen_reg_rtx (DFmode); operands[3] = gen_reg_rtx (SImode); @@ -2571,16 +2567,14 @@ (define_insn "spe_fix_trunctfsi2_internal" (clobber (match_operand:DF 2 "gpc_reg_operand" "=r")) (clobber (match_operand:SI 3 "gpc_reg_operand" "=&r")) (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))] - "!TARGET_IEEEQUAD - && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128" + "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128" "mfspefscr %3\;rlwinm %4,%3,0,0,29\;ori %4,%4,1\;efdadd %2,%1,%L1\;mtspefscr %3\;efdctsiz %0, %2" [(set_attr "length" "24")]) (define_insn "spe_negtf2_internal" [(set (match_operand:TF 0 "gpc_reg_operand" "=r") (neg:TF (match_operand:TF 1 "gpc_reg_operand" "r")))] - "!TARGET_IEEEQUAD - && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128" + "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128" "* { if (REGNO (operands[0]) == REGNO (operands[1]) + 1) @@ -2601,8 +2595,7 @@ (define_expand "spe_abstf2_cmp" (label_ref (match_operand 2 "" "")) (pc))) (set (match_dup 6) (neg:DF (match_dup 6)))] - "!TARGET_IEEEQUAD - && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128" + "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128" " { const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode); @@ -2624,8 +2617,7 @@ (define_expand "spe_abstf2_tst" (label_ref (match_operand 2 "" "")) (pc))) (set (match_dup 6) (neg:DF (match_dup 6)))] - "!TARGET_IEEEQUAD - && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128" + "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128" " { const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode); @@ -3105,8 +3097,7 @@ (define_insn "cmptfeq_gpr" [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r") (match_operand:TF 2 "gpc_reg_operand" "r"))] CMPTFEQ_GPR))] - "!TARGET_IEEEQUAD - && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128 + "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128 && !(flag_finite_math_only && !flag_trapping_math)" "efdcmpeq %0,%1,%2\;bng %0,$+8\;efdcmpeq %0,%L1,%L2" [(set_attr "type" "veccmp") @@ -3118,8 +3109,7 @@ (define_insn "tsttfeq_gpr" [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r") (match_operand:TF 2 "gpc_reg_operand" "r"))] TSTTFEQ_GPR))] - "!TARGET_IEEEQUAD - && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128 + "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128 && flag_finite_math_only && !flag_trapping_math" "efdtsteq %0,%1,%2\;bng %0,$+8\;efdtsteq %0,%L1,%L2" [(set_attr "type" "veccmpsimple") @@ -3131,8 +3121,7 @@ (define_insn "cmptfgt_gpr" [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r") (match_operand:TF 2 "gpc_reg_operand" "r"))] CMPTFGT_GPR))] - "!TARGET_IEEEQUAD - && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128 + "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128 && !(flag_finite_math_only && !flag_trapping_math)" "efdcmpgt %0,%1,%2\;bgt %0,$+16\;efdcmpeq %0,%1,%2\;bng %0,$+8\;efdcmpgt %0,%L1,%L2" [(set_attr "type" "veccmp") @@ -3144,8 +3133,7 @@ (define_insn "tsttfgt_gpr" [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r") (match_operand:TF 2 "gpc_reg_operand" "r"))] TSTTFGT_GPR))] - "!TARGET_IEEEQUAD - && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128 + "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128 && flag_finite_math_only && !flag_trapping_math" "efdtstgt %0,%1,%2\;bgt %0,$+16\;efdtsteq %0,%1,%2\;bng %0,$+8\;efdtstgt %0,%L1,%L2" [(set_attr "type" "veccmpsimple") @@ -3157,8 +3145,7 @@ (define_insn "cmptflt_gpr" [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r") (match_operand:TF 2 "gpc_reg_operand" "r"))] CMPTFLT_GPR))] - "!TARGET_IEEEQUAD - && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128 + "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128 && !(flag_finite_math_only && !flag_trapping_math)" "efdcmplt %0,%1,%2\;bgt %0,$+16\;efdcmpeq %0,%1,%2\;bng %0,$+8\;efdcmplt %0,%L1,%L2" [(set_attr "type" "veccmp") @@ -3170,8 +3157,7 @@ (define_insn "tsttflt_gpr" [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r") (match_operand:TF 2 "gpc_reg_operand" "r"))] TSTTFLT_GPR))] - "!TARGET_IEEEQUAD - && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128 + "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128 && flag_finite_math_only && !flag_trapping_math" "efdtstlt %0,%1,%2\;bgt %0,$+16\;efdtsteq %0,%1,%2\;bng %0,$+8\;efdtstlt %0,%L1,%L2" [(set_attr "type" "veccmpsimple") diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index cf93dbf..4070ee7 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -17206,8 +17206,7 @@ SVR4 ABI)@. @item -mabi=@var{abi-type} @opindex mabi Extend the current ABI with a particular extension, or remove such extension. -Valid values are @var{altivec}, @var{no-altivec}, @var{spe}, -@var{no-spe}, @var{ibmlongdouble}, @var{ieeelongdouble}@. +Valid values are @var{altivec}, @var{no-altivec}, @var{spe}, @var{no-spe}@. @item -mabi=spe @opindex mabi=spe @@ -17219,16 +17218,6 @@ ABI@. @opindex mabi=no-spe Disable Booke SPE ABI extensions for the current ABI@. -@item -mabi=ibmlongdouble -@opindex mabi=ibmlongdouble -Change the current ABI to use IBM extended-precision long double. -This is a PowerPC 32-bit SYSV ABI option. - -@item -mabi=ieeelongdouble -@opindex mabi=ieeelongdouble -Change the current ABI to use IEEE extended-precision long double. -This is a PowerPC 32-bit Linux ABI option. - @item -mprototype @itemx -mno-prototype @opindex mprototype

[6/7] rs6000: Remove -mabi=ieeelongdouble.

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