[5/7] rs6000: Get rid of old-mnemonics

Message ID	edc141b3eec7d6ff8b0acd3f0e2f9d5423e01257.1345067650.git.segher@kernel.crashing.org
State	New
Headers	show Return-Path: <gcc-patches-return-324583-incoming=patchwork.ozlabs.org@gcc.gnu.org> Comment: DKIM? See http://www.dkim.org Comment: DomainKeys? See http://antispam.yahoo.com/domainkeys DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=default; d=gcc.gnu.org; h=Received:Received:X-SWARE-Spam-Status:X-Spam-Check-By:Received:Received:Received:From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:In-Reply-To:References:X-IsSubscribed:Mailing-List:Precedence:List-Id:List-Unsubscribe:List-Archive:List-Post:List-Help:Sender:Delivered-To; b=GWfwMIOPJXEIShx8h2aco8Q7ogWStHcU9KElhukZ99+Opp0IApQXyoMaZ0zIkq GxJxJZGvnGrjX/X+zRp80O1Ae6I3jrIsjOOVrchO14SyRz4SAm4Qd06WgZsvTfsz OaYPf5zlbcQ0BBQ0XB7hxijKpyjstzyKeYCTb5uPujrqk=; From: Segher Boessenkool <segher@kernel.crashing.org> To: gcc-patches@gcc.gnu.org Cc: dje.gcc@gmail.com, meissner@gcc.gnu.org, Segher Boessenkool <segher@kernel.crashing.org> Subject: [PATCH 5/7] rs6000: Get rid of old-mnemonics Date: Wed, 15 Aug 2012 15:29:21 -0700 Message-Id: <edc141b3eec7d6ff8b0acd3f0e2f9d5423e01257.1345067650.git.segher@kernel.crashing.org> In-Reply-To: <cover.1345067650.git.segher@kernel.crashing.org> References: <cover.1345067650.git.segher@kernel.crashing.org> In-Reply-To: <cover.1345067650.git.segher@kernel.crashing.org> References: <cover.1345067650.git.segher@kernel.crashing.org> Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk Sender: gcc-patches-owner@gcc.gnu.org

diff --git a/gcc/config/rs6000/aix43.h b/gcc/config/rs6000/aix43.h index e4863ef..8465c20 100644 --- a/gcc/config/rs6000/aix43.h +++ b/gcc/config/rs6000/aix43.h @@ -93,7 +93,7 @@ do { \ %{pthread: -D_THREAD_SAFE}" #undef TARGET_DEFAULT -#define TARGET_DEFAULT MASK_NEW_MNEMONICS +#define TARGET_DEFAULT 0 #undef PROCESSOR_DEFAULT #define PROCESSOR_DEFAULT PROCESSOR_PPC604e @@ -146,7 +146,7 @@ do { \ and "cror 31,31,31" for POWER architecture. */ #undef RS6000_CALL_GLUE -#define RS6000_CALL_GLUE "{cror 31,31,31|nop}" +#define RS6000_CALL_GLUE "nop" /* AIX 4.2 and above provides initialization and finalization function support from linker command line. */ diff --git a/gcc/config/rs6000/aix51.h b/gcc/config/rs6000/aix51.h index effd278..a140e12 100644 --- a/gcc/config/rs6000/aix51.h +++ b/gcc/config/rs6000/aix51.h @@ -90,7 +90,7 @@ do { \ %{pthread: -D_THREAD_SAFE}" #undef TARGET_DEFAULT -#define TARGET_DEFAULT MASK_NEW_MNEMONICS +#define TARGET_DEFAULT 0 #undef PROCESSOR_DEFAULT #define PROCESSOR_DEFAULT PROCESSOR_PPC604e @@ -150,7 +150,7 @@ do { \ and "cror 31,31,31" for POWER architecture. */ #undef RS6000_CALL_GLUE -#define RS6000_CALL_GLUE "{cror 31,31,31|nop}" +#define RS6000_CALL_GLUE "nop" /* AIX 4.2 and above provides initialization and finalization function support from linker command line. */ diff --git a/gcc/config/rs6000/aix52.h b/gcc/config/rs6000/aix52.h index a5f1ca7..1c9e77f 100644 --- a/gcc/config/rs6000/aix52.h +++ b/gcc/config/rs6000/aix52.h @@ -99,7 +99,7 @@ do { \ %{pthread: -D_THREAD_SAFE}" #undef TARGET_DEFAULT -#define TARGET_DEFAULT MASK_NEW_MNEMONICS +#define TARGET_DEFAULT 0 #undef PROCESSOR_DEFAULT #define PROCESSOR_DEFAULT PROCESSOR_POWER4 @@ -162,7 +162,7 @@ do { \ and "cror 31,31,31" for POWER architecture. */ #undef RS6000_CALL_GLUE -#define RS6000_CALL_GLUE "{cror 31,31,31|nop}" +#define RS6000_CALL_GLUE "nop" /* AIX 4.2 and above provides initialization and finalization function support from linker command line. */ diff --git a/gcc/config/rs6000/aix53.h b/gcc/config/rs6000/aix53.h index 5c72d57..d1a99e9 100644 --- a/gcc/config/rs6000/aix53.h +++ b/gcc/config/rs6000/aix53.h @@ -105,7 +105,7 @@ do { \ %{pthread: -D_THREAD_SAFE}" #undef TARGET_DEFAULT -#define TARGET_DEFAULT MASK_NEW_MNEMONICS +#define TARGET_DEFAULT 0 #undef PROCESSOR_DEFAULT #define PROCESSOR_DEFAULT PROCESSOR_POWER5 @@ -160,7 +160,7 @@ do { \ and "cror 31,31,31" for POWER architecture. */ #undef RS6000_CALL_GLUE -#define RS6000_CALL_GLUE "{cror 31,31,31|nop}" +#define RS6000_CALL_GLUE "nop" /* AIX 4.2 and above provides initialization and finalization function support from linker command line. */ diff --git a/gcc/config/rs6000/aix61.h b/gcc/config/rs6000/aix61.h index c9a89fb..663777c 100644 --- a/gcc/config/rs6000/aix61.h +++ b/gcc/config/rs6000/aix61.h @@ -106,7 +106,7 @@ do { \ %{pthread: -D_THREAD_SAFE}" #undef TARGET_DEFAULT -#define TARGET_DEFAULT MASK_NEW_MNEMONICS +#define TARGET_DEFAULT 0 #undef PROCESSOR_DEFAULT #define PROCESSOR_DEFAULT PROCESSOR_POWER7 @@ -161,7 +161,7 @@ do { \ and "cror 31,31,31" for POWER architecture. */ #undef RS6000_CALL_GLUE -#define RS6000_CALL_GLUE "{cror 31,31,31|nop}" +#define RS6000_CALL_GLUE "nop" /* AIX 4.2 and above provides initialization and finalization function support from linker command line. */ diff --git a/gcc/config/rs6000/darwin.h b/gcc/config/rs6000/darwin.h index 13d53f5..17ff675 100644 --- a/gcc/config/rs6000/darwin.h +++ b/gcc/config/rs6000/darwin.h @@ -280,7 +280,7 @@ extern int darwin_emit_branch_islands; default as well. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_MULTIPLE | MASK_NEW_MNEMONICS | MASK_PPC_GFXOPT) +#define TARGET_DEFAULT (MASK_MULTIPLE | MASK_PPC_GFXOPT) /* Darwin only runs on PowerPC, so short-circuit POWER patterns. */ #undef TARGET_IEEEQUAD diff --git a/gcc/config/rs6000/darwin.md b/gcc/config/rs6000/darwin.md index e811822..c456934 100644 --- a/gcc/config/rs6000/darwin.md +++ b/gcc/config/rs6000/darwin.md @@ -23,7 +23,7 @@ (define_insn "adddi3_high" (plus:DI (match_operand:DI 1 "gpc_reg_operand" "b") (high:DI (match_operand 2 "" ""))))] "TARGET_MACHO && TARGET_64BIT" - "{cau|addis} %0,%1,ha16(%2)" + "addis %0,%1,ha16(%2)" [(set_attr "length" "4")]) (define_insn "movdf_low_si" @@ -44,9 +44,9 @@ (define_insn "movdf_low_si" return \"ld %0,lo16(%2)(%1)\"; else { - output_asm_insn (\"{cal|la} %0,lo16(%2)(%1)\", operands); - output_asm_insn (\"{l|lwz} %L0,4(%0)\", operands); - return (\"{l|lwz} %0,0(%0)\"); + output_asm_insn (\"la %0,lo16(%2)(%1)\", operands); + output_asm_insn (\"lwz %L0,4(%0)\", operands); + return (\"lwz %0,0(%0)\"); } } default: @@ -102,7 +102,7 @@ (define_insn "movsf_low_si" "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT" "@ lfs %0,lo16(%2)(%1) - {l|lwz} %0,lo16(%2)(%1)" + lwz %0,lo16(%2)(%1)" [(set_attr "type" "load") (set_attr "length" "4")]) @@ -113,7 +113,7 @@ (define_insn "movsf_low_di" "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT" "@ lfs %0,lo16(%2)(%1) - {l|lwz} %0,lo16(%2)(%1)" + lwz %0,lo16(%2)(%1)" [(set_attr "type" "load") (set_attr "length" "4")]) @@ -124,7 +124,7 @@ (define_insn "movsf_low_st_si" "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT" "@ stfs %0,lo16(%2)(%1) - {st|stw} %0,lo16(%2)(%1)" + stw %0,lo16(%2)(%1)" [(set_attr "type" "store") (set_attr "length" "4")]) @@ -135,7 +135,7 @@ (define_insn "movsf_low_st_di" "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT" "@ stfs %0,lo16(%2)(%1) - {st|stw} %0,lo16(%2)(%1)" + stw %0,lo16(%2)(%1)" [(set_attr "type" "store") (set_attr "length" "4")]) @@ -146,7 +146,7 @@ (define_insn "movdi_low" (match_operand 2 "" ""))))] "TARGET_MACHO && TARGET_64BIT" "@ - {l|ld} %0,lo16(%2)(%1) + ld %0,lo16(%2)(%1) lfd %0,lo16(%2)(%1)" [(set_attr "type" "load") (set_attr "length" "4")]) @@ -156,7 +156,7 @@ (define_insn "movsi_low_st" (match_operand 2 "" ""))) (match_operand:SI 0 "gpc_reg_operand" "r"))] "TARGET_MACHO && ! TARGET_64BIT" - "{st|stw} %0,lo16(%2)(%1)" + "stw %0,lo16(%2)(%1)" [(set_attr "type" "store") (set_attr "length" "4")]) @@ -166,7 +166,7 @@ (define_insn "movdi_low_st" (match_operand:DI 0 "gpc_reg_operand" "r,*!d"))] "TARGET_MACHO && TARGET_64BIT" "@ - {st|std} %0,lo16(%2)(%1) + std %0,lo16(%2)(%1) stfd %0,lo16(%2)(%1)" [(set_attr "type" "store") (set_attr "length" "4")]) @@ -189,14 +189,14 @@ (define_insn "macho_high_si" [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r") (high:SI (match_operand 1 "" "")))] "TARGET_MACHO && ! TARGET_64BIT" - "{liu|lis} %0,ha16(%1)") + "lis %0,ha16(%1)") (define_insn "macho_high_di" [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r") (high:DI (match_operand 1 "" "")))] "TARGET_MACHO && TARGET_64BIT" - "{liu|lis} %0,ha16(%1)") + "lis %0,ha16(%1)") (define_expand "macho_low" [(set (match_operand 0 "" "") @@ -218,8 +218,8 @@ (define_insn "macho_low_si" (match_operand 2 "" "")))] "TARGET_MACHO && ! TARGET_64BIT" "@ - {cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)} - {cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}") + la %0,lo16(%2)(%1) + addic %0,%1,lo16(%2)") (define_insn "macho_low_di" [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") @@ -227,8 +227,8 @@ (define_insn "macho_low_di" (match_operand 2 "" "")))] "TARGET_MACHO && TARGET_64BIT" "@ - {cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)} - {cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}") + la %0,lo16(%2)(%1) + addic %0,%1,lo16(%2)") (define_split [(set (mem:V4SI (plus:DI (match_operand:DI 0 "gpc_reg_operand" "") diff --git a/gcc/config/rs6000/darwin64.h b/gcc/config/rs6000/darwin64.h index fbda740..6278183 100644 --- a/gcc/config/rs6000/darwin64.h +++ b/gcc/config/rs6000/darwin64.h @@ -20,7 +20,7 @@ #undef TARGET_DEFAULT #define TARGET_DEFAULT (MASK_POWERPC64 | MASK_64BIT \ - | MASK_MULTIPLE | MASK_NEW_MNEMONICS | MASK_PPC_GFXOPT) + | MASK_MULTIPLE | MASK_PPC_GFXOPT) #undef DARWIN_ARCH_SPEC #define DARWIN_ARCH_SPEC "%{m32:ppc;:ppc64}" diff --git a/gcc/config/rs6000/default64.h b/gcc/config/rs6000/default64.h index 7206671..0780572 100644 --- a/gcc/config/rs6000/default64.h +++ b/gcc/config/rs6000/default64.h @@ -19,5 +19,4 @@ along with GCC; see the file COPYING3. If not see <http://www.gnu.org/licenses/>. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT \ - (MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_64BIT | MASK_NEW_MNEMONICS) +#define TARGET_DEFAULT (MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_64BIT) diff --git a/gcc/config/rs6000/dfp.md b/gcc/config/rs6000/dfp.md index d2fd12b..9dadf6f 100644 --- a/gcc/config/rs6000/dfp.md +++ b/gcc/config/rs6000/dfp.md @@ -68,12 +68,12 @@ (define_insn "movsd_hardfloat" && (TARGET_HARD_FLOAT && TARGET_FPRS)" "@ mr %0,%1 - {l%U1%X1|lwz%U1%X1} %0,%1 - {st%U0%X0|stw%U0%X0} %1,%0 + lwz%U1%X1 %0,%1 + stw%U0%X0 %1,%0 fmr %0,%1 mt%0 %1 mf%1 %0 - {cror 0,0,0|nop} + nop # #" [(set_attr "type" "*,load,store,fp,mtjmpr,mfjmpr,*,*,*") @@ -89,14 +89,14 @@ (define_insn "movsd_softfloat" mr %0,%1 mt%0 %1 mf%1 %0 - {l%U1%X1|lwz%U1%X1} %0,%1 - {st%U0%X0|stw%U0%X0} %1,%0 - {lil|li} %0,%1 - {liu|lis} %0,%v1 - {cal|la} %0,%a1 + lwz%U1%X1 %0,%1 + stw%U0%X0 %1,%0 + li %0,%1 + lis %0,%v1 + la %0,%a1 # # - {cror 0,0,0|nop}" + nop" [(set_attr "type" "*,mtjmpr,mfjmpr,load,store,*,*,*,*,*,*") (set_attr "length" "4,4,4,4,4,4,4,4,4,8,4")]) @@ -335,7 +335,7 @@ (define_insn "*movdd_hardfloat64_mfpgpr" stfd%U0%X0 %1,%0 mt%0 %1 mf%1 %0 - {cror 0,0,0|nop} + nop # # # @@ -361,7 +361,7 @@ (define_insn "*movdd_hardfloat64" stfd%U0%X0 %1,%0 mt%0 %1 mf%1 %0 - {cror 0,0,0|nop} + nop # # #" @@ -383,7 +383,7 @@ (define_insn "*movdd_softfloat64" # # # - {cror 0,0,0|nop}" + nop" [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*") (set_attr "length" "4,4,4,4,4,8,12,16,4")]) diff --git a/gcc/config/rs6000/eabi.h b/gcc/config/rs6000/eabi.h index 07854e2..cb0c6bd 100644 --- a/gcc/config/rs6000/eabi.h +++ b/gcc/config/rs6000/eabi.h @@ -22,7 +22,7 @@ /* Add -meabi to target flags. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_NEW_MNEMONICS | MASK_EABI) +#define TARGET_DEFAULT MASK_EABI /* Invoke an initializer function to set up the GOT. */ #define NAME__MAIN "__eabi" diff --git a/gcc/config/rs6000/eabialtivec.h b/gcc/config/rs6000/eabialtivec.h index aaabbf4..bf0fdf1 100644 --- a/gcc/config/rs6000/eabialtivec.h +++ b/gcc/config/rs6000/eabialtivec.h @@ -21,7 +21,7 @@ /* Add -meabi and -maltivec to target flags. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_NEW_MNEMONICS | MASK_EABI | MASK_ALTIVEC) +#define TARGET_DEFAULT (MASK_EABI | MASK_ALTIVEC) #undef SUBSUBTARGET_OVERRIDE_OPTIONS #define SUBSUBTARGET_OVERRIDE_OPTIONS rs6000_altivec_abi = 1 diff --git a/gcc/config/rs6000/eabispe.h b/gcc/config/rs6000/eabispe.h index 89cdfde..68657f1 100644 --- a/gcc/config/rs6000/eabispe.h +++ b/gcc/config/rs6000/eabispe.h @@ -21,7 +21,7 @@ <http://www.gnu.org/licenses/>. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_NEW_MNEMONICS | MASK_STRICT_ALIGN | MASK_EABI) +#define TARGET_DEFAULT (MASK_STRICT_ALIGN | MASK_EABI) #undef ASM_DEFAULT_SPEC #define ASM_DEFAULT_SPEC "-mppc -mspe -me500" diff --git a/gcc/config/rs6000/linuxaltivec.h b/gcc/config/rs6000/linuxaltivec.h index 1f79e22..df876f9 100644 --- a/gcc/config/rs6000/linuxaltivec.h +++ b/gcc/config/rs6000/linuxaltivec.h @@ -21,7 +21,7 @@ /* Override rs6000.h and sysv4.h definition. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_NEW_MNEMONICS | MASK_ALTIVEC) +#define TARGET_DEFAULT MASK_ALTIVEC #undef SUBSUBTARGET_OVERRIDE_OPTIONS #define SUBSUBTARGET_OVERRIDE_OPTIONS rs6000_altivec_abi = 1 diff --git a/gcc/config/rs6000/linuxspe.h b/gcc/config/rs6000/linuxspe.h index afe69f8..6b976af 100644 --- a/gcc/config/rs6000/linuxspe.h +++ b/gcc/config/rs6000/linuxspe.h @@ -22,7 +22,7 @@ /* Override rs6000.h and sysv4.h definition. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_NEW_MNEMONICS | MASK_STRICT_ALIGN) +#define TARGET_DEFAULT MASK_STRICT_ALIGN #undef ASM_DEFAULT_SPEC #define ASM_DEFAULT_SPEC "-mppc -mspe -me500" diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index 5d76f6a..cfac0e7 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -32,101 +32,78 @@ where the arguments are the fields of struct rs6000_ptt. */ -RS6000_CPU ("401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT) -RS6000_CPU ("403", PROCESSOR_PPC403, - POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN) -RS6000_CPU ("405", PROCESSOR_PPC405, - POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB) -RS6000_CPU ("405fp", PROCESSOR_PPC405, - POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB) -RS6000_CPU ("440", PROCESSOR_PPC440, - POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB) -RS6000_CPU ("440fp", PROCESSOR_PPC440, - POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB) -RS6000_CPU ("464", PROCESSOR_PPC440, - POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB) -RS6000_CPU ("464fp", PROCESSOR_PPC440, - POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB) +RS6000_CPU ("401", PROCESSOR_PPC403, MASK_SOFT_FLOAT) +RS6000_CPU ("403", PROCESSOR_PPC403, MASK_SOFT_FLOAT | MASK_STRICT_ALIGN) +RS6000_CPU ("405", PROCESSOR_PPC405, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB) +RS6000_CPU ("405fp", PROCESSOR_PPC405, MASK_MULHW | MASK_DLMZB) +RS6000_CPU ("440", PROCESSOR_PPC440, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB) +RS6000_CPU ("440fp", PROCESSOR_PPC440, MASK_MULHW | MASK_DLMZB) +RS6000_CPU ("464", PROCESSOR_PPC440, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB) +RS6000_CPU ("464fp", PROCESSOR_PPC440, MASK_MULHW | MASK_DLMZB) RS6000_CPU ("476", PROCESSOR_PPC476, - POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_PPC_GFXOPT | MASK_MFCRF - | MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_MULHW | MASK_DLMZB) -RS6000_CPU ("476fp", PROCESSOR_PPC476, - POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB + MASK_SOFT_FLOAT | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_MULHW | MASK_DLMZB) -RS6000_CPU ("505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK) -RS6000_CPU ("601", PROCESSOR_PPC601, - POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING) -RS6000_CPU ("602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT) -RS6000_CPU ("603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT) -RS6000_CPU ("603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT) -RS6000_CPU ("604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT) -RS6000_CPU ("604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT) -RS6000_CPU ("620", PROCESSOR_PPC620, - POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64) -RS6000_CPU ("630", PROCESSOR_PPC630, - POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64) -RS6000_CPU ("740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT) +RS6000_CPU ("476fp", PROCESSOR_PPC476, + MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND + | MASK_CMPB | MASK_MULHW | MASK_DLMZB) +RS6000_CPU ("505", PROCESSOR_MPCCORE, 0) +RS6000_CPU ("601", PROCESSOR_PPC601, MASK_MULTIPLE | MASK_STRING) +RS6000_CPU ("602", PROCESSOR_PPC603, MASK_PPC_GFXOPT) +RS6000_CPU ("603", PROCESSOR_PPC603, MASK_PPC_GFXOPT) +RS6000_CPU ("603e", PROCESSOR_PPC603, MASK_PPC_GFXOPT) +RS6000_CPU ("604", PROCESSOR_PPC604, MASK_PPC_GFXOPT) +RS6000_CPU ("604e", PROCESSOR_PPC604e, MASK_PPC_GFXOPT) +RS6000_CPU ("620", PROCESSOR_PPC620, MASK_PPC_GFXOPT | MASK_POWERPC64) +RS6000_CPU ("630", PROCESSOR_PPC630, MASK_PPC_GFXOPT | MASK_POWERPC64) +RS6000_CPU ("740", PROCESSOR_PPC750, MASK_PPC_GFXOPT) RS6000_CPU ("7400", PROCESSOR_PPC7400, POWERPC_7400_MASK) RS6000_CPU ("7450", PROCESSOR_PPC7450, POWERPC_7400_MASK) -RS6000_CPU ("750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT) -RS6000_CPU ("801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT) -RS6000_CPU ("821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT) -RS6000_CPU ("823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT) -RS6000_CPU ("8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN - | MASK_ISEL) -RS6000_CPU ("8548", PROCESSOR_PPC8548, POWERPC_BASE_MASK | MASK_STRICT_ALIGN - | MASK_ISEL) +RS6000_CPU ("750", PROCESSOR_PPC750, MASK_PPC_GFXOPT) +RS6000_CPU ("801", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT) +RS6000_CPU ("821", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT) +RS6000_CPU ("823", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT) +RS6000_CPU ("8540", PROCESSOR_PPC8540, MASK_STRICT_ALIGN | MASK_ISEL) +RS6000_CPU ("8548", PROCESSOR_PPC8548, MASK_STRICT_ALIGN | MASK_ISEL) RS6000_CPU ("a2", PROCESSOR_PPCA2, - POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_POPCNTB - | MASK_CMPB | MASK_NO_UPDATE) -RS6000_CPU ("e300c2", PROCESSOR_PPCE300C2, POWERPC_BASE_MASK | MASK_SOFT_FLOAT) -RS6000_CPU ("e300c3", PROCESSOR_PPCE300C3, POWERPC_BASE_MASK) -RS6000_CPU ("e500mc", PROCESSOR_PPCE500MC, POWERPC_BASE_MASK | MASK_PPC_GFXOPT - | MASK_ISEL) + MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_POPCNTB | MASK_CMPB + | MASK_NO_UPDATE) +RS6000_CPU ("e300c2", PROCESSOR_PPCE300C2, MASK_SOFT_FLOAT) +RS6000_CPU ("e300c3", PROCESSOR_PPCE300C3, 0) +RS6000_CPU ("e500mc", PROCESSOR_PPCE500MC, MASK_PPC_GFXOPT | MASK_ISEL) RS6000_CPU ("e500mc64", PROCESSOR_PPCE500MC64, - POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL) -RS6000_CPU ("e5500", PROCESSOR_PPCE5500, POWERPC_BASE_MASK | MASK_POWERPC64 - | MASK_PPC_GFXOPT | MASK_ISEL) + MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL) +RS6000_CPU ("e5500", PROCESSOR_PPCE5500, + MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL) RS6000_CPU ("e6500", PROCESSOR_PPCE6500, POWERPC_7400_MASK | MASK_POWERPC64 | MASK_MFCRF | MASK_ISEL) -RS6000_CPU ("860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT) +RS6000_CPU ("860", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT) RS6000_CPU ("970", PROCESSOR_POWER4, POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64) RS6000_CPU ("cell", PROCESSOR_CELL, POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64) -RS6000_CPU ("common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS) -RS6000_CPU ("ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT) -RS6000_CPU ("G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT) +RS6000_CPU ("ec603e", PROCESSOR_PPC603, MASK_SOFT_FLOAT) +RS6000_CPU ("G3", PROCESSOR_PPC750, MASK_PPC_GFXOPT) RS6000_CPU ("G4", PROCESSOR_PPC7450, POWERPC_7400_MASK) RS6000_CPU ("G5", PROCESSOR_POWER4, POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64) -RS6000_CPU ("titan", PROCESSOR_TITAN, - POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB) -RS6000_CPU ("power3", PROCESSOR_PPC630, - POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64) -RS6000_CPU ("power4", PROCESSOR_POWER4, - POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT +RS6000_CPU ("titan", PROCESSOR_TITAN, MASK_MULHW | MASK_DLMZB) +RS6000_CPU ("power3", PROCESSOR_PPC630, MASK_PPC_GFXOPT | MASK_POWERPC64) +RS6000_CPU ("power4", PROCESSOR_POWER4, MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_PPC_GFXOPT | MASK_MFCRF) -RS6000_CPU ("power5", PROCESSOR_POWER5, - POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT +RS6000_CPU ("power5", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB) -RS6000_CPU ("power5+", PROCESSOR_POWER5, - POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT +RS6000_CPU ("power5+", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND) -RS6000_CPU ("power6", PROCESSOR_POWER6, - POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT +RS6000_CPU ("power6", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP | MASK_RECIP_PRECISION) -RS6000_CPU ("power6x", PROCESSOR_POWER6, - POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT +RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP | MASK_MFPGPR | MASK_RECIP_PRECISION) RS6000_CPU ("power7", PROCESSOR_POWER7, /* Don't add MASK_ISEL by default */ POWERPC_7400_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP | MASK_POPCNTD | MASK_VSX | MASK_RECIP_PRECISION) -RS6000_CPU ("powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK) -RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, - POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64) -RS6000_CPU ("rs64", PROCESSOR_RS64A, - POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64) +RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0) +RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT | MASK_POWERPC64) +RS6000_CPU ("rs64", PROCESSOR_RS64A, MASK_PPC_GFXOPT | MASK_POWERPC64) diff --git a/gcc/config/rs6000/rs6000-tables.opt b/gcc/config/rs6000/rs6000-tables.opt index 26e700f..f63d9c4 100644 --- a/gcc/config/rs6000/rs6000-tables.opt +++ b/gcc/config/rs6000/rs6000-tables.opt @@ -141,50 +141,47 @@ EnumValue Enum(rs6000_cpu_opt_value) String(cell) Value(37) EnumValue -Enum(rs6000_cpu_opt_value) String(common) Value(38) +Enum(rs6000_cpu_opt_value) String(ec603e) Value(38) EnumValue -Enum(rs6000_cpu_opt_value) String(ec603e) Value(39) +Enum(rs6000_cpu_opt_value) String(G3) Value(39) EnumValue -Enum(rs6000_cpu_opt_value) String(G3) Value(40) +Enum(rs6000_cpu_opt_value) String(G4) Value(40) EnumValue -Enum(rs6000_cpu_opt_value) String(G4) Value(41) +Enum(rs6000_cpu_opt_value) String(G5) Value(41) EnumValue -Enum(rs6000_cpu_opt_value) String(G5) Value(42) +Enum(rs6000_cpu_opt_value) String(titan) Value(42) EnumValue -Enum(rs6000_cpu_opt_value) String(titan) Value(43) +Enum(rs6000_cpu_opt_value) String(power3) Value(43) EnumValue -Enum(rs6000_cpu_opt_value) String(power3) Value(44) +Enum(rs6000_cpu_opt_value) String(power4) Value(44) EnumValue -Enum(rs6000_cpu_opt_value) String(power4) Value(45) +Enum(rs6000_cpu_opt_value) String(power5) Value(45) EnumValue -Enum(rs6000_cpu_opt_value) String(power5) Value(46) +Enum(rs6000_cpu_opt_value) String(power5+) Value(46) EnumValue -Enum(rs6000_cpu_opt_value) String(power5+) Value(47) +Enum(rs6000_cpu_opt_value) String(power6) Value(47) EnumValue -Enum(rs6000_cpu_opt_value) String(power6) Value(48) +Enum(rs6000_cpu_opt_value) String(power6x) Value(48) EnumValue -Enum(rs6000_cpu_opt_value) String(power6x) Value(49) +Enum(rs6000_cpu_opt_value) String(power7) Value(49) EnumValue -Enum(rs6000_cpu_opt_value) String(power7) Value(50) +Enum(rs6000_cpu_opt_value) String(powerpc) Value(50) EnumValue -Enum(rs6000_cpu_opt_value) String(powerpc) Value(51) +Enum(rs6000_cpu_opt_value) String(powerpc64) Value(51) EnumValue -Enum(rs6000_cpu_opt_value) String(powerpc64) Value(52) - -EnumValue -Enum(rs6000_cpu_opt_value) String(rs64) Value(53) +Enum(rs6000_cpu_opt_value) String(rs64) Value(52) diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index d979b30..4571c6f 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -1457,8 +1457,7 @@ static const struct attribute_spec rs6000_attribute_table[] = /* Simplifications for entries below. */ enum { - POWERPC_BASE_MASK = MASK_NEW_MNEMONICS, - POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC + POWERPC_7400_MASK = MASK_PPC_GFXOPT | MASK_ALTIVEC }; /* Some OSs don't support saving the high part of 64-bit registers on context @@ -1468,7 +1467,7 @@ enum { the user's specification. */ enum { - POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT | MASK_STRICT_ALIGN + POWERPC_MASKS = (MASK_PPC_GPOPT | MASK_STRICT_ALIGN | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW | MASK_DLMZB | MASK_CMPB | MASK_MFPGPR | MASK_DFP @@ -4023,11 +4022,11 @@ direct_return (void) int num_insns_constant_wide (HOST_WIDE_INT value) { - /* signed constant loadable with {cal|addi} */ + /* signed constant loadable with addi */ if ((unsigned HOST_WIDE_INT) (value + 0x8000) < 0x10000) return 1; - /* constant loadable with {cau|addis} */ + /* constant loadable with addis */ else if ((value & 0xffff) == 0 && (value >> 31 == -1 || value >> 31 == 0)) return 1; @@ -13027,7 +13026,7 @@ rs6000_output_load_multiple (rtx operands[3]) rtx xop[10]; if (XVECLEN (operands[0], 0) == 1) - return "{l|lwz} %2,0(%1)"; + return "lwz %2,0(%1)"; for (i = 0; i < words; i++) if (refers_to_regno_p (REGNO (operands[2]) + i, @@ -13038,7 +13037,7 @@ rs6000_output_load_multiple (rtx operands[3]) xop[0] = GEN_INT (4 * (words-1)); xop[1] = operands[1]; xop[2] = operands[2]; - output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop); + output_asm_insn ("lswi %2,%1,%0\n\tlwz %1,%0(%1)", xop); return ""; } else if (i == 0) @@ -13046,7 +13045,7 @@ rs6000_output_load_multiple (rtx operands[3]) xop[0] = GEN_INT (4 * (words-1)); xop[1] = operands[1]; xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); - output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop); + output_asm_insn ("addi %1,%1,4\n\tlswi %2,%1,%0\n\tlwz %1,-4(%1)", xop); return ""; } else @@ -13057,16 +13056,16 @@ rs6000_output_load_multiple (rtx operands[3]) xop[0] = GEN_INT (j * 4); xop[1] = operands[1]; xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j); - output_asm_insn ("{l|lwz} %2,%0(%1)", xop); + output_asm_insn ("lwz %2,%0(%1)", xop); } xop[0] = GEN_INT (i * 4); xop[1] = operands[1]; - output_asm_insn ("{l|lwz} %1,%0(%1)", xop); + output_asm_insn ("lwz %1,%0(%1)", xop); return ""; } } - return "{lsi|lswi} %2,%1,%N0"; + return "lswi %2,%1,%N0"; } @@ -14957,7 +14956,7 @@ print_operand (FILE *file, rtx x, int code) && REGNO (x) != CTR_REGNO)) output_operand_lossage ("invalid %%T value"); else if (REGNO (x) == LR_REGNO) - fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file); + fputs ("lr", file); else fputs ("ctr", file); return; @@ -15922,8 +15921,7 @@ output_cbranch (rtx op, const char *label, int reversed, rtx insn) gcc_unreachable (); } - /* Maybe we have a guess as to how likely the branch is. - The old mnemonics don't have a way to specify this information. */ + /* Maybe we have a guess as to how likely the branch is. */ pred = ""; note = find_reg_note (insn, REG_BR_PROB, NULL_RTX); if (note != NULL_RTX) @@ -15950,9 +15948,9 @@ output_cbranch (rtx op, const char *label, int reversed, rtx insn) } if (label == NULL) - s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred); + s += sprintf (s, "b%slr%s ", ccode, pred); else - s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred); + s += sprintf (s, "b%s%s ", ccode, pred); /* We need to escape any '%' characters in the reg_names string. Assume they'd only be the first character.... */ @@ -18788,9 +18786,9 @@ output_probe_stack_range (rtx reg1, rtx reg2) xops[0] = reg1; xops[1] = reg2; if (TARGET_64BIT) - output_asm_insn ("{cmp|cmpd} 0,%0,%1", xops); + output_asm_insn ("cmpd 0,%0,%1", xops); else - output_asm_insn ("{cmp|cmpw} 0,%0,%1", xops); + output_asm_insn ("cmpw 0,%0,%1", xops); fputs ("\tbeq 0,", asm_out_file); assemble_name_raw (asm_out_file, end_lab); @@ -18798,11 +18796,11 @@ output_probe_stack_range (rtx reg1, rtx reg2) /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */ xops[1] = GEN_INT (-PROBE_INTERVAL); - output_asm_insn ("{cal %0,%1(%0)|addi %0,%0,%1}", xops); + output_asm_insn ("addi %0,%0,%1", xops); /* Probe at TEST_ADDR and branch. */ xops[1] = gen_rtx_REG (Pmode, 0); - output_asm_insn ("{st|stw} %1,0(%0)", xops); + output_asm_insn ("stw %1,0(%0)", xops); fprintf (asm_out_file, "\tb "); assemble_name_raw (asm_out_file, loop_lab); fputc ('\n', asm_out_file); @@ -22351,7 +22349,7 @@ output_function_profiler (FILE *file, int labelno) fprintf (file, "\tmflr %s\n", reg_names[0]); if (NO_PROFILE_COUNTERS) { - asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", + asm_fprintf (file, "\tstw %s,4(%s)\n", reg_names[0], reg_names[1]); } else if (TARGET_SECURE_PLT && flag_pic) @@ -22364,29 +22362,29 @@ output_function_profiler (FILE *file, int labelno) } else asm_fprintf (file, "\tbcl 20,31,1f\n1:\n"); - asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", + asm_fprintf (file, "\tstw %s,4(%s)\n", reg_names[0], reg_names[1]); asm_fprintf (file, "\tmflr %s\n", reg_names[12]); - asm_fprintf (file, "\t{cau|addis} %s,%s,", + asm_fprintf (file, "\taddis %s,%s,", reg_names[12], reg_names[12]); assemble_name (file, buf); - asm_fprintf (file, "-1b@ha\n\t{cal|la} %s,", reg_names[0]); + asm_fprintf (file, "-1b@ha\n\tla %s,", reg_names[0]); assemble_name (file, buf); asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]); } else if (flag_pic == 1) { fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file); - asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", + asm_fprintf (file, "\tstw %s,4(%s)\n", reg_names[0], reg_names[1]); asm_fprintf (file, "\tmflr %s\n", reg_names[12]); - asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]); + asm_fprintf (file, "\tlwz %s,", reg_names[0]); assemble_name (file, buf); asm_fprintf (file, "@got(%s)\n", reg_names[12]); } else if (flag_pic > 1) { - asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", + asm_fprintf (file, "\tstw %s,4(%s)\n", reg_names[0], reg_names[1]); /* Now, we need to get the address of the label. */ if (TARGET_LINK_STACK) @@ -22407,19 +22405,19 @@ output_function_profiler (FILE *file, int labelno) fputs ("-.\n1:", file); asm_fprintf (file, "\tmflr %s\n", reg_names[11]); } - asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n", + asm_fprintf (file, "\tlwz %s,0(%s)\n", reg_names[0], reg_names[11]); - asm_fprintf (file, "\t{cax|add} %s,%s,%s\n", + asm_fprintf (file, "\tadd %s,%s,%s\n", reg_names[0], reg_names[0], reg_names[11]); } else { - asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]); + asm_fprintf (file, "\tlis %s,", reg_names[12]); assemble_name (file, buf); fputs ("@ha\n", file); - asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", + asm_fprintf (file, "\tstw %s,4(%s)\n", reg_names[0], reg_names[1]); - asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]); + asm_fprintf (file, "\tla %s,", reg_names[0]); assemble_name (file, buf); asm_fprintf (file, "@l(%s)\n", reg_names[12]); } diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 2edf007..abafbf9 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -348,10 +348,6 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); #define PROCESSOR_DEFAULT PROCESSOR_PPC603 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A -/* Specify the dialect of assembler to use. New mnemonics is dialect one - and the old mnemonics are dialect zero. */ -#define ASSEMBLER_DIALECT (TARGET_NEW_MNEMONICS ? 1 : 0) - /* Debug support */ #define MASK_DEBUG_STACK 0x01 /* debug stack applications */ #define MASK_DEBUG_ARG 0x02 /* debug argument handling */ diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 19e3a76..d5ffd81 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -288,7 +288,7 @@ (define_mode_attr tptrsize [(SI "TARGET_32BIT") (define_mode_attr mptrsize [(SI "si") (DI "di")]) -(define_mode_attr ptrload [(SI "{l|lwz}") +(define_mode_attr ptrload [(SI "lwz") (DI "ld")]) (define_mode_attr rreg [(SF "f") @@ -597,7 +597,7 @@ (define_insn "" "" "@ lbz%U1%X1 %0,%1 - {rlinm|rlwinm} %0,%1,0,0xff" + rlwinm %0,%1,0,0xff" [(set_attr "type" "load,*")]) (define_insn "" @@ -607,7 +607,7 @@ (define_insn "" (clobber (match_scratch:SI 2 "=r,r"))] "" "@ - {andil.|andi.} %2,%1,0xff + andi. %2,%1,0xff #" [(set_attr "type" "fast_compare,compare") (set_attr "length" "4,8")]) @@ -633,7 +633,7 @@ (define_insn "" (zero_extend:SI (match_dup 1)))] "" "@ - {andil.|andi.} %0,%1,0xff + andi. %0,%1,0xff #" [(set_attr "type" "fast_compare,compare") (set_attr "length" "4,8")]) @@ -717,7 +717,7 @@ (define_insn "" "" "@ lbz%U1%X1 %0,%1 - {rlinm|rlwinm} %0,%1,0,0xff" + rlwinm %0,%1,0,0xff" [(set_attr "type" "load,*")]) (define_insn "" @@ -727,7 +727,7 @@ (define_insn "" (clobber (match_scratch:HI 2 "=r,r"))] "" "@ - {andil.|andi.} %2,%1,0xff + andi. %2,%1,0xff #" [(set_attr "type" "fast_compare,compare") (set_attr "length" "4,8")]) @@ -753,7 +753,7 @@ (define_insn "" (zero_extend:HI (match_dup 1)))] "" "@ - {andil.|andi.} %0,%1,0xff + andi. %0,%1,0xff #" [(set_attr "type" "fast_compare,compare") (set_attr "length" "4,8")]) @@ -843,7 +843,7 @@ (define_insn "" "" "@ lhz%U1%X1 %0,%1 - {rlinm|rlwinm} %0,%1,0,0xffff" + rlwinm %0,%1,0,0xffff" [(set_attr "type" "load,*")]) (define_insn "" @@ -853,7 +853,7 @@ (define_insn "" (clobber (match_scratch:SI 2 "=r,r"))] "" "@ - {andil.|andi.} %2,%1,0xffff + andi. %2,%1,0xffff #" [(set_attr "type" "fast_compare,compare") (set_attr "length" "4,8")]) @@ -879,7 +879,7 @@ (define_insn "" (zero_extend:SI (match_dup 1)))] "" "@ - {andil.|andi.} %0,%1,0xffff + andi. %0,%1,0xffff #" [(set_attr "type" "fast_compare,compare") (set_attr "length" "4,8")]) @@ -910,14 +910,14 @@ (define_insn "" "rs6000_gen_cell_microcode" "@ lha%U1%X1 %0,%1 - {exts|extsh} %0,%1" + extsh %0,%1" [(set_attr "type" "load_ext,exts")]) (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")))] "!rs6000_gen_cell_microcode" - "{exts|extsh} %0,%1" + "extsh %0,%1" [(set_attr "type" "exts")]) (define_insn "" @@ -927,7 +927,7 @@ (define_insn "" (clobber (match_scratch:SI 2 "=r,r"))] "" "@ - {exts.|extsh.} %2,%1 + extsh. %2,%1 #" [(set_attr "type" "compare") (set_attr "length" "4,8")]) @@ -953,7 +953,7 @@ (define_insn "" (sign_extend:SI (match_dup 1)))] "" "@ - {exts.|extsh.} %0,%1 + extsh. %0,%1 #" [(set_attr "type" "compare") (set_attr "length" "4,8")]) @@ -1547,10 +1547,10 @@ (define_insn "*add<mode>3_internal1" (match_operand:GPR 2 "add_operand" "r,I,I,L")))] "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))" "@ - {cax|add} %0,%1,%2 - {cal %0,%2(%1)|addi %0,%1,%2} - {ai|addic} %0,%1,%2 - {cau|addis} %0,%1,%v2" + add %0,%1,%2 + addi %0,%1,%2 + addic %0,%1,%2 + addis %0,%1,%v2" [(set_attr "length" "4,4,4,4")]) (define_insn "addsi3_high" @@ -1558,7 +1558,7 @@ (define_insn "addsi3_high" (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") (high:SI (match_operand 2 "" ""))))] "TARGET_MACHO && !TARGET_64BIT" - "{cau|addis} %0,%1,ha16(%2)" + "addis %0,%1,ha16(%2)" [(set_attr "length" "4")]) (define_insn "*add<mode>3_internal2" @@ -1569,8 +1569,8 @@ (define_insn "*add<mode>3_internal2" (clobber (match_scratch:P 3 "=r,r,r,r"))] "" "@ - {cax.|add.} %3,%1,%2 - {ai.|addic.} %3,%1,%2 + add. %3,%1,%2 + addic. %3,%1,%2 # #" [(set_attr "type" "fast_compare,compare,compare,compare") @@ -1601,8 +1601,8 @@ (define_insn "*add<mode>3_internal3" (match_dup 2)))] "" "@ - {cax.|add.} %0,%1,%2 - {ai.|addic.} %0,%1,%2 + add. %0,%1,%2 + addic. %0,%1,%2 # #" [(set_attr "type" "fast_compare,compare,compare,compare") @@ -2012,7 +2012,7 @@ (define_insn "clz<mode>2" [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))] "" - "{cntlz|cntlz<wd>} %0,%1" + "cntlz<wd> %0,%1" [(set_attr "type" "cntlz")]) (define_expand "ctz<mode>2" @@ -2181,8 +2181,8 @@ (define_insn "*bswapsi2_internal" (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))] "" "@ - {lbrx|lwbrx} %0,%y1 - {stbrx|stwbrx} %1,%y0 + lwbrx %0,%y1 + stwbrx %1,%y0 #" [(set_attr "length" "4,4,12") (set_attr "type" "load,store,*")]) @@ -2548,8 +2548,8 @@ (define_insn "mulsi3" (match_operand:SI 2 "reg_or_short_operand" "r,I")))] "" "@ - {muls|mullw} %0,%1,%2 - {muli|mulli} %0,%1,%2" + mullw %0,%1,%2 + mulli %0,%1,%2" [(set (attr "type") (cond [(match_operand:SI 2 "s8bit_cint_operand" "") (const_string "imul3") @@ -2565,7 +2565,7 @@ (define_insn "*mulsi3_internal1" (clobber (match_scratch:SI 3 "=r,r"))] "" "@ - {muls.|mullw.} %3,%1,%2 + mullw. %3,%1,%2 #" [(set_attr "type" "imul_compare") (set_attr "length" "4,8")]) @@ -2593,7 +2593,7 @@ (define_insn "*mulsi3_internal2" (mult:SI (match_dup 1) (match_dup 2)))] "" "@ - {muls.|mullw.} %0,%1,%2 + mullw. %0,%1,%2 #" [(set_attr "type" "imul_compare") (set_attr "length" "4,8")]) @@ -2682,7 +2682,7 @@ (define_insn "" (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") (match_operand:GPR 2 "exact_log2_cint_operand" "N")))] "" - "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0" + "sra<wd>i %0,%1,%p2\;addze %0,%0" [(set_attr "type" "two") (set_attr "length" "8")]) @@ -2694,7 +2694,7 @@ (define_insn "" (clobber (match_scratch:P 3 "=r,r"))] "" "@ - {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3 + sra<wd>i %3,%1,%p2\;addze. %3,%3 #" [(set_attr "type" "compare") (set_attr "length" "8,12") @@ -2724,7 +2724,7 @@ (define_insn "" (div:P (match_dup 1) (match_dup 2)))] "" "@ - {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0 + sra<wd>i %0,%1,%p2\;addze. %0,%0 #" [(set_attr "type" "compare") (set_attr "length" "8,12") @@ -2769,9 +2769,9 @@ (define_insn "andsi3_mc" "rs6000_gen_cell_microcode" "@ and %0,%1,%2 - {rlinm|rlwinm} %0,%1,0,%m2,%M2 - {andil.|andi.} %0,%1,%b2 - {andiu.|andis.} %0,%1,%u2" + rlwinm %0,%1,0,%m2,%M2 + andi. %0,%1,%b2 + andis. %0,%1,%u2" [(set_attr "type" "*,*,fast_compare,fast_compare")]) (define_insn "andsi3_nomc" @@ -2782,7 +2782,7 @@ (define_insn "andsi3_nomc" "!rs6000_gen_cell_microcode" "@ and %0,%1,%2 - {rlinm|rlwinm} %0,%1,0,%m2,%M2") + rlwinm %0,%1,0,%m2,%M2") (define_insn "andsi3_internal0_nomc" [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") @@ -2791,7 +2791,7 @@ (define_insn "andsi3_internal0_nomc" "!rs6000_gen_cell_microcode" "@ and %0,%1,%2 - {rlinm|rlwinm} %0,%1,0,%m2,%M2") + rlwinm %0,%1,0,%m2,%M2") ;; Note to set cr's other than cr0 we do the and immediate and then @@ -2808,9 +2808,9 @@ (define_insn "*andsi3_internal2_mc" "TARGET_32BIT && rs6000_gen_cell_microcode" "@ and. %3,%1,%2 - {andil.|andi.} %3,%1,%b2 - {andiu.|andis.} %3,%1,%u2 - {rlinm.|rlwinm.} %3,%1,0,%m2,%M2 + andi. %3,%1,%b2 + andis. %3,%1,%u2 + rlwinm. %3,%1,0,%m2,%M2 # # # @@ -2829,9 +2829,9 @@ (define_insn "*andsi3_internal3_mc" "TARGET_64BIT && rs6000_gen_cell_microcode" "@ # - {andil.|andi.} %3,%1,%b2 - {andiu.|andis.} %3,%1,%u2 - {rlinm.|rlwinm.} %3,%1,0,%m2,%M2 + andi. %3,%1,%b2 + andis. %3,%1,%u2 + rlwinm. %3,%1,0,%m2,%M2 # # # @@ -2889,9 +2889,9 @@ (define_insn "*andsi3_internal4" "TARGET_32BIT && rs6000_gen_cell_microcode" "@ and. %0,%1,%2 - {andil.|andi.} %0,%1,%b2 - {andiu.|andis.} %0,%1,%u2 - {rlinm.|rlwinm.} %0,%1,0,%m2,%M2 + andi. %0,%1,%b2 + andis. %0,%1,%u2 + rlwinm. %0,%1,0,%m2,%M2 # # # @@ -2912,9 +2912,9 @@ (define_insn "*andsi3_internal5_mc" "TARGET_64BIT && rs6000_gen_cell_microcode" "@ # - {andil.|andi.} %0,%1,%b2 - {andiu.|andis.} %0,%1,%u2 - {rlinm.|rlwinm.} %0,%1,0,%m2,%M2 + andi. %0,%1,%b2 + andis. %0,%1,%u2 + rlwinm. %0,%1,0,%m2,%M2 # # # @@ -3037,8 +3037,8 @@ (define_insn "*boolsi3_internal1" "" "@ %q3 %0,%1,%2 - {%q3il|%q3i} %0,%1,%b2 - {%q3iu|%q3is} %0,%1,%u2") + %q3i %0,%1,%b2 + %q3is %0,%1,%u2") (define_insn "*boolsi3_internal2" [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") @@ -3292,7 +3292,7 @@ (define_insn "insvsi" operands[4] = GEN_INT (32 - start - size); operands[1] = GEN_INT (start + size - 1); - return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; + return \"rlwimi %0,%3,%h4,%h2,%h1\"; }" [(set_attr "type" "insert_word")]) @@ -3311,7 +3311,7 @@ (define_insn "*insvsi_internal1" operands[4] = GEN_INT (shift - start - size); operands[1] = GEN_INT (start + size - 1); - return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; + return \"rlwimi %0,%3,%h4,%h2,%h1\"; }" [(set_attr "type" "insert_word")]) @@ -3330,7 +3330,7 @@ (define_insn "*insvsi_internal2" operands[4] = GEN_INT (32 - shift - start - size); operands[1] = GEN_INT (start + size - 1); - return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; + return \"rlwimi %0,%3,%h4,%h2,%h1\"; }" [(set_attr "type" "insert_word")]) @@ -3349,7 +3349,7 @@ (define_insn "*insvsi_internal3" operands[4] = GEN_INT (32 - shift - start - size); operands[1] = GEN_INT (start + size - 1); - return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; + return \"rlwimi %0,%3,%h4,%h2,%h1\"; }" [(set_attr "type" "insert_word")]) @@ -3371,7 +3371,7 @@ (define_insn "*insvsi_internal4" /* Align extract field with insert field */ operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size); operands[1] = GEN_INT (insert_start + insert_size - 1); - return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\"; + return \"rlwimi %0,%3,%h5,%h2,%h1\"; }" [(set_attr "type" "insert_word")]) @@ -3391,7 +3391,7 @@ (define_insn "*insvsi_internal5" operands[4] = GEN_INT(32 - INTVAL(operands[2])); operands[2] = GEN_INT(mb); operands[1] = GEN_INT(me); - return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; + return \"rlwimi %0,%3,%h4,%h2,%h1\"; }" [(set_attr "type" "insert_word")]) @@ -3410,7 +3410,7 @@ (define_insn "*insvsi_internal6" operands[4] = GEN_INT(32 - INTVAL(operands[2])); operands[2] = GEN_INT(mb); operands[1] = GEN_INT(me); - return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; + return \"rlwimi %0,%3,%h4,%h2,%h1\"; }" [(set_attr "type" "insert_word")]) @@ -3507,7 +3507,7 @@ (define_insn "extzvsi" operands[3] = const0_rtx; else operands[3] = GEN_INT (start + size); - return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\"; + return \"rlwinm %0,%1,%3,%s2,31\"; }") (define_insn "*extzvsi_internal1" @@ -3538,16 +3538,16 @@ (define_insn "*extzvsi_internal1" operands[3] = GEN_INT (((1 << (16 - (start & 15))) - (1 << (16 - (start & 15) - size)))); if (start < 16) - return \"{andiu.|andis.} %4,%1,%3\"; + return \"andis. %4,%1,%3\"; else - return \"{andil.|andi.} %4,%1,%3\"; + return \"andi. %4,%1,%3\"; } if (start + size >= 32) operands[3] = const0_rtx; else operands[3] = GEN_INT (start + size); - return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\"; + return \"rlwinm. %4,%1,%3,%s2,31\"; }" [(set_attr "type" "delayed_compare") (set_attr "length" "4,8")]) @@ -3591,14 +3591,14 @@ (define_insn "*extzvsi_internal2" if (start >= 16 && start + size == 32) { operands[3] = GEN_INT ((1 << size) - 1); - return \"{andil.|andi.} %0,%1,%3\"; + return \"andi. %0,%1,%3\"; } if (start + size >= 32) operands[3] = const0_rtx; else operands[3] = GEN_INT (start + size); - return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\"; + return \"rlwinm. %0,%1,%3,%s2,31\"; }" [(set_attr "type" "delayed_compare") (set_attr "length" "4,8")]) @@ -3689,8 +3689,8 @@ (define_insn "rotlsi3" (match_operand:SI 2 "reg_or_cint_operand" "r,i")))] "" "@ - {rlnm|rlwnm} %0,%1,%2,0xffffffff - {rlinm|rlwinm} %0,%1,%h2,0xffffffff" + rlwnm %0,%1,%2,0xffffffff + rlwinm %0,%1,%h2,0xffffffff" [(set_attr "type" "var_shift_rotate,integer")]) (define_insn "*rotlsi3_64" @@ -3700,8 +3700,8 @@ (define_insn "*rotlsi3_64" (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))] "TARGET_64BIT" "@ - {rlnm|rlwnm} %0,%1,%2,0xffffffff - {rlinm|rlwinm} %0,%1,%h2,0xffffffff" + rlwnm %0,%1,%2,0xffffffff + rlwinm %0,%1,%h2,0xffffffff" [(set_attr "type" "var_shift_rotate,integer")]) (define_insn "*rotlsi3_internal2" @@ -3712,8 +3712,8 @@ (define_insn "*rotlsi3_internal2" (clobber (match_scratch:SI 3 "=r,r,r,r"))] "" "@ - {rlnm.|rlwnm.} %3,%1,%2,0xffffffff - {rlinm.|rlwinm.} %3,%1,%h2,0xffffffff + rlwnm. %3,%1,%2,0xffffffff + rlwinm. %3,%1,%h2,0xffffffff # #" [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") @@ -3742,8 +3742,8 @@ (define_insn "*rotlsi3_internal3" (rotate:SI (match_dup 1) (match_dup 2)))] "" "@ - {rlnm.|rlwnm.} %0,%1,%2,0xffffffff - {rlinm.|rlwinm.} %0,%1,%h2,0xffffffff + rlwnm. %0,%1,%2,0xffffffff + rlwinm. %0,%1,%h2,0xffffffff # #" [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") @@ -3771,8 +3771,8 @@ (define_insn "*rotlsi3_internal4" (match_operand:SI 3 "mask_operand" "n,n")))] "" "@ - {rlnm|rlwnm} %0,%1,%2,%m3,%M3 - {rlinm|rlwinm} %0,%1,%h2,%m3,%M3" + rlwnm %0,%1,%2,%m3,%M3 + rlwinm %0,%1,%h2,%m3,%M3" [(set_attr "type" "var_shift_rotate,integer")]) (define_insn "*rotlsi3_internal5" @@ -3785,8 +3785,8 @@ (define_insn "*rotlsi3_internal5" (clobber (match_scratch:SI 4 "=r,r,r,r"))] "" "@ - {rlnm.|rlwnm.} %4,%1,%2,%m3,%M3 - {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3 + rlwnm. %4,%1,%2,%m3,%M3 + rlwinm. %4,%1,%h2,%m3,%M3 # #" [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") @@ -3821,8 +3821,8 @@ (define_insn "*rotlsi3_internal6" (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "" "@ - {rlnm.|rlwnm.} %0,%1,%2,%m3,%M3 - {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3 + rlwnm. %0,%1,%2,%m3,%M3 + rlwinm. %0,%1,%h2,%m3,%M3 # #" [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") @@ -3852,7 +3852,7 @@ (define_insn "*rotlsi3_internal7" (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] "" - "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff" + "rlw%I2nm %0,%1,%h2,0xff" [(set (attr "cell_micro") (if_then_else (match_operand:SI 2 "const_int_operand" "") (const_string "not") @@ -3868,8 +3868,8 @@ (define_insn "*rotlsi3_internal8" (clobber (match_scratch:SI 3 "=r,r,r,r"))] "" "@ - {rlnm.|rlwnm.} %3,%1,%2,0xff - {rlinm.|rlwinm.} %3,%1,%h2,0xff + rlwnm. %3,%1,%2,0xff + rlwinm. %3,%1,%h2,0xff # #" [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") @@ -3904,8 +3904,8 @@ (define_insn "*rotlsi3_internal9" (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] "" "@ - {rlnm.|rlwnm.} %0,%1,%2,0xff - {rlinm.|rlwinm.} %0,%1,%h2,0xff + rlwnm. %0,%1,%2,0xff + rlwinm. %0,%1,%h2,0xff # #" [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") @@ -3936,8 +3936,8 @@ (define_insn "*rotlsi3_internal10" (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))] "" "@ - {rlnm|rlwnm} %0,%1,%2,0xffff - {rlinm|rlwinm} %0,%1,%h2,0xffff" + rlwnm %0,%1,%2,0xffff + rlwinm %0,%1,%h2,0xffff" [(set_attr "type" "var_shift_rotate,integer")]) @@ -3951,8 +3951,8 @@ (define_insn "*rotlsi3_internal11" (clobber (match_scratch:SI 3 "=r,r,r,r"))] "" "@ - {rlnm.|rlwnm.} %3,%1,%2,0xffff - {rlinm.|rlwinm.} %3,%1,%h2,0xffff + rlwnm. %3,%1,%2,0xffff + rlwinm. %3,%1,%h2,0xffff # #" [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") @@ -3987,8 +3987,8 @@ (define_insn "*rotlsi3_internal12" (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] "" "@ - {rlnm.|rlwnm.} %0,%1,%2,0xffff - {rlinm.|rlwinm.} %0,%1,%h2,0xffff + rlwnm. %0,%1,%2,0xffff + rlwinm. %0,%1,%h2,0xffff # #" [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") @@ -4017,8 +4017,8 @@ (define_insn "ashlsi3" (match_operand:SI 2 "reg_or_cint_operand" "r,i")))] "" "@ - {sl|slw} %0,%1,%2 - {sli|slwi} %0,%1,%h2" + slw %0,%1,%2 + slwi %0,%1,%h2" [(set_attr "type" "var_shift_rotate,shift")]) (define_insn "*ashlsi3_64" @@ -4028,8 +4028,8 @@ (define_insn "*ashlsi3_64" (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))] "TARGET_POWERPC64" "@ - {sl|slw} %0,%1,%2 - {sli|slwi} %0,%1,%h2" + slw %0,%1,%2 + slwi %0,%1,%h2" [(set_attr "type" "var_shift_rotate,shift")]) (define_insn "" @@ -4040,8 +4040,8 @@ (define_insn "" (clobber (match_scratch:SI 3 "=r,r,r,r"))] "TARGET_32BIT" "@ - {sl.|slw.} %3,%1,%2 - {sli.|slwi.} %3,%1,%h2 + slw. %3,%1,%2 + slwi. %3,%1,%h2 # #" [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") @@ -4070,8 +4070,8 @@ (define_insn "" (ashift:SI (match_dup 1) (match_dup 2)))] "TARGET_32BIT" "@ - {sl.|slw.} %0,%1,%2 - {sli.|slwi.} %0,%1,%h2 + slw. %0,%1,%2 + slwi. %0,%1,%h2 # #" [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") @@ -4098,7 +4098,7 @@ (define_insn "rlwinm" (match_operand:SI 2 "const_int_operand" "i")) (match_operand:SI 3 "mask_operand" "n")))] "includes_lshift_p (operands[2], operands[3])" - "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3") + "rlwinm %0,%1,%h2,%m3,%M3") (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") @@ -4110,7 +4110,7 @@ (define_insn "" (clobber (match_scratch:SI 4 "=r,r"))] "includes_lshift_p (operands[2], operands[3])" "@ - {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3 + rlwinm. %4,%1,%h2,%m3,%M3 #" [(set_attr "type" "delayed_compare") (set_attr "length" "4,8")]) @@ -4143,7 +4143,7 @@ (define_insn "" (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "includes_lshift_p (operands[2], operands[3])" "@ - {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3 + rlwinm. %0,%1,%h2,%m3,%M3 #" [(set_attr "type" "delayed_compare") (set_attr "length" "4,8")]) @@ -4172,8 +4172,8 @@ (define_insn "lshrsi3" "" "@ mr %0,%1 - {sr|srw} %0,%1,%2 - {sri|srwi} %0,%1,%h2" + srw %0,%1,%2 + srwi %0,%1,%h2" [(set_attr "type" "integer,var_shift_rotate,shift")]) (define_insn "*lshrsi3_64" @@ -4183,8 +4183,8 @@ (define_insn "*lshrsi3_64" (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))] "TARGET_POWERPC64" "@ - {sr|srw} %0,%1,%2 - {sri|srwi} %0,%1,%h2" + srw %0,%1,%2 + srwi %0,%1,%h2" [(set_attr "type" "var_shift_rotate,shift")]) (define_insn "" @@ -4196,8 +4196,8 @@ (define_insn "" "TARGET_32BIT" "@ mr. %1,%1 - {sr.|srw.} %3,%1,%2 - {sri.|srwi.} %3,%1,%h2 + srw. %3,%1,%2 + srwi. %3,%1,%h2 # # #" @@ -4228,8 +4228,8 @@ (define_insn "" "TARGET_32BIT" "@ mr. %0,%1 - {sr.|srw.} %0,%1,%2 - {sri.|srwi.} %0,%1,%h2 + srw. %0,%1,%2 + srwi. %0,%1,%h2 # # #" @@ -4257,7 +4257,7 @@ (define_insn "" (match_operand:SI 2 "const_int_operand" "i")) (match_operand:SI 3 "mask_operand" "n")))] "includes_rshift_p (operands[2], operands[3])" - "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3") + "rlwinm %0,%1,%s2,%m3,%M3") (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") @@ -4269,7 +4269,7 @@ (define_insn "" (clobber (match_scratch:SI 4 "=r,r"))] "includes_rshift_p (operands[2], operands[3])" "@ - {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3 + rlwinm. %4,%1,%s2,%m3,%M3 #" [(set_attr "type" "delayed_compare") (set_attr "length" "4,8")]) @@ -4302,7 +4302,7 @@ (define_insn "" (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "includes_rshift_p (operands[2], operands[3])" "@ - {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3 + rlwinm. %0,%1,%s2,%m3,%M3 #" [(set_attr "type" "delayed_compare") (set_attr "length" "4,8")]) @@ -4331,7 +4331,7 @@ (define_insn "" (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "i")) 0)))] "includes_rshift_p (operands[2], GEN_INT (255))" - "{rlinm|rlwinm} %0,%1,%s2,0xff") + "rlwinm %0,%1,%s2,0xff") (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") @@ -4344,7 +4344,7 @@ (define_insn "" (clobber (match_scratch:SI 3 "=r,r"))] "includes_rshift_p (operands[2], GEN_INT (255))" "@ - {rlinm.|rlwinm.} %3,%1,%s2,0xff + rlwinm. %3,%1,%s2,0xff #" [(set_attr "type" "delayed_compare") (set_attr "length" "4,8")]) @@ -4380,7 +4380,7 @@ (define_insn "" (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] "includes_rshift_p (operands[2], GEN_INT (255))" "@ - {rlinm.|rlwinm.} %0,%1,%s2,0xff + rlwinm. %0,%1,%s2,0xff #" [(set_attr "type" "delayed_compare") (set_attr "length" "4,8")]) @@ -4410,7 +4410,7 @@ (define_insn "" (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "i")) 0)))] "includes_rshift_p (operands[2], GEN_INT (65535))" - "{rlinm|rlwinm} %0,%1,%s2,0xffff") + "rlwinm %0,%1,%s2,0xffff") (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") @@ -4423,7 +4423,7 @@ (define_insn "" (clobber (match_scratch:SI 3 "=r,r"))] "includes_rshift_p (operands[2], GEN_INT (65535))" "@ - {rlinm.|rlwinm.} %3,%1,%s2,0xffff + rlwinm. %3,%1,%s2,0xffff #" [(set_attr "type" "delayed_compare") (set_attr "length" "4,8")]) @@ -4459,7 +4459,7 @@ (define_insn "" (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] "includes_rshift_p (operands[2], GEN_INT (65535))" "@ - {rlinm.|rlwinm.} %0,%1,%s2,0xffff + rlwinm. %0,%1,%s2,0xffff #" [(set_attr "type" "delayed_compare") (set_attr "length" "4,8")]) @@ -4488,8 +4488,8 @@ (define_insn "ashrsi3" (match_operand:SI 2 "reg_or_cint_operand" "r,i")))] "" "@ - {sra|sraw} %0,%1,%2 - {srai|srawi} %0,%1,%h2" + sraw %0,%1,%2 + srawi %0,%1,%h2" [(set_attr "type" "var_shift_rotate,shift")]) (define_insn "*ashrsi3_64" @@ -4499,8 +4499,8 @@ (define_insn "*ashrsi3_64" (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))] "TARGET_POWERPC64" "@ - {sra|sraw} %0,%1,%2 - {srai|srawi} %0,%1,%h2" + sraw %0,%1,%2 + srawi %0,%1,%h2" [(set_attr "type" "var_shift_rotate,shift")]) (define_insn "" @@ -4511,8 +4511,8 @@ (define_insn "" (clobber (match_scratch:SI 3 "=r,r,r,r"))] "" "@ - {sra.|sraw.} %3,%1,%2 - {srai.|srawi.} %3,%1,%h2 + sraw. %3,%1,%2 + srawi. %3,%1,%h2 # #" [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") @@ -4541,8 +4541,8 @@ (define_insn "" (ashiftrt:SI (match_dup 1) (match_dup 2)))] "" "@ - {sra.|sraw.} %0,%1,%2 - {srai.|srawi.} %0,%1,%h2 + sraw. %0,%1,%2 + srawi. %0,%1,%h2 # #" [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") @@ -5065,7 +5065,7 @@ (define_insn "*adddf3_fpr" (match_operand:DF 2 "gpc_reg_operand" "d")))] "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && !VECTOR_UNIT_VSX_P (DFmode)" - "{fa|fadd} %0,%1,%2" + "fadd %0,%1,%2" [(set_attr "type" "fp") (set_attr "fp_type" "fp_addsub_d")]) @@ -5082,7 +5082,7 @@ (define_insn "*subdf3_fpr" (match_operand:DF 2 "gpc_reg_operand" "d")))] "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && !VECTOR_UNIT_VSX_P (DFmode)" - "{fs|fsub} %0,%1,%2" + "fsub %0,%1,%2" [(set_attr "type" "fp") (set_attr "fp_type" "fp_addsub_d")]) @@ -5099,7 +5099,7 @@ (define_insn "*muldf3_fpr" (match_operand:DF 2 "gpc_reg_operand" "d")))] "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && !VECTOR_UNIT_VSX_P (DFmode)" - "{fm|fmul} %0,%1,%2" + "fmul %0,%1,%2" [(set_attr "type" "dmul") (set_attr "fp_type" "fp_mul_d")]) @@ -5118,7 +5118,7 @@ (define_insn "*divdf3_fpr" (match_operand:DF 2 "gpc_reg_operand" "d")))] "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && !TARGET_SIMPLE_FPU && !VECTOR_UNIT_VSX_P (DFmode)" - "{fd|fdiv} %0,%1,%2" + "fdiv %0,%1,%2" [(set_attr "type" "ddiv")]) (define_insn "*fred_fpr" @@ -5144,7 +5144,7 @@ (define_insn "*fmadf4_fpr" (match_operand:DF 3 "gpc_reg_operand" "f")))] "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && VECTOR_UNIT_NONE_P (DFmode)" - "{fma|fmadd} %0,%1,%2,%3" + "fmadd %0,%1,%2,%3" [(set_attr "type" "fp") (set_attr "fp_type" "fp_maddsub_d")]) @@ -5155,7 +5155,7 @@ (define_insn "*fmsdf4_fpr" (neg:DF (match_operand:DF 3 "gpc_reg_operand" "f"))))] "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && VECTOR_UNIT_NONE_P (DFmode)" - "{fms|fmsub} %0,%1,%2,%3" + "fmsub %0,%1,%2,%3" [(set_attr "type" "fp") (set_attr "fp_type" "fp_maddsub_d")]) @@ -5166,7 +5166,7 @@ (define_insn "*nfmadf4_fpr" (match_operand:DF 3 "gpc_reg_operand" "f"))))] "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && VECTOR_UNIT_NONE_P (DFmode)" - "{fnma|fnmadd} %0,%1,%2,%3" + "fnmadd %0,%1,%2,%3" [(set_attr "type" "fp") (set_attr "fp_type" "fp_maddsub_d")]) @@ -5177,7 +5177,7 @@ (define_insn "*nfmsdf4_fpr" (neg:DF (match_operand:DF 3 "gpc_reg_operand" "f")))))] "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && VECTOR_UNIT_NONE_P (DFmode)" - "{fnms|fnmsub} %0,%1,%2,%3" + "fnmsub %0,%1,%2,%3" [(set_attr "type" "fp") (set_attr "fp_type" "fp_maddsub_d")]) @@ -5794,7 +5794,7 @@ (define_insn "fctiwz_<mode>" (unspec:DI [(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))] UNSPEC_FCTIWZ))] "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" - "{fcirz|fctiwz} %0,%1" + "fctiwz %0,%1" [(set_attr "type" "fp")]) (define_insn "fctiwuz_<mode>" @@ -6211,12 +6211,12 @@ (define_insn "*adddi3_noppc64" { if (WORDS_BIG_ENDIAN) return (GET_CODE (operands[2])) != CONST_INT - ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\" - : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\"; + ? \"addc %L0,%L1,%L2\;adde %0,%1,%2\" + : \"addic %L0,%L1,%2\;add%G2e %0,%1\"; else return (GET_CODE (operands[2])) != CONST_INT - ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\" - : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\"; + ? \"addc %0,%1,%2\;adde %L0,%L1,%L2\" + : \"addic %0,%1,%2\;add%G2e %L0,%L1\"; }" [(set_attr "type" "two") (set_attr "length" "8")]) @@ -6230,12 +6230,12 @@ (define_insn "*subdi3_noppc64" { if (WORDS_BIG_ENDIAN) return (GET_CODE (operands[1]) != CONST_INT) - ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\" - : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\"; + ? \"subfc %L0,%L2,%L1\;subfe %0,%2,%1\" + : \"subfic %L0,%L2,%1\;subf%G1e %0,%2\"; else return (GET_CODE (operands[1]) != CONST_INT) - ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\" - : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\"; + ? \"subfc %0,%2,%1\;subfe %L0,%L2,%L1\" + : \"subfic %0,%2,%1\;subf%G1e %L0,%L2\"; }" [(set_attr "type" "two") (set_attr "length" "8")]) @@ -6247,8 +6247,8 @@ (define_insn "*negdi2_noppc64" "* { return (WORDS_BIG_ENDIAN) - ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\" - : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\"; + ? \"subfic %L0,%L1,0\;subfze %0,%1\" + : \"subfic %0,%1,0\;subfze %L0,%L1\"; }" [(set_attr "type" "two") (set_attr "length" "8")]) @@ -6352,8 +6352,8 @@ (define_insn "ashrdi3_no_power" (match_operand:SI 2 "const_int_operand" "M,i")))] "TARGET_32BIT && !TARGET_POWERPC64 && WORDS_BIG_ENDIAN" "@ - {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2 - {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2" + srawi %0,%1,31\;srawi %L0,%1,%h2 + srwi %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;srawi %0,%1,%h2" [(set_attr "type" "two,three") (set_attr "length" "8,12")]) @@ -7869,7 +7869,7 @@ (define_insn "*movsi_got_internal" (match_operand:SI 2 "gpc_reg_operand" "b")] UNSPEC_MOVSI_GOT))] "DEFAULT_ABI == ABI_V4 && flag_pic == 1" - "{l|lwz} %0,%a1@got(%2)" + "lwz %0,%a1@got(%2)" [(set_attr "type" "load")]) ;; Used by sched, shorten_branches and final when the GOT pseudo reg @@ -7896,7 +7896,7 @@ (define_insn "movsi_low" (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") (match_operand 2 "" ""))))] "TARGET_MACHO && ! TARGET_64BIT" - "{l|lwz} %0,lo16(%2)(%1)" + "lwz %0,lo16(%2)(%1)" [(set_attr "type" "load") (set_attr "length" "4")]) @@ -7907,16 +7907,16 @@ (define_insn "*movsi_internal1" (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))" "@ mr %0,%1 - {cal|la} %0,%a1 - {l%U1%X1|lwz%U1%X1} %0,%1 - {st%U0%X0|stw%U0%X0} %1,%0 - {lil|li} %0,%1 - {liu|lis} %0,%v1 + la %0,%a1 + lwz%U1%X1 %0,%1 + stw%U0%X0 %1,%0 + li %0,%1 + lis %0,%v1 # mf%1 %0 mt%0 %1 mt%0 %1 - {cror 0,0,0|nop}" + nop" [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*") (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4")]) @@ -7927,16 +7927,16 @@ (define_insn "*movsi_internal1_single" (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))" "@ mr %0,%1 - {cal|la} %0,%a1 - {l%U1%X1|lwz%U1%X1} %0,%1 - {st%U0%X0|stw%U0%X0} %1,%0 - {lil|li} %0,%1 - {liu|lis} %0,%v1 + la %0,%a1 + lwz%U1%X1 %0,%1 + stw%U0%X0 %1,%0 + li %0,%1 + lis %0,%v1 # mf%1 %0 mt%0 %1 mt%0 %1 - {cror 0,0,0|nop} + nop stfs%U0%X0 %1, %0 lfs%U1%X1 %0, %1" [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*,*,*") @@ -7971,7 +7971,7 @@ (define_insn "*mov<mode>_internal2" (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))] "" "@ - {cmpi|cmp<wd>i} %2,%0,0 + cmp<wd>i %2,%0,0 mr. %0,%1 #" [(set_attr "type" "cmp,compare,cmp") @@ -7998,10 +7998,10 @@ (define_insn "*movhi_internal" mr %0,%1 lhz%U1%X1 %0,%1 sth%U0%X0 %1,%0 - {lil|li} %0,%w1 + li %0,%w1 mf%1 %0 mt%0 %1 - {cror 0,0,0|nop}" + nop" [(set_attr "type" "*,load,store,*,mfjmpr,mtjmpr,*")]) (define_expand "mov<mode>" @@ -8019,10 +8019,10 @@ (define_insn "*movqi_internal" mr %0,%1 lbz%U1%X1 %0,%1 stb%U0%X0 %1,%0 - {lil|li} %0,%1 + li %0,%1 mf%1 %0 mt%0 %1 - {cror 0,0,0|nop}" + nop" [(set_attr "type" "*,load,store,*,mfjmpr,mtjmpr,*")]) ;; Here is how to move condition codes around. When we store CC data in @@ -8042,16 +8042,16 @@ (define_insn "*movcc_internal1" "@ mcrf %0,%1 mtcrf 128,%1 - {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff + rlwinm %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;rlwinm %1,%1,%f0,0xffffffff crxor %0,%0,%0 mfcr %0%Q1 - mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000 + mfcr %0%Q1\;rlwinm %0,%0,%f1,0xf0000000 mr %0,%1 - {lil|li} %0,%1 + li %0,%1 mf%1 %0 mt%0 %1 - {l%U1%X1|lwz%U1%X1} %0,%1 - {st%U0%U1|stw%U0%U1} %1,%0" + lwz%U1%X1 %0,%1 + stw%U0%U1 %1,%0" [(set (attr "type") (cond [(eq_attr "alternative" "0,3") (const_string "cr_logical") @@ -8117,14 +8117,14 @@ (define_insn "*movsf_hardfloat" && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)" "@ mr %0,%1 - {l%U1%X1|lwz%U1%X1} %0,%1 - {st%U0%X0|stw%U0%X0} %1,%0 + lwz%U1%X1 %0,%1 + stw%U0%X0 %1,%0 fmr %0,%1 lfs%U1%X1 %0,%1 stfs%U0%X0 %1,%0 mt%0 %1 mf%1 %0 - {cror 0,0,0|nop} + nop # #" [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*") @@ -8140,13 +8140,13 @@ (define_insn "*movsf_softfloat" mr %0,%1 mt%0 %1 mf%1 %0 - {l%U1%X1|lwz%U1%X1} %0,%1 - {st%U0%X0|stw%U0%X0} %1,%0 - {lil|li} %0,%1 - {liu|lis} %0,%v1 + lwz%U1%X1 %0,%1 + stw%U0%X0 %1,%0 + li %0,%1 + lis %0,%v1 # # - {cror 0,0,0|nop}" + nop" [(set_attr "type" "*,mtjmpr,mfjmpr,load,store,*,*,*,*,*") (set_attr "length" "4,4,4,4,4,4,4,4,8,4")]) @@ -8344,7 +8344,7 @@ (define_insn "*movdf_hardfloat64_mfpgpr" xxlxor %x0,%x0,%x0 mt%0 %1 mf%1 %0 - {cror 0,0,0|nop} + nop # # # @@ -8378,7 +8378,7 @@ (define_insn "*movdf_hardfloat64" xxlxor %x0,%x0,%x0 mt%0 %1 mf%1 %0 - {cror 0,0,0|nop} + nop # # #" @@ -8400,7 +8400,7 @@ (define_insn "*movdf_softfloat64" # # # - {cror 0,0,0|nop}" + nop" [(set_attr "type" "store,load,*,mtjmpr,mfjmpr,*,*,*,*") (set_attr "length" "4,4,4,4,4,8,12,16,4")]) @@ -8789,7 +8789,7 @@ (define_insn "*movdi_mfpgpr" fmr %0,%1 mf%1 %0 mt%0 %1 - {cror 0,0,0|nop} + nop mftgpr %0,%1 mffgpr %0,%1" [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,fp,mfjmpr,mtjmpr,*,mftgpr,mffgpr") @@ -8813,7 +8813,7 @@ (define_insn "*movdi_internal64" fmr %0,%1 mf%1 %0 mt%0 %1 - {cror 0,0,0|nop} + nop xxlxor %x0,%x0,%x0" [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,fp,mfjmpr,mtjmpr,*,vecsimple") (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")]) @@ -8895,7 +8895,7 @@ (define_insn "*movti_string" gcc_unreachable (); case 0: if (TARGET_STRING) - return \"{stsi|stswi} %1,%P0,16\"; + return \"stswi %1,%P0,16\"; case 1: return \"#\"; case 2: @@ -8903,7 +8903,7 @@ (define_insn "*movti_string" fall through to generating four loads. */ if (TARGET_STRING && ! reg_overlap_mentioned_p (operands[0], operands[1])) - return \"{lsi|lswi} %0,%P1,16\"; + return \"lswi %0,%P1,16\"; /* ... fall through ... */ case 3: case 4: @@ -9173,7 +9173,7 @@ (define_insn "*stmsi8" (set (mem:SI (plus:SI (match_dup 1) (const_int 28))) (match_operand:SI 10 "gpc_reg_operand" "r"))])] "TARGET_STRING && XVECLEN (operands[0], 0) == 9" - "{stsi|stswi} %2,%1,%O0" + "stswi %2,%1,%O0" [(set_attr "type" "store_ux") (set_attr "cell_micro" "always")]) @@ -9195,7 +9195,7 @@ (define_insn "*stmsi7" (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) (match_operand:SI 9 "gpc_reg_operand" "r"))])] "TARGET_STRING && XVECLEN (operands[0], 0) == 8" - "{stsi|stswi} %2,%1,%O0" + "stswi %2,%1,%O0" [(set_attr "type" "store_ux") (set_attr "cell_micro" "always")]) @@ -9215,7 +9215,7 @@ (define_insn "*stmsi6" (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) (match_operand:SI 8 "gpc_reg_operand" "r"))])] "TARGET_STRING && XVECLEN (operands[0], 0) == 7" - "{stsi|stswi} %2,%1,%O0" + "stswi %2,%1,%O0" [(set_attr "type" "store_ux") (set_attr "cell_micro" "always")]) @@ -9233,7 +9233,7 @@ (define_insn "*stmsi5" (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) (match_operand:SI 7 "gpc_reg_operand" "r"))])] "TARGET_STRING && XVECLEN (operands[0], 0) == 6" - "{stsi|stswi} %2,%1,%O0" + "stswi %2,%1,%O0" [(set_attr "type" "store_ux") (set_attr "cell_micro" "always")]) @@ -9249,7 +9249,7 @@ (define_insn "*stmsi4" (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) (match_operand:SI 6 "gpc_reg_operand" "r"))])] "TARGET_STRING && XVECLEN (operands[0], 0) == 5" - "{stsi|stswi} %2,%1,%O0" + "stswi %2,%1,%O0" [(set_attr "type" "store_ux") (set_attr "cell_micro" "always")]) @@ -9263,7 +9263,7 @@ (define_insn "*stmsi3" (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) (match_operand:SI 5 "gpc_reg_operand" "r"))])] "TARGET_STRING && XVECLEN (operands[0], 0) == 4" - "{stsi|stswi} %2,%1,%O0" + "stswi %2,%1,%O0" [(set_attr "type" "store_ux") (set_attr "cell_micro" "always")]) @@ -9345,7 +9345,7 @@ (define_insn "" && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) && REGNO (operands[4]) == 5" - "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" + "lswi %4,%1,%2\;stswi %4,%0,%2" [(set_attr "type" "store_ux") (set_attr "cell_micro" "always") (set_attr "length" "8")]) @@ -9385,7 +9385,7 @@ (define_insn "" && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) && REGNO (operands[4]) == 5" - "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" + "lswi %4,%1,%2\;stswi %4,%0,%2" [(set_attr "type" "store_ux") (set_attr "cell_micro" "always") (set_attr "length" "8")]) @@ -9421,7 +9421,7 @@ (define_insn "" && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) && REGNO (operands[4]) == 5" - "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" + "lswi %4,%1,%2\;stswi %4,%0,%2" [(set_attr "type" "store_ux") (set_attr "cell_micro" "always") (set_attr "length" "8")]) @@ -9446,7 +9446,7 @@ (define_insn "" (clobber (match_scratch:SI 5 "=X"))] "TARGET_STRING && ! TARGET_POWERPC64 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" - "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" + "lswi %4,%1,%2\;stswi %4,%0,%2" [(set_attr "type" "store_ux") (set_attr "cell_micro" "always") (set_attr "length" "8")]) @@ -9470,7 +9470,7 @@ (define_insn "" (clobber (match_scratch:SI 4 "=&r")) (clobber (match_scratch:SI 5 "=X"))] "TARGET_STRING && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" - "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" + "lswi %4,%1,%2\;stswi %4,%0,%2" [(set_attr "type" "store_ux") (set_attr "cell_micro" "always") (set_attr "length" "8")]) @@ -9538,8 +9538,8 @@ (define_insn "*movsi_update1" && (!avoiding_indexed_address_p (SImode) || !gpc_reg_operand (operands[2], SImode))" "@ - {lux|lwzux} %3,%0,%2 - {lu|lwzu} %3,%2(%0)" + lwzux %3,%0,%2 + lwzu %3,%2(%0)" [(set_attr "type" "load_ux,load_u")]) (define_insn "*movsi_update2" @@ -9566,8 +9566,8 @@ (define_insn "movsi_update" || (REG_P (operands[0]) && REGNO (operands[0]) == STACK_POINTER_REGNUM))" "@ - {stux|stwux} %3,%0,%2 - {stu|stwu} %3,%2(%0)" + stwux %3,%0,%2 + stwu %3,%2(%0)" [(set_attr "type" "store_ux,store_u")]) ;; This is an unconditional pattern; needed for stack allocation, even @@ -9580,8 +9580,8 @@ (define_insn "movsi_update_stack" (plus:SI (match_dup 1) (match_dup 2)))] "" "@ - {stux|stwux} %3,%0,%2 - {stu|stwu} %3,%2(%0)" + stwux %3,%0,%2 + stwu %3,%2(%0)" [(set_attr "type" "store_ux,store_u")]) (define_insn "*movhi_update1" @@ -9723,8 +9723,8 @@ (define_insn "*movsf_update3" && (!avoiding_indexed_address_p (SImode) || !gpc_reg_operand (operands[2], SImode))" "@ - {lux|lwzux} %3,%0,%2 - {lu|lwzu} %3,%2(%0)" + lwzux %3,%0,%2 + lwzu %3,%2(%0)" [(set_attr "type" "load_ux,load_u")]) (define_insn "*movsf_update4" @@ -9737,8 +9737,8 @@ (define_insn "*movsf_update4" && (!avoiding_indexed_address_p (SImode) || !gpc_reg_operand (operands[2], SImode))" "@ - {stux|stwux} %3,%0,%2 - {stu|stwu} %3,%2(%0)" + stwux %3,%0,%2 + stwu %3,%2(%0)" [(set_attr "type" "store_ux,store_u")]) (define_insn "*movdf_update1" @@ -10382,7 +10382,7 @@ (define_insn "load_toc_aix_si" ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1); operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); operands[2] = gen_rtx_REG (Pmode, 2); - return \"{l|lwz} %0,%1(%2)\"; + return \"lwz %0,%1(%2)\"; }" [(set_attr "type" "load")]) @@ -10497,7 +10497,7 @@ (define_insn "load_toc_v4_PIC_2" (minus:SI (match_operand:SI 2 "immediate_operand" "s") (match_operand:SI 3 "immediate_operand" "s")))))] "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" - "{l|lwz} %0,%2-%3(%1)" + "lwz %0,%2-%3(%1)" [(set_attr "type" "load")]) (define_insn "load_toc_v4_PIC_3b" @@ -10507,7 +10507,7 @@ (define_insn "load_toc_v4_PIC_3b" (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s") (match_operand:SI 3 "symbol_ref_operand" "s")))))] "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic" - "{cau|addis} %0,%1,%2-%3@ha") + "addis %0,%1,%2-%3@ha") (define_insn "load_toc_v4_PIC_3c" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -10515,7 +10515,7 @@ (define_insn "load_toc_v4_PIC_3c" (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s") (match_operand:SI 3 "symbol_ref_operand" "s"))))] "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic" - "{cal %0,%2-%3@l(%1)|addi %0,%1,%2-%3@l}") + "addi %0,%1,%2-%3@l") ;; If the TOC is shared over a translation unit, as happens with all ;; the kinds of PIC that we support, we need to restore the TOC @@ -10560,7 +10560,7 @@ (define_insn "*largetoc_high" (match_operand:DI 2 "gpc_reg_operand" "b")] UNSPEC_TOCREL)))] "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL" - "{cau|addis} %0,%2,%1@toc@ha") + "addis %0,%2,%1@toc@ha") (define_insn "*largetoc_high_plus" [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r") @@ -10571,7 +10571,7 @@ (define_insn "*largetoc_high_plus" UNSPEC_TOCREL) (match_operand 3 "const_int_operand" "n"))))] "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL" - "{cau|addis} %0,%2,%1+%3@toc@ha") + "addis %0,%2,%1+%3@toc@ha") (define_insn "*largetoc_low" [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") @@ -10579,14 +10579,14 @@ (define_insn "*largetoc_low" (match_operand:DI 2 "" "")))] "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL" "@ - {cal %0,%2@l(%1)|addi %0,%1,%2@l} - {ai|addic} %0,%1,%2@l") + addi %0,%1,%2@l + addic %0,%1,%2@l") (define_insn_and_split "*tocref<mode>" [(set (match_operand:P 0 "gpc_reg_operand" "=b*r") (match_operand:P 1 "small_toc_ref" "R"))] "TARGET_TOC" - "{cal|la} %0,%a1" + "la %0,%a1" "&& TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL && reload_completed" [(set (match_dup 0) (high:P (match_dup 1))) (set (match_dup 0) (lo_sum:P (match_dup 0) (match_dup 1)))]) @@ -10599,7 +10599,7 @@ (define_insn "elf_high" [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r") (high:SI (match_operand 1 "" "")))] "TARGET_ELF && ! TARGET_64BIT" - "{liu|lis} %0,%1@ha") + "lis %0,%1@ha") (define_insn "elf_low" [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") @@ -10607,8 +10607,8 @@ (define_insn "elf_low" (match_operand 2 "" "")))] "TARGET_ELF && ! TARGET_64BIT" "@ - {cal|la} %0,%2@l(%1) - {ai|addic} %0,%1,%K2") + la %0,%2@l(%1) + addic %0,%1,%K2") ;; Call and call_value insns (define_expand "call" @@ -11368,7 +11368,7 @@ (define_insn "probe_stack" "* { operands[1] = gen_rtx_REG (Pmode, 0); - return \"{st%U0%X0|stw%U0%X0} %1,%0\"; + return \"stw%U0%X0 %1,%0\"; }" [(set_attr "type" "store") (set_attr "length" "4")]) @@ -11493,7 +11493,7 @@ (define_insn "stack_protect_setsi" (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET)) (set (match_scratch:SI 2 "=&r") (const_int 0))] "TARGET_32BIT" - "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0" + "lwz%U1%X1 %2,%1\;stw%U0%X0 %2,%0\;li %2,0" [(set_attr "type" "three") (set_attr "length" "12")]) @@ -11502,7 +11502,7 @@ (define_insn "stack_protect_setdi" (unspec:DI [(match_operand:DI 1 "memory_operand" "Y")] UNSPEC_SP_SET)) (set (match_scratch:DI 2 "=&r") (const_int 0))] "TARGET_64BIT" - "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0" + "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;li %2,0" [(set_attr "type" "three") (set_attr "length" "12")]) @@ -11534,8 +11534,8 @@ (define_insn "stack_protect_testsi" (clobber (match_scratch:SI 3 "=&r,&r"))] "TARGET_32BIT" "@ - {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0 - {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0" + lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0 + lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;cmplw %0,%3,%4\;li %3,0\;li %4,0" [(set_attr "length" "16,20")]) (define_insn "stack_protect_testdi" @@ -11547,8 +11547,8 @@ (define_insn "stack_protect_testdi" (clobber (match_scratch:DI 3 "=&r,&r"))] "TARGET_64BIT" "@ - ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0 - ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0" + ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0 + ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;li %3,0\;li %4,0" [(set_attr "length" "16,20")]) @@ -11558,7 +11558,7 @@ (define_insn "*cmp<mode>_internal1" (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r") (match_operand:GPR 2 "reg_or_short_operand" "rI")))] "" - "{cmp%I2|cmp<wd>%I2} %0,%1,%2" + "cmp<wd>%I2 %0,%1,%2" [(set_attr "type" "cmp")]) ;; If we are comparing a register for equality with a large constant, @@ -11609,7 +11609,7 @@ (define_insn "*cmpsi_internal2" (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_u_short_operand" "rK")))] "" - "{cmpl%I2|cmplw%I2} %0,%1,%b2" + "cmplw%I2 %0,%1,%b2" [(set_attr "type" "cmp")]) (define_insn "*cmpdi_internal2" @@ -11767,7 +11767,7 @@ (define_insn "" [(match_operand 2 "cc_reg_operand" "y") (const_int 0)]))] "" - "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1" + "mfcr %0%Q2\;rlwinm %0,%0,%J1,1" [(set (attr "type") (cond [(match_test "TARGET_MFCRF") (const_string "mfcrf") @@ -11780,7 +11780,7 @@ (define_insn "move_from_CR_gt_bit" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))] "TARGET_HARD_FLOAT && !TARGET_FPRS" - "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31" + "mfcr %0\;rlwinm %0,%0,%D1,31,31" [(set_attr "type" "mfcr") (set_attr "length" "8")]) @@ -11789,7 +11789,7 @@ (define_insn "move_from_CR_ov_bit" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))] "TARGET_ISEL" - "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1" + "mfcr %0\;rlwinm %0,%0,%t1,1" [(set_attr "type" "mfcr") (set_attr "length" "8")]) @@ -11799,7 +11799,7 @@ (define_insn "" [(match_operand 2 "cc_reg_operand" "y") (const_int 0)]))] "TARGET_POWERPC64" - "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1" + "mfcr %0%Q2\;rlwinm %0,%0,%J1,1" [(set (attr "type") (cond [(match_test "TARGET_MFCRF") (const_string "mfcrf") @@ -11817,7 +11817,7 @@ (define_insn "" (match_op_dup 1 [(match_dup 2) (const_int 0)]))] "TARGET_32BIT" "@ - mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1 + mfcr %3%Q2\;rlwinm. %3,%3,%J1,1 #" [(set_attr "type" "delayed_compare") (set_attr "length" "8,16")]) @@ -11859,7 +11859,7 @@ (define_insn "" operands[4] = GEN_INT (count); operands[5] = GEN_INT (put_bit); - return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\"; + return \"mfcr %0%Q2\;rlwinm %0,%0,%4,%5,%5\"; }" [(set (attr "type") (cond [(match_test "TARGET_MFCRF") @@ -11898,7 +11898,7 @@ (define_insn "" operands[5] = GEN_INT (count); operands[6] = GEN_INT (put_bit); - return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\"; + return \"mfcr %4%Q2\;rlwinm. %4,%4,%5,%6,%6\"; }" [(set_attr "type" "delayed_compare") (set_attr "length" "8,16")]) @@ -11936,7 +11936,7 @@ (define_peephole [(match_operand 5 "cc_reg_operand" "y") (const_int 0)]))] "REGNO (operands[2]) != REGNO (operands[5])" - "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" + "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1" [(set_attr "type" "mfcr") (set_attr "length" "12")]) @@ -11950,7 +11950,7 @@ (define_peephole [(match_operand 5 "cc_reg_operand" "y") (const_int 0)]))] "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])" - "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" + "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1" [(set_attr "type" "mfcr") (set_attr "length" "12")]) @@ -12066,11 +12066,11 @@ (define_insn "*plus_eqsi" (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))] "TARGET_32BIT" "@ - xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 - {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3 - {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 - {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 - {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3" + xor %0,%1,%2\;subfic %0,%0,0\;addze %0,%3 + subfic %0,%1,0\;addze %0,%3 + xori %0,%1,%b2\;subfic %0,%0,0\;addze %0,%3 + xoris %0,%1,%u2\;subfic %0,%0,0\;addze %0,%3 + subfic %0,%1,%2\;subfic %0,%0,0\;addze %0,%3" [(set_attr "type" "three,two,three,three,three") (set_attr "length" "12,8,12,12,12")]) @@ -12085,11 +12085,11 @@ (define_insn "*compare_plus_eqsi" (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))] "TARGET_32BIT && optimize_size" "@ - xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 - {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3 - {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 - {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 - {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 + xor %4,%1,%2\;subfic %4,%4,0\;addze. %4,%3 + subfic %4,%1,0\;addze. %4,%3 + xori %4,%1,%b2\;subfic %4,%4,0\;addze. %4,%3 + xoris %4,%1,%u2\;subfic %4,%4,0\;addze. %4,%3 + subfic %4,%1,%2\;subfic %4,%4,0\;addze. %4,%3 # # # @@ -12129,11 +12129,11 @@ (define_insn "*plus_eqsi_compare" (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "TARGET_32BIT && optimize_size" "@ - xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 - {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3 - {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 - {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 - {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 + xor %0,%1,%2\;subfic %0,%0,0\;addze. %0,%3 + subfic %0,%1,0\;addze. %0,%3 + xori %0,%1,%b2\;subfic %0,%0,0\;addze. %0,%3 + xoris %0,%1,%u2\;subfic %0,%0,0\;addze. %0,%3 + subfic %0,%1,%2\;subfic %0,%0,0\;addze. %0,%3 # # # @@ -12165,7 +12165,7 @@ (define_insn "*neg_eq0<mode>" (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r") (const_int 0))))] "" - "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0" + "addic %0,%1,-1\;subfe %0,%0,%0" [(set_attr "type" "two") (set_attr "length" "8")]) @@ -12205,7 +12205,7 @@ (define_insn "*ne0si" (const_int 31))) (clobber (match_scratch:SI 2 "=&r"))] "TARGET_32BIT && !TARGET_ISEL" - "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1" + "addic %2,%1,-1\;subfe %0,%2,%1" [(set_attr "type" "two") (set_attr "length" "8")]) @@ -12228,7 +12228,7 @@ (define_insn "*plus_ne0si" (match_operand:SI 2 "gpc_reg_operand" "r"))) (clobber (match_scratch:SI 3 "=&r"))] "TARGET_32BIT" - "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2" + "addic %3,%1,-1\;addze %0,%2" [(set_attr "type" "two") (set_attr "length" "8")]) @@ -12256,7 +12256,7 @@ (define_insn "*compare_plus_ne0si" (clobber (match_scratch:SI 4 "=X,&r"))] "TARGET_32BIT" "@ - {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2 + addic %3,%1,-1\;addze. %3,%2 #" [(set_attr "type" "compare") (set_attr "length" "8,12")]) @@ -12331,7 +12331,7 @@ (define_insn "*plus_ne0si_compare" (clobber (match_scratch:SI 3 "=&r,&r"))] "TARGET_32BIT" "@ - {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2 + addic %3,%1,-1\;addze. %0,%2 #" [(set_attr "type" "compare") (set_attr "length" "8,12")]) @@ -12404,7 +12404,7 @@ (define_insn "*leu<mode>" (leu:P (match_operand:P 1 "gpc_reg_operand" "r") (match_operand:P 2 "reg_or_short_operand" "rI")))] "" - "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" + "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0" [(set_attr "type" "three") (set_attr "length" "12")]) @@ -12418,7 +12418,7 @@ (define_insn "*leu<mode>_compare" (leu:P (match_dup 1) (match_dup 2)))] "" "@ - {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 + subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0 #" [(set_attr "type" "compare") (set_attr "length" "12,16")]) @@ -12445,7 +12445,7 @@ (define_insn "*plus_leu<mode>" (match_operand:P 2 "reg_or_short_operand" "rI")) (match_operand:P 3 "gpc_reg_operand" "r")))] "" - "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3" + "subf%I2c %0,%1,%2\;addze %0,%3" [(set_attr "type" "two") (set_attr "length" "8")]) @@ -12459,7 +12459,7 @@ (define_insn "" (clobber (match_scratch:SI 4 "=&r,&r"))] "TARGET_32BIT" "@ - {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3 + subf%I2c %4,%1,%2\;addze. %4,%3 #" [(set_attr "type" "compare") (set_attr "length" "8,12")]) @@ -12492,7 +12492,7 @@ (define_insn "" (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "TARGET_32BIT" "@ - {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3 + subf%I2c %0,%1,%2\;addze. %0,%3 #" [(set_attr "type" "compare") (set_attr "length" "8,12")]) @@ -12519,7 +12519,7 @@ (define_insn "*neg_leu<mode>" (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r") (match_operand:P 2 "reg_or_short_operand" "rI"))))] "" - "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0" + "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;nand %0,%0,%0" [(set_attr "type" "three") (set_attr "length" "12")]) @@ -12530,7 +12530,7 @@ (define_insn "*and_neg_leu<mode>" (match_operand:P 2 "reg_or_short_operand" "rI"))) (match_operand:P 3 "gpc_reg_operand" "r")))] "" - "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0" + "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;andc %0,%3,%0" [(set_attr "type" "three") (set_attr "length" "12")]) @@ -12545,7 +12545,7 @@ (define_insn "" (clobber (match_scratch:SI 4 "=&r,&r"))] "TARGET_32BIT" "@ - {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 + subf%I2c %4,%1,%2\;subfe %4,%4,%4\;andc. %4,%3,%4 #" [(set_attr "type" "compare") (set_attr "length" "12,16")]) @@ -12580,7 +12580,7 @@ (define_insn "" (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] "TARGET_32BIT" "@ - {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 + subf%I2c %0,%1,%2\;subfe %0,%0,%0\;andc. %0,%3,%0 #" [(set_attr "type" "compare") (set_attr "length" "12,16")]) @@ -12669,8 +12669,8 @@ (define_insn "*neg_ltu<mode>" (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))] "" "@ - {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0 - {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0" + subfc %0,%2,%1\;subfe %0,%0,%0 + addic %0,%1,%n2\;subfe %0,%0,%0" [(set_attr "type" "two") (set_attr "length" "8")]) @@ -12680,8 +12680,8 @@ (define_insn "*geu<mode>" (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))] "" "@ - {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0 - {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" + subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0 + addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0" [(set_attr "type" "three") (set_attr "length" "12")]) @@ -12695,8 +12695,8 @@ (define_insn "*geu<mode>_compare" (geu:P (match_dup 1) (match_dup 2)))] "" "@ - {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 - {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 + subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0 + addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0 # #" [(set_attr "type" "compare") @@ -12725,8 +12725,8 @@ (define_insn "*plus_geu<mode>" (match_operand:P 3 "gpc_reg_operand" "r,r")))] "" "@ - {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3 - {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3" + subfc %0,%2,%1\;addze %0,%3 + addic %0,%1,%n2\;addze %0,%3" [(set_attr "type" "two") (set_attr "length" "8")]) @@ -12740,8 +12740,8 @@ (define_insn "" (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] "TARGET_32BIT" "@ - {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3 - {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3 + subfc %4,%2,%1\;addze. %4,%3 + addic %4,%1,%n2\;addze. %4,%3 # #" [(set_attr "type" "compare") @@ -12775,8 +12775,8 @@ (define_insn "" (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "TARGET_32BIT" "@ - {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3 - {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3 + subfc %0,%2,%1\;addze. %0,%3 + addic %0,%1,%n2\;addze. %0,%3 # #" [(set_attr "type" "compare") @@ -12805,8 +12805,8 @@ (define_insn "*neg_geu<mode>" (match_operand:P 2 "reg_or_short_operand" "r,I"))))] "" "@ - {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0 - {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0" + subfc %0,%2,%1\;subfe %0,%0,%0\;nand %0,%0,%0 + subfic %0,%1,-1\;add%I2c %0,%0,%2\;subfe %0,%0,%0" [(set_attr "type" "three") (set_attr "length" "12")]) @@ -12818,8 +12818,8 @@ (define_insn "*and_neg_geu<mode>" (match_operand:P 3 "gpc_reg_operand" "r,r")))] "" "@ - {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0 - {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0" + subfc %0,%2,%1\;subfe %0,%0,%0\;andc %0,%3,%0 + addic %0,%1,%n2\;subfe %0,%0,%0\;andc %0,%3,%0" [(set_attr "type" "three") (set_attr "length" "12")]) @@ -12834,8 +12834,8 @@ (define_insn "" (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] "TARGET_32BIT" "@ - {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 - {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 + subfc %4,%2,%1\;subfe %4,%4,%4\;andc. %4,%3,%4 + addic %4,%1,%n2\;subfe %4,%4,%4\;andc. %4,%3,%4 # #" [(set_attr "type" "compare") @@ -12871,8 +12871,8 @@ (define_insn "" (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] "TARGET_32BIT" "@ - {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 - {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 + subfc %0,%2,%1\;subfe %0,%0,%0\;andc. %0,%3,%0 + addic %0,%1,%n2\;subfe %0,%0,%0\;andc. %0,%3,%0 # #" [(set_attr "type" "compare") @@ -12902,7 +12902,7 @@ (define_insn "*plus_gt0<mode>" (const_int 0)) (match_operand:P 2 "gpc_reg_operand" "r")))] "" - "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2" + "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2" [(set_attr "type" "three") (set_attr "length" "12")]) @@ -12916,7 +12916,7 @@ (define_insn "" (clobber (match_scratch:SI 3 "=&r,&r"))] "TARGET_32BIT" "@ - {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2 + addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2 #" [(set_attr "type" "compare") (set_attr "length" "12,16")]) @@ -12981,7 +12981,7 @@ (define_insn "" (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))] "TARGET_32BIT" "@ - {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2 + addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2 #" [(set_attr "type" "compare") (set_attr "length" "12,16")]) @@ -13100,7 +13100,7 @@ (define_insn "*neg_gtu<mode>" (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r") (match_operand:P 2 "reg_or_short_operand" "rI"))))] "" - "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0" + "subf%I2c %0,%1,%2\;subfe %0,%0,%0" [(set_attr "type" "two") (set_attr "length" "8")]) @@ -13227,7 +13227,7 @@ (define_insn "*cceq_rev_compare" (const_int 0)]) (const_int 0)))] "" - "{crnor %E0,%j1,%j1|crnot %E0,%j1}" + "crnot %E0,%j1" [(set_attr "type" "cr_logical,delayed_cr")]) ;; If we are comparing the result of two comparisons, this can be done @@ -13296,7 +13296,7 @@ (define_insn "jump" (define_insn "<return_str>return" [(any_return)] "<return_pred>" - "{br|blr}" + "blr" [(set_attr "type" "jmpreg")]) (define_expand "indirect_jump" @@ -13307,7 +13307,7 @@ (define_insn "*indirect_jump<mode>" "" "@ bctr - {br|blr}" + blr" [(set_attr "type" "jmpreg")]) ;; Table jump for switch statements: @@ -13359,13 +13359,13 @@ (define_insn "*tablejump<mode>_internal1" "" "@ bctr - {br|blr}" + blr" [(set_attr "type" "jmpreg")]) (define_insn "nop" [(const_int 0)] "" - "{cror 0,0,0|nop}") + "nop") (define_insn "group_ending_nop" [(unspec [(const_int 0)] UNSPEC_GRP_END_NOP)] @@ -13444,7 +13444,7 @@ (define_insn "*ctr<mode>_internal1" if (which_alternative != 0) return \"#\"; else if (get_attr_length (insn) == 4) - return \"{bdn|bdnz} %l0\"; + return \"bdnz %l0\"; else return \"bdz $+8\;b %l0\"; }" @@ -13470,7 +13470,7 @@ (define_insn "*ctr<mode>_internal2" else if (get_attr_length (insn) == 4) return \"bdz %l0\"; else - return \"{bdn|bdnz} $+8\;b %l0\"; + return \"bdnz $+8\;b %l0\"; }" [(set_attr "type" "branch") (set_attr "length" "*,12,16,16")]) @@ -13496,7 +13496,7 @@ (define_insn "*ctr<mode>_internal5" else if (get_attr_length (insn) == 4) return \"bdz %l0\"; else - return \"{bdn|bdnz} $+8\;b %l0\"; + return \"bdnz $+8\;b %l0\"; }" [(set_attr "type" "branch") (set_attr "length" "*,12,16,16")]) @@ -13518,7 +13518,7 @@ (define_insn "*ctr<mode>_internal6" if (which_alternative != 0) return \"#\"; else if (get_attr_length (insn) == 4) - return \"{bdn|bdnz} %l0\"; + return \"bdnz %l0\"; else return \"bdz $+8\;b %l0\"; }" @@ -13584,7 +13584,7 @@ (define_split (define_insn "trap" [(trap_if (const_int 1) (const_int 0))] "" - "{t 31,0,0|trap}" + "trap" [(set_attr "type" "trap")]) (define_expand "ctrap<mode>4" @@ -13601,7 +13601,7 @@ (define_insn "" (match_operand:GPR 2 "reg_or_short_operand" "rI")]) (const_int 0))] "" - "{t|t<wd>}%V0%I2 %1,%2" + "t<wd>%V0%I2 %1,%2" [(set_attr "type" "trap")]) ;; Insns related to generating the function prologue and epilogue. @@ -13653,7 +13653,7 @@ (define_insn "*stmw" [(set (match_operand:SI 1 "memory_operand" "=m") (match_operand:SI 2 "gpc_reg_operand" "r"))])] "TARGET_MULTIPLE" - "{stm|stmw} %2,%1" + "stmw %2,%1" [(set_attr "type" "store_ux")]) ; The following comment applies to: @@ -13812,7 +13812,7 @@ (define_insn "*lmw" [(set (match_operand:SI 1 "gpc_reg_operand" "=r") (match_operand:SI 2 "memory_operand" "m"))])] "TARGET_MULTIPLE" - "{lm|lmw} %1,%2" + "lmw %1,%2" [(set_attr "type" "load_ux") (set_attr "cell_micro" "always")]) diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index 9f3567a..878b0fb 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -150,14 +150,6 @@ mstring Target Report Mask(STRING) Save Generate string instructions for block moves -mnew-mnemonics -Target Report RejectNegative Mask(NEW_MNEMONICS) -Use new mnemonics for PowerPC architecture - -mold-mnemonics -Target Report RejectNegative InverseMask(NEW_MNEMONICS) -Use old mnemonics for PowerPC architecture - msoft-float Target Report RejectNegative Mask(SOFT_FLOAT) Do not use hardware floating point diff --git a/gcc/config/rs6000/spe.md b/gcc/config/rs6000/spe.md index 43cdbfa..bf59b6c 100644 --- a/gcc/config/rs6000/spe.md +++ b/gcc/config/rs6000/spe.md @@ -2289,9 +2289,9 @@ (define_insn "*frob_<DITI:mode>_<SPE64:mode>_2" known to be dead. */ if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, operands[1], 0)) - return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; + return \"lwz %L0,%L1\;lwz %0,%1\"; else - return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\"; + return \"lwz%U1%X1 %0,%1\;lwz %L0,%L1\"; } }" [(set_attr "length" "8,8")]) @@ -2315,9 +2315,9 @@ (define_insn "*frob_ti_<mode>_8_2" return \"evldd%X1 %Z0,%y1\;evmergehi %Y0,%Z0,%Z0\"; if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, operands[1], 0)) - return \"{l|lwz} %Z0,%L1\;{l|lwz} %Y0,%1\"; + return \"lwz %Z0,%L1\;lwz %Y0,%1\"; else - return \"{l%U1%X1|lwz%U1%X1} %Y0,%1\;{l|lwz} %Z0,%L1\"; + return \"lwz%U1%X1 %Y0,%1\;lwz %Z0,%L1\"; } }" [(set_attr "length" "8,8")]) @@ -2336,7 +2336,7 @@ (define_insn "mov_si<mode>_e500_subreg0" || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)" "@ evmergelo %0,%1,%0 - evmergelohi %0,%0,%0\;{l%U1%X1|lwz%U1%X1} %0,%1\;evmergelohi %0,%0,%0" + evmergelohi %0,%0,%0\;lwz%U1%X1 %0,%1\;evmergelohi %0,%0,%0" [(set_attr "length" "4,12")]) (define_insn_and_split "*mov_si<mode>_e500_subreg0_elf_low" @@ -2366,7 +2366,7 @@ (define_insn "*mov_si<mode>_e500_subreg0_2" || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)" "@ evmergehi %0,%0,%1 - evmergelohi %1,%1,%1\;{st%U0%X0|stw%U0%X0} %1,%0" + evmergelohi %1,%1,%1\;stw%U0%X0 %1,%0" [(set_attr "length" "4,8")]) (define_insn "*mov_si<mode>_e500_subreg4" @@ -2376,7 +2376,7 @@ (define_insn "*mov_si<mode>_e500_subreg4" || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)" "@ mr %0,%1 - {l%U1%X1|lwz%U1%X1} %0,%1") + lwz%U1%X1 %0,%1") (define_insn "*mov_si<mode>_e500_subreg4_elf_low" [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r") 4) @@ -2385,7 +2385,7 @@ (define_insn "*mov_si<mode>_e500_subreg4_elf_low" "((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode)) || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)) && TARGET_ELF && !TARGET_64BIT" - "{ai|addic} %0,%1,%K2") + "addic %0,%1,%K2") (define_insn "*mov_si<mode>_e500_subreg4_2" [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m") @@ -2394,7 +2394,7 @@ (define_insn "*mov_si<mode>_e500_subreg4_2" || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)" "@ mr %0,%1 - {st%U0%X0|stw%U0%X0} %1,%0") + stw%U0%X0 %1,%0") (define_insn "*mov_sitf_e500_subreg8" [(set (subreg:SI (match_operand:TF 0 "register_operand" "+r,&r") 8) @@ -2402,7 +2402,7 @@ (define_insn "*mov_sitf_e500_subreg8" "TARGET_E500_DOUBLE" "@ evmergelo %L0,%1,%L0 - evmergelohi %L0,%L0,%L0\;{l%U1%X1|lwz%U1%X1} %L0,%1\;evmergelohi %L0,%L0,%L0" + evmergelohi %L0,%L0,%L0\;lwz%U1%X1 %L0,%1\;evmergelohi %L0,%L0,%L0" [(set_attr "length" "4,12")]) (define_insn "*mov_sitf_e500_subreg8_2" @@ -2411,7 +2411,7 @@ (define_insn "*mov_sitf_e500_subreg8_2" "TARGET_E500_DOUBLE" "@ evmergehi %0,%0,%L1 - evmergelohi %L1,%L1,%L1\;{st%U0%X0|stw%U0%X0} %L1,%0" + evmergelohi %L1,%L1,%L1\;stw%U0%X0 %L1,%0" [(set_attr "length" "4,8")]) (define_insn "*mov_sitf_e500_subreg12" @@ -2420,7 +2420,7 @@ (define_insn "*mov_sitf_e500_subreg12" "TARGET_E500_DOUBLE" "@ mr %L0,%1 - {l%U1%X1|lwz%U1%X1} %L0,%1") + lwz%U1%X1 %L0,%1") (define_insn "*mov_sitf_e500_subreg12_2" [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m") @@ -2428,7 +2428,7 @@ (define_insn "*mov_sitf_e500_subreg12_2" "TARGET_E500_DOUBLE" "@ mr %0,%L1 - {st%U0%X0|stw%U0%X0} %L1,%0") + stw%U0%X0 %L1,%0") ;; FIXME: Allow r=CONST0. (define_insn "*movdf_e500_double" diff --git a/gcc/config/rs6000/sync.md b/gcc/config/rs6000/sync.md index f1e3515..013e09c 100644 --- a/gcc/config/rs6000/sync.md +++ b/gcc/config/rs6000/sync.md @@ -66,7 +66,7 @@ (define_insn "*hwsync" [(set (match_operand:BLK 0 "" "") (unspec:BLK [(match_dup 0)] UNSPEC_SYNC))] "" - "{dcs|sync}" + "sync" [(set_attr "type" "sync")]) (define_expand "lwsync" @@ -96,7 +96,7 @@ (define_insn "*lwsync" (define_insn "isync" [(unspec_volatile:BLK [(const_int 0)] UNSPECV_ISYNC)] "" - "{ics|isync}" + "isync" [(set_attr "type" "isync")]) ;; The control dependency used for load dependency described diff --git a/gcc/config/rs6000/sysv4.h b/gcc/config/rs6000/sysv4.h index d43a699..978ba31 100644 --- a/gcc/config/rs6000/sysv4.h +++ b/gcc/config/rs6000/sysv4.h @@ -220,7 +220,7 @@ do { \ /* Override rs6000.h definition. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT MASK_NEW_MNEMONICS +#define TARGET_DEFAULT 0 /* Override rs6000.h definition. */ #undef PROCESSOR_DEFAULT @@ -450,7 +450,7 @@ do { \ do { \ if (DEFAULT_ABI == ABI_V4) \ asm_fprintf (FILE, \ - "\t{stu|stwu} %s,-16(%s)\n\t{st|stw} %s,12(%s)\n", \ + "\tstwu %s,-16(%s)\n\tstw %s,12(%s)\n", \ reg_names[1], reg_names[1], reg_names[REGNO], \ reg_names[1]); \ } while (0) @@ -462,7 +462,7 @@ do { \ do { \ if (DEFAULT_ABI == ABI_V4) \ asm_fprintf (FILE, \ - "\t{l|lwz} %s,12(%s)\n\t{ai|addic} %s,%s,16\n", \ + "\tlwz %s,12(%s)\n\taddic %s,%s,16\n", \ reg_names[REGNO], reg_names[1], reg_names[1], \ reg_names[1]); \ } while (0) diff --git a/gcc/config/rs6000/sysv4le.h b/gcc/config/rs6000/sysv4le.h index f5726db..a899501 100644 --- a/gcc/config/rs6000/sysv4le.h +++ b/gcc/config/rs6000/sysv4le.h @@ -20,7 +20,7 @@ <http://www.gnu.org/licenses/>. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_NEW_MNEMONICS | MASK_LITTLE_ENDIAN) +#define TARGET_DEFAULT MASK_LITTLE_ENDIAN #undef CC1_ENDIAN_DEFAULT_SPEC #define CC1_ENDIAN_DEFAULT_SPEC "%(cc1_endian_little)" diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 37cb248..58db3cf 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -545,7 +545,7 @@ (define_insn "*vsx_fmadf4" xsmaddmdp %x0,%x1,%x3 xsmaddadp %x0,%x1,%x2 xsmaddmdp %x0,%x1,%x3 - {fma|fmadd} %0,%1,%2,%3" + fmadd %0,%1,%2,%3" [(set_attr "type" "fp") (set_attr "fp_type" "fp_maddsub_d")]) @@ -591,7 +591,7 @@ (define_insn "*vsx_fmsdf4" xsmsubmdp %x0,%x1,%x3 xsmsubadp %x0,%x1,%x2 xsmsubmdp %x0,%x1,%x3 - {fms|fmsub} %0,%1,%2,%3" + fmsub %0,%1,%2,%3" [(set_attr "type" "fp") (set_attr "fp_type" "fp_maddsub_d")]) @@ -623,7 +623,7 @@ (define_insn "*vsx_nfmadf4" xsnmaddmdp %x0,%x1,%x3 xsnmaddadp %x0,%x1,%x2 xsnmaddmdp %x0,%x1,%x3 - {fnma|fnmadd} %0,%1,%2,%3" + fnmadd %0,%1,%2,%3" [(set_attr "type" "fp") (set_attr "fp_type" "fp_maddsub_d")]) @@ -657,7 +657,7 @@ (define_insn "*vsx_nfmsdf4" xsnmsubmdp %x0,%x1,%x3 xsnmsubadp %x0,%x1,%x2 xsnmsubmdp %x0,%x1,%x3 - {fnms|fnmsub} %0,%1,%2,%3" + fnmsub %0,%1,%2,%3" [(set_attr "type" "fp") (set_attr "fp_type" "fp_maddsub_d")]) diff --git a/gcc/config/rs6000/vxworks.h b/gcc/config/rs6000/vxworks.h index 2213037..74761dc 100644 --- a/gcc/config/rs6000/vxworks.h +++ b/gcc/config/rs6000/vxworks.h @@ -99,7 +99,7 @@ VXWORKS_ADDITIONAL_CPP_SPEC #undef MULTILIB_DEFAULTS #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_NEW_MNEMONICS | MASK_EABI | MASK_STRICT_ALIGN) +#define TARGET_DEFAULT (MASK_EABI | MASK_STRICT_ALIGN) #undef PROCESSOR_DEFAULT #define PROCESSOR_DEFAULT PROCESSOR_PPC604 diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 78bcde7..cf93dbf 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -804,7 +804,6 @@ See RS/6000 and PowerPC Options. -mmfcrf -mno-mfcrf -mpopcntb -mno-popcntb -mpopcntd -mno-popcntd @gol -mfprnd -mno-fprnd @gol -mcmpb -mno-cmpb -mmfpgpr -mno-mfpgpr -mhard-dfp -mno-hard-dfp @gol --mnew-mnemonics -mold-mnemonics @gol -mfull-toc -mminimal-toc -mno-fp-in-toc -mno-sum-in-toc @gol -m64 -m32 -mxl-compat -mno-xl-compat -mpe @gol -malign-power -malign-natural @gol @@ -16640,26 +16639,9 @@ The @option{-mpowerpc64} option allows GCC to generate the additional and to treat GPRs as 64-bit, doubleword quantities. GCC defaults to @option{-mno-powerpc64}. -@item -mnew-mnemonics -@itemx -mold-mnemonics -@opindex mnew-mnemonics -@opindex mold-mnemonics -Select which mnemonics to use in the generated assembler code. With -@option{-mnew-mnemonics}, GCC uses the assembler mnemonics defined for -the PowerPC architecture. With @option{-mold-mnemonics} it uses the -assembler mnemonics defined for the POWER architecture. Instructions -defined in only one architecture have only one mnemonic; GCC uses that -mnemonic irrespective of which of these options is specified. - -GCC defaults to the mnemonics appropriate for the architecture in -use. Specifying @option{-mcpu=@var{cpu_type}} sometimes overrides the -value of these option. Unless you are building a cross-compiler, you -should normally not specify either @option{-mnew-mnemonics} or -@option{-mold-mnemonics}, but should instead accept the default. - @item -mcpu=@var{cpu_type} @opindex mcpu -Set architecture type, register usage, choice of mnemonics, and +Set architecture type, register usage, and instruction scheduling parameters for machine type @var{cpu_type}. Supported values for @var{cpu_type} are @samp{401}, @samp{403}, @samp{405}, @samp{405fp}, @samp{440}, @samp{440fp}, @samp{464}, @samp{464fp}, @@ -16686,7 +16668,7 @@ The @option{-mcpu} options automatically enable or disable the following options: @gccoptlist{-maltivec -mfprnd -mhard-float -mmfcrf -mmultiple @gol --mnew-mnemonics -mpopcntb -mpopcntd -mpowerpc64 @gol +-mpopcntb -mpopcntd -mpowerpc64 @gol -mpowerpc-gpopt -mpowerpc-gfxopt -msingle-float -mdouble-float @gol -msimple-fpu -mstring -mmulhw -mdlmzb -mmfpgpr -mvsx} @@ -16706,11 +16688,11 @@ environment. @item -mtune=@var{cpu_type} @opindex mtune Set the instruction scheduling parameters for machine type -@var{cpu_type}, but do not set the architecture type, register usage, or -choice of mnemonics, as @option{-mcpu=@var{cpu_type}} does. The same +@var{cpu_type}, but do not set the architecture type or register usage, +as @option{-mcpu=@var{cpu_type}} does. The same values for @var{cpu_type} are used for @option{-mtune} as for @option{-mcpu}. If both are specified, the code generated uses the -architecture, registers, and mnemonics set by @option{-mcpu}, but the +architecture and registers set by @option{-mcpu}, but the scheduling parameters set by @option{-mtune}. @item -mcmodel=small diff --git a/libgcc/longlong.h b/libgcc/longlong.h index 0427718..c62194e 100644 --- a/libgcc/longlong.h +++ b/libgcc/longlong.h @@ -862,37 +862,37 @@ UDItype __umulsidi3 (USItype, USItype); #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ do { \ if (__builtin_constant_p (bh) && (bh) == 0) \ - __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \ + __asm__ ("add%I4c %1,%3,%4\n\taddze %0,%2" \ : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\ else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \ - __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \ + __asm__ ("add%I4c %1,%3,%4\n\taddme %0,%2" \ : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\ else \ - __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \ + __asm__ ("add%I5c %1,%4,%5\n\tadde %0,%2,%3" \ : "=r" (sh), "=&r" (sl) \ : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \ } while (0) #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ do { \ if (__builtin_constant_p (ah) && (ah) == 0) \ - __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \ + __asm__ ("subf%I3c %1,%4,%3\n\tsubfze %0,%2" \ : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\ else if (__builtin_constant_p (ah) && (ah) == ~(USItype) 0) \ - __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \ + __asm__ ("subf%I3c %1,%4,%3\n\tsubfme %0,%2" \ : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\ else if (__builtin_constant_p (bh) && (bh) == 0) \ - __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \ + __asm__ ("subf%I3c %1,%4,%3\n\taddme %0,%2" \ : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\ else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \ - __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \ + __asm__ ("subf%I3c %1,%4,%3\n\taddze %0,%2" \ : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\ else \ - __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \ + __asm__ ("subf%I4c %1,%5,%4\n\tsubfe %0,%3,%2" \ : "=r" (sh), "=&r" (sl) \ : "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \ } while (0) #define count_leading_zeros(count, x) \ - __asm__ ("{cntlz|cntlzw} %0,%1" : "=r" (count) : "r" (x)) + __asm__ ("cntlzw %0,%1" : "=r" (count) : "r" (x)) #define COUNT_LEADING_ZEROS_0 32 #if defined (_ARCH_PPC) || defined (__powerpc__) || defined (__POWERPC__) \ || defined (__ppc__) \ @@ -931,32 +931,32 @@ UDItype __umulsidi3 (USItype, USItype); #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ do { \ if (__builtin_constant_p (bh) && (bh) == 0) \ - __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \ + __asm__ ("add%I4c %1,%3,%4\n\taddze %0,%2" \ : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\ else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \ - __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \ + __asm__ ("add%I4c %1,%3,%4\n\taddme %0,%2" \ : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\ else \ - __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \ + __asm__ ("add%I5c %1,%4,%5\n\tadde %0,%2,%3" \ : "=r" (sh), "=&r" (sl) \ : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \ } while (0) #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ do { \ if (__builtin_constant_p (ah) && (ah) == 0) \ - __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \ + __asm__ ("subf%I3c %1,%4,%3\n\tsubfze %0,%2" \ : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\ else if (__builtin_constant_p (ah) && (ah) == ~(UDItype) 0) \ - __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \ + __asm__ ("subf%I3c %1,%4,%3\n\tsubfme %0,%2" \ : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\ else if (__builtin_constant_p (bh) && (bh) == 0) \ - __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \ + __asm__ ("subf%I3c %1,%4,%3\n\taddme %0,%2" \ : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\ else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \ - __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \ + __asm__ ("subf%I3c %1,%4,%3\n\taddze %0,%2" \ : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\ else \ - __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \ + __asm__ ("subf%I4c %1,%5,%4\n\tsubfe %0,%3,%2" \ : "=r" (sh), "=&r" (sl) \ : "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \ } while (0)

[5/7] rs6000: Get rid of old-mnemonics

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