@@ -7933,6 +7933,18 @@ (define_insn "*andqi_1_slp"
[(set_attr "type" "alu1")
(set_attr "mode" "QI")])
+;; Turn *anddi_1 into *andsi_1_zext if possible.
+(define_split
+ [(set (match_operand:DI 0 "register_operand")
+ (and:DI (subreg:DI (match_operand:SI 1 "register_operand") 0)
+ (match_operand:DI 2 "x86_64_zext_immediate_operand")))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_64BIT"
+ [(parallel [(set (match_dup 0)
+ (zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))
+ (clobber (reg:CC FLAGS_REG))])]
+ "operands[2] = gen_lowpart (SImode, operands[2]);")
+
(define_split
[(set (match_operand:SWI248 0 "register_operand")
(and:SWI248 (match_operand:SWI248 1 "nonimmediate_operand")