| Message ID | 1336347984-3714-4-git-send-email-afaerber@suse.de |
|---|---|
| State | New |
| Headers | show |
On 07.05.2012, at 01:46, Andreas Färber wrote: > Adjust the tcg_out_qemu_{ld,st}() slow paths to pass AREG0 in r3. > Automate the register numbering to avoid double-coding the two modes, > and introduce TCG_TARGET_CALL_ALIGN_I64_ARG() macro to align for SVR4 > but not for Darwin ABI. > > Based on patch by malc. AREG0-free PPC works for me with this patch on a ppc32 host. Tested-by: Alexander Graf <agraf@suse.de> Alex
On 08.05.2012, at 19:39, Alexander Graf wrote: > > On 07.05.2012, at 01:46, Andreas Färber wrote: > >> Adjust the tcg_out_qemu_{ld,st}() slow paths to pass AREG0 in r3. >> Automate the register numbering to avoid double-coding the two modes, >> and introduce TCG_TARGET_CALL_ALIGN_I64_ARG() macro to align for SVR4 >> but not for Darwin ABI. >> >> Based on patch by malc. > > AREG0-free PPC works for me with this patch on a ppc32 host. > > Tested-by: Alexander Graf <agraf@suse.de> I take that one back - it breaks once things get more complex. Debugging ... Alex
Am 08.05.2012 19:43, schrieb Alexander Graf: > > On 08.05.2012, at 19:39, Alexander Graf wrote: > >> On 07.05.2012, at 01:46, Andreas Färber wrote: >> >>> Adjust the tcg_out_qemu_{ld,st}() slow paths to pass AREG0 in r3. >>> Automate the register numbering to avoid double-coding the two modes, >>> and introduce TCG_TARGET_CALL_ALIGN_I64_ARG() macro to align for SVR4 >>> but not for Darwin ABI. >>> >>> Based on patch by malc. >> >> AREG0-free PPC works for me with this patch on a ppc32 host. >> >> Tested-by: Alexander Graf <agraf@suse.de> > > I take that one back - it breaks once things get more complex. Debugging ... We've been modifying the slow path here - I wonder if any changes are needed for the fast path? Don't understand that one unfortunately... Andreas
On 08.05.2012, at 21:34, Andreas Färber wrote: > Am 08.05.2012 19:43, schrieb Alexander Graf: >> >> On 08.05.2012, at 19:39, Alexander Graf wrote: >> >>> On 07.05.2012, at 01:46, Andreas Färber wrote: >>> >>>> Adjust the tcg_out_qemu_{ld,st}() slow paths to pass AREG0 in r3. >>>> Automate the register numbering to avoid double-coding the two modes, >>>> and introduce TCG_TARGET_CALL_ALIGN_I64_ARG() macro to align for SVR4 >>>> but not for Darwin ABI. >>>> >>>> Based on patch by malc. >>> >>> AREG0-free PPC works for me with this patch on a ppc32 host. >>> >>> Tested-by: Alexander Graf <agraf@suse.de> >> >> I take that one back - it breaks once things get more complex. Debugging ... > > We've been modifying the slow path here - I wonder if any changes are > needed for the fast path? Don't understand that one unfortunately... I already posted the fix :) Alex
diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c index 5a651ce..ace5548 100644 --- a/tcg/ppc/tcg-target.c +++ b/tcg/ppc/tcg-target.c @@ -39,6 +39,16 @@ static uint8_t *tb_ret_addr; #define LR_OFFSET 4 #endif +#ifdef TCG_TARGET_CALL_ALIGN_ARGS +#define TCG_TARGET_CALL_ALIGN_I64_ARG(reg) do { \ + if (((reg) % 2) == 0) { \ + (reg)++; \ + } \ + } while (0) +#else +#define TCG_TARGET_CALL_ALIGN_I64_ARG(reg) do { } while (0) +#endif + #define FAST_PATH #ifndef GUEST_BASE @@ -513,7 +523,6 @@ static void tcg_out_call (TCGContext *s, tcg_target_long arg, int const_arg) #include "../../softmmu_defs.h" #ifdef CONFIG_TCG_PASS_AREG0 -#error CONFIG_TCG_PASS_AREG0 is not supported /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr, int mmu_idx) */ static const void * const qemu_ld_helpers[4] = { @@ -556,7 +565,7 @@ static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc) { int addr_reg, data_reg, data_reg2, r0, r1, rbase, bswap; #ifdef CONFIG_SOFTMMU - int mem_index, s_bits, r2; + int mem_index, s_bits, r2, ir; void *label1_ptr, *label2_ptr; #if TARGET_LONG_BITS == 64 int addr_reg2; @@ -618,14 +627,20 @@ static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc) #endif /* slow path */ +#ifdef CONFIG_TCG_PASS_AREG0 + tcg_out_mov (s, TCG_TYPE_I32, 3, TCG_AREG0); + ir = 4; +#else + ir = 3; +#endif #if TARGET_LONG_BITS == 32 - tcg_out_mov (s, TCG_TYPE_I32, 3, addr_reg); - tcg_out_movi (s, TCG_TYPE_I32, 4, mem_index); + tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg); #else - tcg_out_mov (s, TCG_TYPE_I32, 3, addr_reg2); - tcg_out_mov (s, TCG_TYPE_I32, 4, addr_reg); - tcg_out_movi (s, TCG_TYPE_I32, 5, mem_index); + TCG_TARGET_CALL_ALIGN_I64_ARG (ir); + tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg2); + tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg); #endif + tcg_out_movi (s, TCG_TYPE_I32, ir, mem_index); tcg_out_call (s, (tcg_target_long) qemu_ld_helpers[s_bits], 1); switch (opc) { @@ -814,13 +829,18 @@ static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc) #endif /* slow path */ -#if TARGET_LONG_BITS == 32 - tcg_out_mov (s, TCG_TYPE_I32, 3, addr_reg); +#ifdef CONFIG_TCG_PASS_AREG0 + tcg_out_mov (s, TCG_TYPE_I32, 3, TCG_AREG0); ir = 4; #else - tcg_out_mov (s, TCG_TYPE_I32, 3, addr_reg2); - tcg_out_mov (s, TCG_TYPE_I32, 4, addr_reg); - ir = 5; + ir = 3; +#endif +#if TARGET_LONG_BITS == 32 + tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg); +#else + TCG_TARGET_CALL_ALIGN_I64_ARG (ir); + tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg2); + tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg); #endif switch (opc) { @@ -844,9 +864,7 @@ static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc) tcg_out_mov (s, TCG_TYPE_I32, ir, data_reg); break; case 3: -#ifdef TCG_TARGET_CALL_ALIGN_ARGS - ir = 5; -#endif + TCG_TARGET_CALL_ALIGN_I64_ARG (ir); tcg_out_mov (s, TCG_TYPE_I32, ir++, data_reg2); tcg_out_mov (s, TCG_TYPE_I32, ir, data_reg); break;
Adjust the tcg_out_qemu_{ld,st}() slow paths to pass AREG0 in r3. Automate the register numbering to avoid double-coding the two modes, and introduce TCG_TARGET_CALL_ALIGN_I64_ARG() macro to align for SVR4 but not for Darwin ABI. Based on patch by malc. Signed-off-by: Andreas Färber <afaerber@suse.de> --- tcg/ppc/tcg-target.c | 48 +++++++++++++++++++++++++++++++++--------------- 1 files changed, 33 insertions(+), 15 deletions(-)