| Message ID | 1334744404-721-1-git-send-email-hechtb@gmail.com |
|---|---|
| State | RFC |
| Headers | show |
2012/4/18 Bastian Hecht <hechtb@googlemail.com>: > When using CONFIG_MTD_NAND_VERIFY_WRITE=y an extra read command is sent > to the NAND chip after writing a page. We need an extra status command > to avoid hick-ups that lead to page write failures. > --- > > Hello all, > > I'm experiencing problems with my current setup and > CONFIG_MTD_NAND_VERIFY_WRITE=y. Usually the command sequence is like > 0x70 Status read > 0x80 0x10 Page prog > 0x70 > 0x80 0x10 Page prog > 0x70 > ... > > When activating write verification there is a read command before the > page prog. I've written this unclearly. I mean if we issue multiple page writes, the page writes are not preceeded by a status read, but by a page read command from the last verification. > 0x80 0x10 > 0x70 > 0x0 read > 0x80 0x10 > 0x70 > ... > This makes my chip write garbage, while the patch fixes it. > Now I wonder if this problem is caused by my NAND chip only, or if this > is a general problem that should be adressed. > --- > drivers/mtd/nand/nand_base.c | 2 ++ > 1 files changed, 2 insertions(+), 0 deletions(-) > > diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c > index 8a393f9..62d6691 100644 > --- a/drivers/mtd/nand/nand_base.c > +++ b/drivers/mtd/nand/nand_base.c > @@ -2101,6 +2101,8 @@ static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, > > if (chip->verify_buf(mtd, buf, mtd->writesize)) > return -EIO; > + > + chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); > #endif > return 0; > } > -- > 1.7.5.4 >
On Wed, 2012-04-18 at 12:25 +0200, Bastian Hecht wrote: > 2012/4/18 Bastian Hecht <hechtb@googlemail.com>: > > When using CONFIG_MTD_NAND_VERIFY_WRITE=y an extra read command is sent > > to the NAND chip after writing a page. We need an extra status command > > to avoid hick-ups that lead to page write failures. > > --- > > > > Hello all, > > > > I'm experiencing problems with my current setup and > > CONFIG_MTD_NAND_VERIFY_WRITE=y. Usually the command sequence is like > > 0x70 Status read > > 0x80 0x10 Page prog > > 0x70 > > 0x80 0x10 Page prog > > 0x70 > > ... > > > > When activating write verification there is a read command before the > > page prog. > > I've written this unclearly. I mean if we issue multiple page writes, > the page writes are not preceeded by a status read, but by a page read > command from the last verification. Looks good to me. Could you send the final patch with final commit message. Probably a small comment in the code is also a good idea.
> Looks good to me. Could you send the final patch with final commit > message. Probably a small comment in the code is also a good idea. Thanks for taking a look at it. I'll post it in a sec. > -- > Best Regards, > Artem Bityutskiy
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 8a393f9..62d6691 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -2101,6 +2101,8 @@ static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, if (chip->verify_buf(mtd, buf, mtd->writesize)) return -EIO; + + chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); #endif return 0; }