| Message ID | DA9F2E38-0A29-4ADE-933E-81692C2E42A9@suse.de |
|---|---|
| State | New |
| Headers | show |
Am 07.02.2012 23:57, schrieb Alexander Graf: > > On 07.02.2012, at 23:29, Brad Smith wrote: > >> On 07/02/12 5:12 PM, malc wrote: >>> On Tue, 7 Feb 2012, Alexander Graf wrote: >>> >>>> >>>> On 07.02.2012, at 22:12, malc wrote: >>>> >>>>> On Tue, 7 Feb 2012, Alexander Graf wrote: >>>>> >>>>>> >>>>>> On 07.02.2012, at 13:52, Maurizio Caloro wrote: >>>>>> >>>>>>> Hello Together >>>>>>> Here i drive with me MiniMac G4 1.4Ghz and i try to run Qemu 1.0. i wan't run one Virt. MS Server2008 it's this realistic?. >>>>>>> >>>>>>> Unfortunitly from the first (other) Mailinglist i don't become any Answer. >>>>>>> >>>>>>> on a possible error recovery support, I would grateful to you. >>>>>>> Thanks and best regards >>>>>>> Mauri >>>>>>> >>>>>>>> NetBSD powermac.G4 5.1 NetBSD 5.1 (GENERIC) #0: Sat Nov 6 17:09:11 UTC>2010 builds@b7.netbsd.org:/home/builds/ab/netbsd-5-1->RELEASE/macppc/201011061943Z-obj/home/builds/ab/netbsd-5-1->RELEASE/src/sys/arch/macppc/compile/GENERIC macppc >>>>>>>> >>>>>>>> # gmake >>>>>>>> CC i386-softmmu/memory.o >>>>>>>> LINK i386-softmmu/qemu-system-i386 >>>>>>>> ld: warning: libintl.so.0, needed by /usr/pkg/lib/libgthread-2.0.so, may conflict with libintl.so.8 >>>>>>>> tcg/tcg.o: In function `tcg_prologue_init': >>>>>>>> /usr/source/qemu-1.0/tcg/tcg.c:268: undefined reference to `flush_icache_range' >>>>>>>> tcg/tcg.o: In function `ppc_tb_set_jmp_target': >>>>>>>> /usr/source/qemu-1.0/tcg/ppc/tcg-target.c:1291: undefined reference to `flush_icache_range' >>>>>>>> tcg/tcg.o: In function `tcg_gen_code': >>>>>>>> /usr/source/qemu-1.0/tcg/tcg.c:2191: undefined reference to `flush_icache_range' >>>>>> >>>>>> I'd say your gcc is too old / buggy. >>>>> >>>>> You probably missed the NetBSD part (anyway originally i did) >>>> >>>> Gcc on NetBSD doesn't implement the cache flush helpers? They're just a >>>> bunch of instructions, so I don't see how that'd be target os specific. >>>> >>> >>> Take a look at cache-utils.c, it conditionally (depending on the host OS >>> type) tries to gigure out the cache line sizes, there's code to do that >>> on Linux, OSX, AIX and FreeBSD. I have no idea if FreeBSD method works >>> for Net/Open/Dragonfly.. so.. >> >> The FreeBSD method will not work with NetBSD. For NetBSD you have to use >> the machdep.cacheinfo sysctl MIB. For OpenBSD this is the only local patch >> we have since there is no sysctl (yet) to retrieve the cache line size. >> DragonFly has no PowerPC support. > > Eh, this patch: > > diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c > index f5d9bf3..f9793e6 100644 > --- a/tcg/ppc/tcg-target.c > +++ b/tcg/ppc/tcg-target.c > @@ -1260,6 +1260,17 @@ static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args, > tcg_out_bc (s, (BC | BI (7, CR_EQ) | BO_COND_TRUE), args[5]); > } > > +#ifdef __NetBSD__ > +static void flush_icache_range(unsigned long begin, unsigned long end) > +{ > + unsigned int i = begin & ~15UL; > + for (; i < end; i+=16) { > + asm("icbi 0,%0" : : "r"(i)); > + } > + asm("isync"); > +} > +#endif > + > void ppc_tb_set_jmp_target (unsigned long jmp_addr, unsigned long addr) > { > uint32_t *ptr; > > Alex > > Hello Alex Yes i think this its running to end.... at the moment it's compiling :-) this pace of Code have you writen?, you are a genius !!! i write you also if this compilation finish. best regards and good night:-)
On 02/07/2012 04:57 PM, Alexander Graf wrote: > > On 07.02.2012, at 23:29, Brad Smith wrote: > >> On 07/02/12 5:12 PM, malc wrote: >>> On Tue, 7 Feb 2012, Alexander Graf wrote: >>> >>>> >>>> On 07.02.2012, at 22:12, malc wrote: >>>> >>>>> On Tue, 7 Feb 2012, Alexander Graf wrote: >>>>> >>>>>> >>>>>> On 07.02.2012, at 13:52, Maurizio Caloro wrote: >>>>>> >>>>>>> Hello Together >>>>>>> Here i drive with me MiniMac G4 1.4Ghz and i try to run Qemu 1.0. i wan't run one Virt. MS Server2008 it's this realistic?. >>>>>>> >>>>>>> Unfortunitly from the first (other) Mailinglist i don't become any Answer. >>>>>>> >>>>>>> on a possible error recovery support, I would grateful to you. >>>>>>> Thanks and best regards >>>>>>> Mauri >>>>>>> >>>>>>>> NetBSD powermac.G4 5.1 NetBSD 5.1 (GENERIC) #0: Sat Nov 6 17:09:11 UTC>2010 builds@b7.netbsd.org:/home/builds/ab/netbsd-5-1->RELEASE/macppc/201011061943Z-obj/home/builds/ab/netbsd-5-1->RELEASE/src/sys/arch/macppc/compile/GENERIC macppc >>>>>>>> >>>>>>>> # gmake >>>>>>>> CC i386-softmmu/memory.o >>>>>>>> LINK i386-softmmu/qemu-system-i386 >>>>>>>> ld: warning: libintl.so.0, needed by /usr/pkg/lib/libgthread-2.0.so, may conflict with libintl.so.8 >>>>>>>> tcg/tcg.o: In function `tcg_prologue_init': >>>>>>>> /usr/source/qemu-1.0/tcg/tcg.c:268: undefined reference to `flush_icache_range' >>>>>>>> tcg/tcg.o: In function `ppc_tb_set_jmp_target': >>>>>>>> /usr/source/qemu-1.0/tcg/ppc/tcg-target.c:1291: undefined reference to `flush_icache_range' >>>>>>>> tcg/tcg.o: In function `tcg_gen_code': >>>>>>>> /usr/source/qemu-1.0/tcg/tcg.c:2191: undefined reference to `flush_icache_range' >>>>>> >>>>>> I'd say your gcc is too old / buggy. >>>>> >>>>> You probably missed the NetBSD part (anyway originally i did) >>>> >>>> Gcc on NetBSD doesn't implement the cache flush helpers? They're just a >>>> bunch of instructions, so I don't see how that'd be target os specific. >>>> >>> >>> Take a look at cache-utils.c, it conditionally (depending on the host OS >>> type) tries to gigure out the cache line sizes, there's code to do that >>> on Linux, OSX, AIX and FreeBSD. I have no idea if FreeBSD method works >>> for Net/Open/Dragonfly.. so.. >> >> The FreeBSD method will not work with NetBSD. For NetBSD you have to use >> the machdep.cacheinfo sysctl MIB. For OpenBSD this is the only local patch >> we have since there is no sysctl (yet) to retrieve the cache line size. >> DragonFly has no PowerPC support. > > Eh, this patch: > > diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c > index f5d9bf3..f9793e6 100644 > --- a/tcg/ppc/tcg-target.c > +++ b/tcg/ppc/tcg-target.c > @@ -1260,6 +1260,17 @@ static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args, > tcg_out_bc (s, (BC | BI (7, CR_EQ) | BO_COND_TRUE), args[5]); > } > > +#ifdef __NetBSD__ > +static void flush_icache_range(unsigned long begin, unsigned long end) > +{ > + unsigned int i = begin & ~15UL; > + for (; i < end; i+=16) { > + asm("icbi 0,%0" : : "r"(i)); > + } > + asm("isync"); > +} > +#endif What about flushing the data cache first, as the other flush_icache_range does? Why isn't the cache-utils.h version of flush_icache_range being seen? It's only ppc_init_cacheline_sizes() that is OS-conditional -- shouldn't that be what the undefined reference is for? Is _ARCH_PPC failing to be defined? -Scott
On 09.02.2012, at 00:29, Scott Wood wrote: > On 02/07/2012 04:57 PM, Alexander Graf wrote: >> >> On 07.02.2012, at 23:29, Brad Smith wrote: >> >>> On 07/02/12 5:12 PM, malc wrote: >>>> On Tue, 7 Feb 2012, Alexander Graf wrote: >>>> >>>>> >>>>> On 07.02.2012, at 22:12, malc wrote: >>>>> >>>>>> On Tue, 7 Feb 2012, Alexander Graf wrote: >>>>>> >>>>>>> >>>>>>> On 07.02.2012, at 13:52, Maurizio Caloro wrote: >>>>>>> >>>>>>>> Hello Together >>>>>>>> Here i drive with me MiniMac G4 1.4Ghz and i try to run Qemu 1.0. i wan't run one Virt. MS Server2008 it's this realistic?. >>>>>>>> >>>>>>>> Unfortunitly from the first (other) Mailinglist i don't become any Answer. >>>>>>>> >>>>>>>> on a possible error recovery support, I would grateful to you. >>>>>>>> Thanks and best regards >>>>>>>> Mauri >>>>>>>> >>>>>>>>> NetBSD powermac.G4 5.1 NetBSD 5.1 (GENERIC) #0: Sat Nov 6 17:09:11 UTC>2010 builds@b7.netbsd.org:/home/builds/ab/netbsd-5-1->RELEASE/macppc/201011061943Z-obj/home/builds/ab/netbsd-5-1->RELEASE/src/sys/arch/macppc/compile/GENERIC macppc >>>>>>>>> >>>>>>>>> # gmake >>>>>>>>> CC i386-softmmu/memory.o >>>>>>>>> LINK i386-softmmu/qemu-system-i386 >>>>>>>>> ld: warning: libintl.so.0, needed by /usr/pkg/lib/libgthread-2.0.so, may conflict with libintl.so.8 >>>>>>>>> tcg/tcg.o: In function `tcg_prologue_init': >>>>>>>>> /usr/source/qemu-1.0/tcg/tcg.c:268: undefined reference to `flush_icache_range' >>>>>>>>> tcg/tcg.o: In function `ppc_tb_set_jmp_target': >>>>>>>>> /usr/source/qemu-1.0/tcg/ppc/tcg-target.c:1291: undefined reference to `flush_icache_range' >>>>>>>>> tcg/tcg.o: In function `tcg_gen_code': >>>>>>>>> /usr/source/qemu-1.0/tcg/tcg.c:2191: undefined reference to `flush_icache_range' >>>>>>> >>>>>>> I'd say your gcc is too old / buggy. >>>>>> >>>>>> You probably missed the NetBSD part (anyway originally i did) >>>>> >>>>> Gcc on NetBSD doesn't implement the cache flush helpers? They're just a >>>>> bunch of instructions, so I don't see how that'd be target os specific. >>>>> >>>> >>>> Take a look at cache-utils.c, it conditionally (depending on the host OS >>>> type) tries to gigure out the cache line sizes, there's code to do that >>>> on Linux, OSX, AIX and FreeBSD. I have no idea if FreeBSD method works >>>> for Net/Open/Dragonfly.. so.. >>> >>> The FreeBSD method will not work with NetBSD. For NetBSD you have to use >>> the machdep.cacheinfo sysctl MIB. For OpenBSD this is the only local patch >>> we have since there is no sysctl (yet) to retrieve the cache line size. >>> DragonFly has no PowerPC support. >> >> Eh, this patch: >> >> diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c >> index f5d9bf3..f9793e6 100644 >> --- a/tcg/ppc/tcg-target.c >> +++ b/tcg/ppc/tcg-target.c >> @@ -1260,6 +1260,17 @@ static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args, >> tcg_out_bc (s, (BC | BI (7, CR_EQ) | BO_COND_TRUE), args[5]); >> } >> >> +#ifdef __NetBSD__ >> +static void flush_icache_range(unsigned long begin, unsigned long end) >> +{ >> + unsigned int i = begin & ~15UL; >> + for (; i < end; i+=16) { >> + asm("icbi 0,%0" : : "r"(i)); >> + } >> + asm("isync"); >> +} >> +#endif > > What about flushing the data cache first, as the other > flush_icache_range does? I actually wrote this one from scratch. Ahem. So why are we flushing the dcache on the other one? Does the icache always fill from memory or can it check if something's in the dcache and fetch it from there? If it's the former, then a dcache flush is crucial, right. > Why isn't the cache-utils.h version of flush_icache_range being seen? > It's only ppc_init_cacheline_sizes() that is OS-conditional -- shouldn't > that be what the undefined reference is for? Is _ARCH_PPC failing to be > defined? Oh, there is a cache flush function already there! Hah! I completely missed out on that one. I would assume it's either because _ARCH_PPC is failing to be picked up (include order?) or because the header file is just not included. My motivation in digging into ppc NetBSD issues is rather small though. Alex
On 02/08/2012 05:42 PM, Alexander Graf wrote: > > On 09.02.2012, at 00:29, Scott Wood wrote: > >> On 02/07/2012 04:57 PM, Alexander Graf wrote: >>> Eh, this patch: >>> >>> diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c >>> index f5d9bf3..f9793e6 100644 >>> --- a/tcg/ppc/tcg-target.c >>> +++ b/tcg/ppc/tcg-target.c >>> @@ -1260,6 +1260,17 @@ static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args, >>> tcg_out_bc (s, (BC | BI (7, CR_EQ) | BO_COND_TRUE), args[5]); >>> } >>> >>> +#ifdef __NetBSD__ >>> +static void flush_icache_range(unsigned long begin, unsigned long end) >>> +{ >>> + unsigned int i = begin & ~15UL; >>> + for (; i < end; i+=16) { >>> + asm("icbi 0,%0" : : "r"(i)); >>> + } >>> + asm("isync"); >>> +} >>> +#endif >> >> What about flushing the data cache first, as the other >> flush_icache_range does? > > I actually wrote this one from scratch. Ahem. > > So why are we flushing the dcache on the other one? Does the icache > always fill from memory or can it check if something's in the dcache > and fetch it from there? If it's the former, then a dcache flush is > crucial, right. The icache is allowed to fill directly from memory, without snooping dcache. Where it actually fetches from and whether it snoops any data cache is implementation-dependent. On our implementations, instruction fetches do not snoop data cache. The fetch could hit in main memory, or in a shared cache such as L3/CPC (e500mc) or L2 (e500v2). >> Why isn't the cache-utils.h version of flush_icache_range being seen? >> It's only ppc_init_cacheline_sizes() that is OS-conditional -- shouldn't >> that be what the undefined reference is for? Is _ARCH_PPC failing to be >> defined? > > Oh, there is a cache flush function already there! Hah! I completely missed out on that one. > > I would assume it's either because _ARCH_PPC is failing to be picked > up (include order?) or because the header file is just not included. > My motivation in digging into ppc NetBSD issues is rather small > though. It looks like GCC sets _ARCH_PPC. Apparently this isn't happening on this user's toolchain. -Scott
On 09.02.2012, at 00:54, Scott Wood wrote: > On 02/08/2012 05:42 PM, Alexander Graf wrote: >> >> On 09.02.2012, at 00:29, Scott Wood wrote: >> >>> On 02/07/2012 04:57 PM, Alexander Graf wrote: >>>> Eh, this patch: >>>> >>>> diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c >>>> index f5d9bf3..f9793e6 100644 >>>> --- a/tcg/ppc/tcg-target.c >>>> +++ b/tcg/ppc/tcg-target.c >>>> @@ -1260,6 +1260,17 @@ static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args, >>>> tcg_out_bc (s, (BC | BI (7, CR_EQ) | BO_COND_TRUE), args[5]); >>>> } >>>> >>>> +#ifdef __NetBSD__ >>>> +static void flush_icache_range(unsigned long begin, unsigned long end) >>>> +{ >>>> + unsigned int i = begin & ~15UL; >>>> + for (; i < end; i+=16) { >>>> + asm("icbi 0,%0" : : "r"(i)); >>>> + } >>>> + asm("isync"); >>>> +} >>>> +#endif >>> >>> What about flushing the data cache first, as the other >>> flush_icache_range does? >> >> I actually wrote this one from scratch. Ahem. >> >> So why are we flushing the dcache on the other one? Does the icache >> always fill from memory or can it check if something's in the dcache >> and fetch it from there? If it's the former, then a dcache flush is >> crucial, right. > > The icache is allowed to fill directly from memory, without snooping > dcache. Where it actually fetches from and whether it snoops any data > cache is implementation-dependent. On our implementations, instruction > fetches do not snoop data cache. The fetch could hit in main memory, or > in a shared cache such as L3/CPC (e500mc) or L2 (e500v2). I see. Then the implementation we have seems to do the right thing ;). > >>> Why isn't the cache-utils.h version of flush_icache_range being seen? >>> It's only ppc_init_cacheline_sizes() that is OS-conditional -- shouldn't >>> that be what the undefined reference is for? Is _ARCH_PPC failing to be >>> defined? >> >> Oh, there is a cache flush function already there! Hah! I completely missed out on that one. >> >> I would assume it's either because _ARCH_PPC is failing to be picked >> up (include order?) or because the header file is just not included. >> My motivation in digging into ppc NetBSD issues is rather small >> though. > > It looks like GCC sets _ARCH_PPC. Apparently this isn't happening on > this user's toolchain. Broken NetBSD again :). I don't think we have to worry too much about it for now. As long as this is documented on the mailing list (which it is now) someone who cares about NetBSD can either a) fix their toolchain or b) add a patch to match on something different and then the 2 other people on this planet running NetBSD PPC will be happy :) Alex
diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c index f5d9bf3..f9793e6 100644 --- a/tcg/ppc/tcg-target.c +++ b/tcg/ppc/tcg-target.c @@ -1260,6 +1260,17 @@ static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args, tcg_out_bc (s, (BC | BI (7, CR_EQ) | BO_COND_TRUE), args[5]); } +#ifdef __NetBSD__ +static void flush_icache_range(unsigned long begin, unsigned long end) +{ + unsigned int i = begin & ~15UL; + for (; i < end; i+=16) { + asm("icbi 0,%0" : : "r"(i)); + } + asm("isync"); +} +#endif + void ppc_tb_set_jmp_target (unsigned long jmp_addr, unsigned long addr) { uint32_t *ptr;