| Message ID | 1328620611-24108-5-git-send-email-robert@delien.nl |
|---|---|
| State | Superseded |
| Delegated to: | Stefano Babic |
| Headers | show |
> From: Robert Delien <robert@delien.nl> > > This patch prevents the needless switching on and off of PLL bypass > mode. With this patch in place, single-stepping through the SPL is > now possible. Why did FSL have it in the bootlets though? Fabio, can you explain? M > > Signed-off-by: Robert Delien <robert@delien.nl> > --- > arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c | 4 ---- > arch/arm/cpu/arm926ejs/mx28/spl_power_init.c | 24 > ------------------------ 2 files changed, 0 insertions(+), 28 deletions(-) > > diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c > b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c index f2fab7c..cf4361c 100644 > --- a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c > +++ b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c > @@ -121,10 +121,6 @@ void mx28_mem_setup_cpu_and_hbus(void) > writeb(19 & CLKCTRL_FRAC_FRAC_MASK, > (uint8_t *)&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]); > > - /* Set CPU bypass */ > - writel(CLKCTRL_CLKSEQ_BYPASS_CPU, > - &clkctrl_regs->hw_clkctrl_clkseq_set); > - > /* HBUS = 151MHz */ > writel(CLKCTRL_HBUS_DIV_MASK, &clkctrl_regs->hw_clkctrl_hbus_set); > writel(((~3) << CLKCTRL_HBUS_DIV_OFFSET) & CLKCTRL_HBUS_DIV_MASK, > diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c > b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c index 380b120..5e21a1e > 100644 > --- a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c > +++ b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c > @@ -30,28 +30,6 @@ > > #include "mx28_init.h" > > -void mx28_power_clock2xtal(void) > -{ > - struct mx28_clkctrl_regs *clkctrl_regs = > - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; > - > - /* Set XTAL as CPU reference clock */ > - writel(CLKCTRL_CLKSEQ_BYPASS_CPU, > - &clkctrl_regs->hw_clkctrl_clkseq_set); > -} > - > -void mx28_power_clock2pll(void) > -{ > - struct mx28_clkctrl_regs *clkctrl_regs = > - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; > - > - writel(CLKCTRL_PLL0CTRL0_POWER, > - &clkctrl_regs->hw_clkctrl_pll0ctrl0_set); > - early_delay(100); > - writel(CLKCTRL_CLKSEQ_BYPASS_CPU, > - &clkctrl_regs->hw_clkctrl_clkseq_clr); > -} > - > void mx28_power_clear_auto_restart(void) > { > struct mx28_rtc_regs *rtc_regs = > @@ -606,7 +584,6 @@ void mx28_power_configure_power_source(void) > mx28_src_power_init(); > > mx28_5v_boot(); > - mx28_power_clock2pll(); > > mx28_init_batt_bo(); > mx28_switch_vddd_to_dcdc_source(); > @@ -880,7 +857,6 @@ void mx28_power_init(void) > struct mx28_power_regs *power_regs = > (struct mx28_power_regs *)MXS_POWER_BASE; > > - mx28_power_clock2xtal(); > mx28_power_clear_auto_restart(); > mx28_power_set_linreg(); > mx28_power_setup_5v_detect();
On Tue, Feb 7, 2012 at 2:53 PM, Marek Vasut <marek.vasut@gmail.com> wrote: >> From: Robert Delien <robert@delien.nl> >> >> This patch prevents the needless switching on and off of PLL bypass >> mode. With this patch in place, single-stepping through the SPL is >> now possible. > > Why did FSL have it in the bootlets though? Fabio, can you explain? Let me ask around and see what I can find about it. Regards, Fabio Estevam
Hi Marek, On Tue, Feb 7, 2012 at 2:53 PM, Marek Vasut <marek.vasut@gmail.com> wrote: >> From: Robert Delien <robert@delien.nl> >> >> This patch prevents the needless switching on and off of PLL bypass >> mode. With this patch in place, single-stepping through the SPL is >> now possible. > > Why did FSL have it in the bootlets though? Fabio, can you explain? Anson (in Cc) explained the following: "The switch of CPU clock is to make our EVK board can boot up the uboot and kernel with less than 100mA power consumption to meet the USB specification, because there is chance that the EVK board is power by USB cable only, we need to make sure in this scenario, before USB enum done, the total power consumption for our EVK board should be less than 100mA, but if CPU running with PLL on, the power consumption is > 100mA under uboot, so we need to disable PLL and switch CPU clock to XTAL before USB enum done." Regards, Fabio Estevam
> Hi Marek, > > On Tue, Feb 7, 2012 at 2:53 PM, Marek Vasut <marek.vasut@gmail.com> wrote: > >> From: Robert Delien <robert@delien.nl> > >> > >> This patch prevents the needless switching on and off of PLL bypass > >> mode. With this patch in place, single-stepping through the SPL is > >> now possible. > > > > Why did FSL have it in the bootlets though? Fabio, can you explain? > > Anson (in Cc) explained the following: > > "The switch of CPU clock is to make our EVK board can boot up the > uboot and kernel with less than 100mA power consumption to meet the > USB specification, because there is chance that the EVK board is power > by USB cable only, we need to make sure in this scenario, before USB > enum done, the total power consumption for our EVK board should be > less than 100mA, but if CPU running with PLL on, the power consumption > is > 100mA under uboot, so we need to disable PLL and switch CPU clock > to XTAL before USB enum done." > And by running off XTAL, the consumption grows so dramatically? M
> That is because not only CPU running @ PLL, HBUS also source from P_CLK, we > switch CPU clock to XTAL, the HBUS clock also slow down. Ok, but you switch it back to PLL after the power supply was configured. And then the consumption grows back. M > > Best Regards. > Anson huang 黄勇才 > > Freescale Semiconductor Shanghai > 上海浦东新区亮景路192号C座2楼 > 201203 > Tel:021-28937058 > > $-----Original Message----- > $From: Marek Vasut [mailto:marek.vasut@gmail.com] > $Sent: Wednesday, February 08, 2012 10:43 AM > $To: Fabio Estevam > $Cc: Huang Yongcai-B20788; robert@delien.nl; u-boot@lists.denx.de > $Subject: Re: [PATCH 4/4 v4] Preventing needless switching on and off PLL > bypass $mode, allowing allow single-stepping through the SPL > $ > $> Hi Marek, > $> > $> On Tue, Feb 7, 2012 at 2:53 PM, Marek Vasut <marek.vasut@gmail.com> > wrote: $> >> From: Robert Delien <robert@delien.nl> > $> >> > $> >> This patch prevents the needless switching on and off of PLL bypass > $> >> mode. With this patch in place, single-stepping through the SPL is > $> >> now possible. > $> > > $> > Why did FSL have it in the bootlets though? Fabio, can you explain? > $> > $> Anson (in Cc) explained the following: > $> > $> "The switch of CPU clock is to make our EVK board can boot up the > $> uboot and kernel with less than 100mA power consumption to meet the > $> USB specification, because there is chance that the EVK board is power > $> by USB cable only, we need to make sure in this scenario, before USB > $> enum done, the total power consumption for our EVK board should be > $> less than 100mA, but if CPU running with PLL on, the power consumption > $> is > 100mA under uboot, so we need to disable PLL and switch CPU clock > $> to XTAL before USB enum done." > $> > $ > $And by running off XTAL, the consumption grows so dramatically? > $ > $M
> "The switch of CPU clock is to make our EVK board can boot up the > uboot and kernel with less than 100mA power consumption to meet the > USB specification That's actually a very good point. For that scenario we may even consider to use the SoC's internal 24MHz ring oscillator instead of the crystal. But this also means that we should disable bypass mode either a whole lot later, or make it depend on CONFIG_USB.
> And by running off XTAL, the consumption grows so dramatically?
No, switching on the PLL does.
And the PLL can use either the external XTAL or the internal ring-
oscillator as a reference. The external XTAL is very accurate, but
uses power. The ring-oscillator is not very accurate, but very
energy efficient.
On the EVK, the external XTAL cannot be powered down
separately, so if it's consuming power anyway, there\s not reason
not to use it over the ring-oscillator. But a more generic design
may want use ring-oscillator initially.
> That is because not only CPU running @ PLL, HBUS also source from P_CLK, we switch > CPU clock to XTAL, the HBUS clock also slow down. You're right, but I'm not switching back to XTAL. I'm just postponing the switch to PLL. Not in the last reason because the first switch to PLL is incorrect (and shouldn't even work).
> Ok, but you switch it back to PLL after the power supply was configured. And > then the consumption grows back. Yes, power_init switches to PLL (yet incorrectly). And memory_init switches back to XTAL when configuring hbus for a brief moment, to switch to PLL after hbus is configured. My proposal is to leave out the incorrect first switch, and leave it on XTAL until hbus is configured. Thhough is still doesn't take care the <100mA requirement mentioned by Fabio...
> 1. Switch P_CLK to XTAL; > 2. Check power source, if there is battery available, we switch back to PLL and make CPU running @ full > speed, and power is sourced from battery; > 3. If battery is not available, and the power supply is from USB host, then we let CPU running @ XTAL > until booting up kernel and USB driver enum done, then switch to PLL. I fully agree.
diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c index f2fab7c..cf4361c 100644 --- a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c @@ -121,10 +121,6 @@ void mx28_mem_setup_cpu_and_hbus(void) writeb(19 & CLKCTRL_FRAC_FRAC_MASK, (uint8_t *)&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]); - /* Set CPU bypass */ - writel(CLKCTRL_CLKSEQ_BYPASS_CPU, - &clkctrl_regs->hw_clkctrl_clkseq_set); - /* HBUS = 151MHz */ writel(CLKCTRL_HBUS_DIV_MASK, &clkctrl_regs->hw_clkctrl_hbus_set); writel(((~3) << CLKCTRL_HBUS_DIV_OFFSET) & CLKCTRL_HBUS_DIV_MASK, diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c index 380b120..5e21a1e 100644 --- a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c @@ -30,28 +30,6 @@ #include "mx28_init.h" -void mx28_power_clock2xtal(void) -{ - struct mx28_clkctrl_regs *clkctrl_regs = - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; - - /* Set XTAL as CPU reference clock */ - writel(CLKCTRL_CLKSEQ_BYPASS_CPU, - &clkctrl_regs->hw_clkctrl_clkseq_set); -} - -void mx28_power_clock2pll(void) -{ - struct mx28_clkctrl_regs *clkctrl_regs = - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; - - writel(CLKCTRL_PLL0CTRL0_POWER, - &clkctrl_regs->hw_clkctrl_pll0ctrl0_set); - early_delay(100); - writel(CLKCTRL_CLKSEQ_BYPASS_CPU, - &clkctrl_regs->hw_clkctrl_clkseq_clr); -} - void mx28_power_clear_auto_restart(void) { struct mx28_rtc_regs *rtc_regs = @@ -606,7 +584,6 @@ void mx28_power_configure_power_source(void) mx28_src_power_init(); mx28_5v_boot(); - mx28_power_clock2pll(); mx28_init_batt_bo(); mx28_switch_vddd_to_dcdc_source(); @@ -880,7 +857,6 @@ void mx28_power_init(void) struct mx28_power_regs *power_regs = (struct mx28_power_regs *)MXS_POWER_BASE; - mx28_power_clock2xtal(); mx28_power_clear_auto_restart(); mx28_power_set_linreg(); mx28_power_setup_5v_detect();