Message ID | OF347B7A99.72C78074-ONC2257980.0037156D-C2257981.0039C970@il.ibm.com |
---|---|
State | New |
Headers | show |
On Tue, Jan 10, 2012 at 12:31 PM, Revital1 Eres <ERES@il.ibm.com> wrote: > > Hello, > > The patch below fixes ICE reported in PR51794. > It avoids creating DDG edges for register uses of class DF_REF_ARTIFICIAL > as > the latter does not have real instructions for them and thus calling > BLOCK_FOR_INSN fails. > > Tested and bootstrap on ppc64-redhat-linux, enabling SMS on loops with SC > 1. > > OK for mainline? > Yes, this is ok. Thanks, Ayal. > Thanks, > Revital > > Chanelog: > > PR rtl-optimization/51794 > * ddg.c (add_cross_iteration_register_deps): Avoid > creating edges for uses of class DF_REF_ARTIFICIAL. > > testsuite/ > PR rtl-optimization/51794 > * gcc.dg/sms-12.c: New test. > > (See attached file: patch_fix_pr51794.txt)
Index: ddg.c =================================================================== --- ddg.c (revision 183001) +++ ddg.c (working copy) @@ -315,7 +315,12 @@ add_cross_iteration_register_deps (ddg_p /* Create inter-loop true dependences and anti dependences. */ for (r_use = DF_REF_CHAIN (last_def); r_use != NULL; r_use = r_use->next) { - rtx use_insn = DF_REF_INSN (r_use->ref); + rtx use_insn; + + if (r_use->ref == NULL || DF_REF_CLASS (r_use->ref) == DF_REF_ARTIFICIAL) + continue; + + use_insn = DF_REF_INSN (r_use->ref); if (BLOCK_FOR_INSN (use_insn) != g->bb) continue; Index: testsuite/gcc.dg/sms-12.c =================================================================== --- testsuite/gcc.dg/sms-12.c (revision 0) +++ testsuite/gcc.dg/sms-12.c (revision 0) @@ -0,0 +1,13 @@ + /* { dg-do compile } */ + /* { dg-options "-O -fmodulo-sched" } */ + + +int +res_inverse (int a) +{ + int i; + char **b = (char **) __builtin_alloca (a * sizeof (char *)); + for (i = 0; i < a; i++) + b[i] = (char *) __builtin_alloca (sizeof (*b[i])); + return 0; +}