@@ -21,6 +21,9 @@ config ARM_VIC_NR
The maximum number of VICs available in the system, for
power management.
+config ARM_NVIC
+ bool
+
config ICST
bool
@@ -4,6 +4,7 @@
obj-$(CONFIG_ARM_GIC) += gic.o
obj-$(CONFIG_ARM_VIC) += vic.o
+obj-$(CONFIG_ARM_NVIC) += nvic.o
obj-$(CONFIG_ICST) += icst.o
obj-$(CONFIG_PL330) += pl330.o
obj-$(CONFIG_SA1111) += sa1111.o
new file mode 100644
@@ -0,0 +1,98 @@
+/*
+ * linux/arch/arm/common/nvic.c
+ *
+ * Copyright (C) 2008 ARM Limited, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Support for the Nested Vectored Interrupt Controller found on the
+ * ARMv7-M CPUs (Cortex-M3)
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/smp.h>
+
+#include <asm/irq.h>
+#include <asm/io.h>
+#include <asm/mach/irq.h>
+#include <asm/hardware/nvic.h>
+
+static DEFINE_RAW_SPINLOCK(irq_controller_lock);
+
+/*
+ * Routines to acknowledge, disable and enable interrupts
+ *
+ * Linux assumes that when we're done with an interrupt we need to
+ * unmask it, in the same way we need to unmask an interrupt when
+ * we first enable it.
+ *
+ * The NVIC has a separate notion of "end of interrupt" to re-enable
+ * an interrupt after handling, in order to support hardware
+ * prioritisation.
+ *
+ * We can make the NVIC behave in the way that Linux expects by making
+ * our "acknowledge" routine disable the interrupt, then mark it as
+ * complete.
+ */
+static void nvic_ack_irq(struct irq_data *d)
+{
+ u32 mask = 1 << (d->irq % 32);
+
+ raw_spin_lock(&irq_controller_lock);
+ writel(mask, NVIC_CLEAR_ENABLE + d->irq / 32 * 4);
+ raw_spin_unlock(&irq_controller_lock);
+}
+
+static void nvic_mask_irq(struct irq_data *d)
+{
+ u32 mask = 1 << (d->irq % 32);
+
+ raw_spin_lock(&irq_controller_lock);
+ writel(mask, NVIC_CLEAR_ENABLE + d->irq / 32 * 4);
+ raw_spin_unlock(&irq_controller_lock);
+}
+
+static void nvic_unmask_irq(struct irq_data *d)
+{
+ u32 mask = 1 << (d->irq % 32);
+
+ raw_spin_lock(&irq_controller_lock);
+ writel(mask, NVIC_SET_ENABLE + d->irq / 32 * 4);
+ raw_spin_unlock(&irq_controller_lock);
+}
+
+static struct irq_chip nvic_chip = {
+ .name = "NVIC",
+ .irq_ack = nvic_ack_irq,
+ .irq_mask = nvic_mask_irq,
+ .irq_unmask = nvic_unmask_irq,
+};
+
+void __init nvic_init(void)
+{
+ unsigned int max_irq, i;
+
+ max_irq = ((readl(NVIC_INTR_CTRL) & 0x1f) + 1) * 32;
+
+ /*
+ * Disable all interrupts
+ */
+ for (i = 0; i < max_irq / 32; i++)
+ writel(~0, NVIC_CLEAR_ENABLE + i * 4);
+
+ /*
+ * Set priority on all interrupts.
+ */
+ for (i = 0; i < max_irq; i += 4)
+ writel(0, NVIC_PRIORITY + i);
+
+ /*
+ * Setup the Linux IRQ subsystem.
+ */
+ for (i = 0; i < NR_IRQS; i++) {
+ irq_set_chip_and_handler(i, &nvic_chip, handle_level_irq);
+ set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
+ }
+}
new file mode 100644
@@ -0,0 +1,34 @@
+/*
+ * linux/include/asm-arm/hardware/nvic.h
+ *
+ * Copyright (C) 2008 ARM Limited, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARM_HARDWARE_NVIC_H
+#define __ASM_ARM_HARDWARE_NVIC_H
+
+#include <linux/compiler.h>
+
+#define V7M_SCS 0xe000e000
+#define NVIC_INTR_CTRL (V7M_SCS + 0x004)
+#define NVIC_SYSTICK_CTRL (V7M_SCS + 0x010)
+#define NVIC_SYSTICK_RELOAD (V7M_SCS + 0x014)
+#define NVIC_SYSTICK_CURRENT (V7M_SCS + 0x018)
+#define NVIC_SYSTICK_CALIBRATION (V7M_SCS + 0x01c)
+#define NVIC_SET_ENABLE (V7M_SCS + 0x100)
+#define NVIC_CLEAR_ENABLE (V7M_SCS + 0x180)
+#define NVIC_SET_PENDING (V7M_SCS + 0x200)
+#define NVIC_CLEAR_PENDING (V7M_SCS + 0x280)
+#define NVIC_ACTIVE_BIT (V7M_SCS + 0x300)
+#define NVIC_PRIORITY (V7M_SCS + 0x400)
+#define NVIC_INTR_CTRL_STATE (V7M_SCS + 0xd04)
+#define NVIC_SOFTWARE_INTR (V7M_SCS + 0xf00)
+
+#ifndef __ASSEMBLY__
+void nvic_init(void);
+#endif
+
+#endif