diff mbox

[U-Boot,3/4] arm, omap3: Add support for TechNexion modules

Message ID 20111121164800.23d1025f@myhost
State Superseded
Delegated to: Tom Rini
Headers show

Commit Message

Tapani Utriainen Nov. 21, 2011, 8:48 a.m. UTC 
Add support for TechNexion TAO3530 SoM

Signed-off-by: Tapani Utriainen <tapani@technexion.com>
CC: Sandeep Paulraj <s-paulraj@ti.com>
---
 arch/arm/include/asm/mach-types.h  |    1 
 board/technexion/tao3530/Makefile  |   43 ++++
 board/technexion/tao3530/tao3530.c |  207 ++++++++++++++++++++
 board/technexion/tao3530/tao3530.h |  382 +++++++++++++++++++++++++++++++++++++
 boards.cfg                         |    1 
 include/configs/tao3530.h          |  362 +++++++++++++++++++++++++++++++++++
 6 files changed, 996 insertions(+)


--
1.7.6

Comments

Wolfgang Denk Nov. 21, 2011, 9:49 a.m. UTC | #1 
Dear Tapani Utriainen,

In message <20111121164800.23d1025f@myhost> you wrote:
> 
> Add support for TechNexion TAO3530 SoM

Same comments as for previous module.

Also again: please chose a beter Subject: line.

...
> +	/* Set memory size environment variable, depending on revision */
> +	switch (tao3530_revision()) {
> +	case 0x2:  /* Rev C1 -- 256MB */
> +		 setenv("mem_size", "mem=256M");
> +		 break;
> +	default:
> +		 printf("Warning: Unknown TAO3530 rev, setting mem=128M\n");
> +	case 0x3: /* Rev A2/B2 -- 128MB */
> +		 setenv("mem_size", "mem=128M"); break;
> +		 break;

Please don't hard-wire memory sizes.  Use get_ram_size() to
auto-detect the actual size on the module.

...
> +	/* Make GPIO 142 as output pin */
> +	writel(readl(&gpio5_base->oe) & ~(GPIO14), &gpio5_base->oe);
> +
> +	/* Now send a pulse on the GPIO pin */

Please add comments why actions like these are needed / what they are
good for.


Best regards,

Wolfgang Denk
Stefano Babic Nov. 21, 2011, 10:17 a.m. UTC | #2 
On 21/11/2011 09:48, Tapani Utriainen wrote:
> 
> Add support for TechNexion TAO3530 SoM
> 
> Signed-off-by: Tapani Utriainen <tapani@technexion.com>
> CC: Sandeep Paulraj <s-paulraj@ti.com>
> ---

Hi Tapani,

>  arch/arm/include/asm/mach-types.h  |    1 
>  board/technexion/tao3530/Makefile  |   43 ++++
>  board/technexion/tao3530/tao3530.c |  207 ++++++++++++++++++++
>  board/technexion/tao3530/tao3530.h |  382 +++++++++++++++++++++++++++++++++++++
>  boards.cfg                         |    1 
>  include/configs/tao3530.h          |  362 +++++++++++++++++++++++++++++++++++
>  6 files changed, 996 insertions(+)
> 

Most my comments from TAM3517 are still valid for this module. I post
here only new comments ;-)

I think you have already got the comment, but you should better explain
in the commit message what the patch does. This patch is different from
the TAM3517 patch, but both share the same commit message.

> diff --git a/board/technexion/tao3530/Makefile b/board/technexion/tao3530/Makefile
> new file mode 100644
> index 0000000..59c7d4f
> --- /dev/null
> +++ b/board/technexion/tao3530/Makefile
> @@ -0,0 +1,43 @@
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.

Author, Copyright ?


> diff --git a/board/technexion/tao3530/tao3530.c b/board/technexion/tao3530/tao3530.c
> new file mode 100644
> index 0000000..b8a4ac8
> --- /dev/null
> +++ b/board/technexion/tao3530/tao3530.c
> @@ -0,0 +1,207 @@
> +/*
> + * Maintainer :
> + *      Tapani Utriainen <linuxfae@technexion.com>
> + *

The correct and used way is to set author and copyright in the header
file, and put the maintainer name in the MAINTAINER file.

> +/*
> + * Routine: misc_init_r
> + * Description: Configure board specific parts
> + */
> +int misc_init_r(void)
> +{
> +	struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
> +	struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
> +
> +	twl4030_power_init();
> +	twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
> +
> +
> +	/* Configure GPIOs to output */
> +	/* GPIO23 */
> +	writel(~(GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe);
> +	writel(~(GPIO31 | GPIO30 | GPIO22 | GPIO21 |
> +		 GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe);

You have already used the GPIO framework - why do you write directly the
registers ?

This should be fixed globally.

> +
> +	/* Set GPIOs */
> +	writel(GPIO10 | GPIO8 | GPIO2 | GPIO1,
> +		&gpio6_base->setdataout);
> +	writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
> +		GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout);
> +
> +#if defined(CONFIG_CMD_NET)
> +	setup_net_chip();
> +#endif
> +	dieid_num_r();
> +
> +	/* Set memory size environment variable, depending on revision */
> +	switch (tao3530_revision()) {
> +	case 0x2:  /* Rev C1 -- 256MB */
> +		 setenv("mem_size", "mem=256M");

mmmhh...memory is computed with get_ram_size(), not on the revision number.

best regards,
Stefano Babic
diff mbox

Patch

diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h
index 685b46f..d900d94 100644
--- a/arch/arm/include/asm/mach-types.h
+++ b/arch/arm/include/asm/mach-types.h
@@ -472,6 +472,7 @@  extern unsigned int __machine_arch_type;
 #define MACH_TYPE_EUKREA_CPUIMX35SD    2821
 #define MACH_TYPE_EUKREA_CPUIMX51SD    2822
 #define MACH_TYPE_EUKREA_CPUIMX51      2823
+#define MACH_TYPE_OMAP3_TAO3530        2836
 #define MACH_TYPE_SMDKC210             2838
 #define MACH_TYPE_OMAP3_BRAILLO        2839
 #define MACH_TYPE_SPYPLUG              2840
diff --git a/board/technexion/tao3530/Makefile b/board/technexion/tao3530/Makefile
new file mode 100644
index 0000000..59c7d4f
--- /dev/null
+++ b/board/technexion/tao3530/Makefile
@@ -0,0 +1,43 @@ 
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= tao3530.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/technexion/tao3530/tao3530.c b/board/technexion/tao3530/tao3530.c
new file mode 100644
index 0000000..b8a4ac8
--- /dev/null
+++ b/board/technexion/tao3530/tao3530.c
@@ -0,0 +1,207 @@ 
+/*
+ * Maintainer :
+ *      Tapani Utriainen <linuxfae@technexion.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <netdev.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
+#include <asm/mach-types.h>
+#include "tao3530.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int tao3530_revision(void)
+{
+	int ret = 0;
+
+	/* char *label argument is unused in gpio_request() */
+	ret = gpio_request(65, "");
+	if (ret) {
+		printf("Error? GPIO 65 not available\n");
+		goto out;
+	}
+	MUX_VAL(CP(GPMC_WAIT3),	(IEN  | PTU | EN  | M4));
+
+	ret = gpio_request(1, "");
+	if (ret) {
+		printf("Error? GPIO 1 not available\n");
+		goto out2;
+	}
+	MUX_VAL(CP(SYS_CLKREQ), (IEN  | PTU | EN | M4));
+
+	ret = gpio_direction_input(65);
+	if (ret) {
+		printf("Error? GPIO 65 not available for input\n");
+		goto out3;
+	}
+
+	ret =  gpio_direction_input(1);
+	if (ret) {
+		printf("Error? GPIO 1 not available for input\n");
+		goto out3;
+	}
+
+	ret = gpio_get_value(65) << 1 | gpio_get_value(1);
+
+out3:
+	MUX_VAL(CP(SYS_CLKREQ), (IEN  | PTU | EN | M0));
+	gpio_free(1);
+out2:
+	MUX_VAL(CP(GPMC_WAIT3),	(IEN  | PTU | EN  | M0));
+	gpio_free(65);
+out:
+
+	return ret;
+}
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+	/* board id for Linux */
+	gd->bd->bi_arch_number = MACH_TYPE_OMAP3_TAO3530;
+	/* boot param addr */
+	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+	return 0;
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+int misc_init_r(void)
+{
+	struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
+	struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
+
+	twl4030_power_init();
+	twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
+
+
+	/* Configure GPIOs to output */
+	/* GPIO23 */
+	writel(~(GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe);
+	writel(~(GPIO31 | GPIO30 | GPIO22 | GPIO21 |
+		 GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe);
+
+	/* Set GPIOs */
+	writel(GPIO10 | GPIO8 | GPIO2 | GPIO1,
+		&gpio6_base->setdataout);
+	writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
+		GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout);
+
+#if defined(CONFIG_CMD_NET)
+	setup_net_chip();
+#endif
+	dieid_num_r();
+
+	/* Set memory size environment variable, depending on revision */
+	switch (tao3530_revision()) {
+	case 0x2:  /* Rev C1 -- 256MB */
+		 setenv("mem_size", "mem=256M");
+		 break;
+	default:
+		 printf("Warning: Unknown TAO3530 rev, setting mem=128M\n");
+	case 0x3: /* Rev A2/B2 -- 128MB */
+		 setenv("mem_size", "mem=128M"); break;
+		 break;
+	}
+	return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ *		hardware. Many pins need to be moved from protect to primary
+ *		mode.
+ */
+void set_muxconf_regs(void)
+{
+	MUX_TAO3530();
+}
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+	omap_mmc_init(0);
+	return 0;
+}
+#endif
+
+/*
+ * Routine: setup_net_chip
+ * Description: Setting up the configuration GPMC registers specific to the
+ *		Ethernet hardware.
+ */
+static void setup_net_chip(void)
+{
+	struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
+	struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
+
+	/* GPIO 1 is low on rev C1, high on A, B */
+
+	/* Configure GPMC registers */
+	writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1);
+	writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2);
+	writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3);
+	writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4);
+	writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5);
+	writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6);
+	writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7);
+
+	/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
+	writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
+	/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
+	writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
+	/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
+	writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
+		&ctrl_base->gpmc_nadv_ale);
+
+	/* Make GPIO 142 as output pin */
+	writel(readl(&gpio5_base->oe) & ~(GPIO14), &gpio5_base->oe);
+
+	/* Now send a pulse on the GPIO pin */
+	writel(GPIO14, &gpio5_base->setdataout);
+	udelay(1);
+	writel(GPIO14, &gpio5_base->cleardataout);
+	udelay(1);
+	writel(GPIO14, &gpio5_base->setdataout);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC911X
+	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+	return rc;
+}
diff --git a/board/technexion/tao3530/tao3530.h b/board/technexion/tao3530/tao3530.h
new file mode 100644
index 0000000..2ce34d8
--- /dev/null
+++ b/board/technexion/tao3530/tao3530.h
@@ -0,0 +1,382 @@ 
+/*
+ * (C) Copyright TechNexion 2010
+ * Edward Lin <linuxfae@technexion.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _TAO3530_H_
+#define _TAO3530_H_
+
+const omap3_sysinfo sysinfo = {
+	DDR_STACKED,
+	"OMAP3 TAO-3530 board",
+	"NAND",
+};
+
+static void setup_net_chip(void);
+
+/*
+ * IEN  - Input Enable
+ * IDIS - Input Disable
+ * PTD  - Pull type Down
+ * PTU  - Pull type Up
+ * DIS  - Pull type selection is inactive
+ * EN   - Pull type selection is active
+ * M0   - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_TAO3530() \
+ /*SDRC*/\
+	MUX_VAL(CP(SDRC_D0),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D1),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D3),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D4),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D5),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D6),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D7),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D8),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D9),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D10),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D11),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D12),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D13),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D14),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D15),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D16),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D17),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D18),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D19),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D20),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D21),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D22),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D23),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D24),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D25),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D26),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D27),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D28),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D29),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D30),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D31),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_CLK),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS0),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS1),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS3),	(IEN  | PTD | DIS | M0)) \
+ /*GPMC*/\
+	MUX_VAL(CP(GPMC_A1),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A2),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A3),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A4),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A5),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A6),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A7),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A8),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A9),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A10),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D0),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D1),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D2),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D3),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D4),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D5),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D6),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D7),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D8),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D9),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D10),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D11),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D12),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D13),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D14),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D15),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS0),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS1),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS2),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS3),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS4),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS5),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS6),	(IEN  | PTD | EN | M0)) \
+	MUX_VAL(CP(GPMC_NCS7),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_CLK),	(IDIS | PTU | EN | M0)) \
+	MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(GPMC_NOE),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(GPMC_NWE),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \
+	MUX_VAL(CP(GPMC_NBE1),	(IEN  | PTU | EN | M0)) \
+	MUX_VAL(CP(GPMC_NWP),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(GPMC_WAIT0),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_WAIT1),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_WAIT2),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_WAIT3),	(IEN  | PTU | EN  | M0)) \
+ /*DSS*/\
+	MUX_VAL(CP(DSS_PCLK),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_HSYNC),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_VSYNC),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_ACBIAS),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA0),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA1),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA2),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA3),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA4),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA5),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA6),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA7),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA8),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA9),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA10),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA11),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA12),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA13),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA14),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA15),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA16),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA17),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA18),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA19),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA20),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA21),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA22),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA23),	(IDIS | PTD | DIS | M0)) \
+ /*CAMERA*/\
+	MUX_VAL(CP(CAM_HS),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CAM_VS),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CAM_XCLKA),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_PCLK),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CAM_FLD),	(IDIS | PTD | DIS | M4)) \
+ /* - CAM_RESET*/\
+	MUX_VAL(CP(CAM_D0),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D1),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D3),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D4),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D5),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D6),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D7),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D8),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D9),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D10),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D11),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_XCLKB),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_WEN),	(IEN  | PTD | DIS | M4)) \
+	MUX_VAL(CP(CAM_STROBE),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(CSI2_DX0),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CSI2_DY0),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CSI2_DX1),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CSI2_DY1),	(IEN  | PTD | DIS | M0)) \
+ /*Audio Interface */\
+	MUX_VAL(CP(MCBSP2_FSX),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP2_CLKX), (IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP2_DR),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP2_DX),	(IDIS | PTD | DIS | M0)) \
+ /*Expansion card */\
+	MUX_VAL(CP(MMC1_CLK),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(MMC1_CMD),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(MMC1_DAT0),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(MMC1_DAT1),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(MMC1_DAT2),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(MMC1_DAT3),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(MMC1_DAT4),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(MMC1_DAT5),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(MMC1_DAT6),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(MMC1_DAT7),	(IEN  | PTU | EN  | M0)) \
+ /* MMC2 WLAN */\
+	MUX_VAL(CP(MMC2_CLK),	(IEN  | PTD | DIS  | M0)) \
+	MUX_VAL(CP(MMC2_CMD),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(MMC2_DAT0),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(MMC2_DAT1),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(MMC2_DAT2),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(MMC2_DAT3),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(MMC2_DAT4),	(IEN  | PTU | EN  | M4)) \
+	MUX_VAL(CP(MMC2_DAT5),	(IEN  | PTU | EN  | M4)) \
+	MUX_VAL(CP(MMC2_DAT6),	(IDIS  | PTD | EN  | M4)) \
+	MUX_VAL(CP(MMC2_DAT7),	(IDIS  | PTU | EN  | M4)) \
+ /*Bluetooth*/\
+	MUX_VAL(CP(MCBSP3_DX),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP3_DR),	(IEN  | PTD | DIS | M0)) \
+ /*LocalBus LAN Reset*/\
+	MUX_VAL(CP(MCBSP3_CLKX), (IEN  | PTD | DIS | M4)) \
+ /*LocalBus LAN IRQ*/\
+	MUX_VAL(CP(MCBSP3_FSX),	(IEN  | PTD | DIS | M4)) \
+	MUX_VAL(CP(UART2_CTS),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(UART2_RTS),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART2_TX),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART2_RX),	(IEN  | PTD | DIS | M0)) \
+ /*Modem Interface */\
+	MUX_VAL(CP(UART1_TX),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART1_RTS),	(IDIS | PTD | DIS | M0))  \
+	MUX_VAL(CP(UART1_CTS),	(IEN  | PTU | DIS | M0))  \
+	MUX_VAL(CP(UART1_RX),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP4_CLKX), (IEN  | PTD | DIS | M1)) \
+	MUX_VAL(CP(MCBSP4_DR),	(IEN  | PTD | DIS | M1)) \
+	MUX_VAL(CP(MCBSP4_DX),	(IEN  | PTD | DIS | M1)) \
+	MUX_VAL(CP(MCBSP4_FSX),	(IEN  | PTD | DIS | M1)) \
+	MUX_VAL(CP(MCBSP1_CLKR),     (IEN | PTD | DIS | M1)) \
+	MUX_VAL(CP(MCBSP1_FSR),	(IDIS | PTU | EN  | M4)) \
+	MUX_VAL(CP(MCBSP1_DX),	(IEN | PTD | DIS | M1)) \
+	MUX_VAL(CP(MCBSP1_DR),		(IEN | PTD | DIS | M1)) \
+	MUX_VAL(CP(MCBSP_CLKS),	(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MCBSP1_FSX),	(IEN | PTD | EN | M1)) \
+	MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTU | EN | M4)) \
+ /*Serial Interface*/\
+	MUX_VAL(CP(UART3_CTS_RCTX), (IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART3_RX_IRRX), (IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_CLK),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_STP),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(HSUSB0_DIR),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_NXT),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA0), (IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA1), (IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA2), (IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA3), (IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA4), (IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA5), (IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA6), (IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA7), (IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(I2C1_SCL),	(IEN  | PTU | EN | M0)) \
+	MUX_VAL(CP(I2C1_SDA),	(IEN  | PTU | EN | M0)) \
+	MUX_VAL(CP(I2C2_SCL),	(IEN  | PTU | EN | M0)) \
+	MUX_VAL(CP(I2C2_SDA),	(IEN  | PTU | EN | M0)) \
+	MUX_VAL(CP(I2C3_SCL),	(IEN  | PTU | EN | M0)) \
+	MUX_VAL(CP(I2C3_SDA),	(IEN  | PTU | EN | M0)) \
+	MUX_VAL(CP(I2C4_SCL),	(IEN  | PTU | EN | M0)) \
+	MUX_VAL(CP(I2C4_SDA),	(IEN  | PTU | EN | M0)) \
+	MUX_VAL(CP(HDQ_SIO),	(IEN  | PTU | EN | M0)) \
+	MUX_VAL(CP(MCSPI1_CLK),	(IEN  | PTD | EN | M0)) \
+	MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | EN | M0)) \
+	MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | EN | M0)) \
+	MUX_VAL(CP(MCSPI1_CS0),	(IEN  | PTD | EN | M0)) \
+	MUX_VAL(CP(MCSPI1_CS1),	(IEN  | PTD | EN | M0)) \
+	MUX_VAL(CP(MCSPI1_CS2),	(IEN  | PTD | EN | M4)) \
+ /* USB EHCI (port 2) */\
+	MUX_VAL(CP(MCSPI1_CS3),	(IEN  | PTU | DIS | M3)) \
+	MUX_VAL(CP(MCSPI2_CLK),	(IEN  | PTU | DIS | M3)) \
+	MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTU | DIS | M3)) \
+	MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTU | DIS | M3)) \
+	MUX_VAL(CP(MCSPI2_CS0),	(IEN  | PTU | DIS | M3)) \
+	MUX_VAL(CP(MCSPI2_CS1),	(IEN  | PTU | DIS | M3)) \
+ /*Control and debug */\
+	MUX_VAL(CP(SYS_32K),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SYS_CLKREQ),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SYS_NIRQ),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(SYS_BOOT0),	(IEN  | PTD | DIS | M4)) \
+	MUX_VAL(CP(SYS_BOOT1),	(IEN  | PTD | DIS | M4)) \
+	MUX_VAL(CP(SYS_BOOT2),	(IEN  | PTD | DIS | M4)) \
+	MUX_VAL(CP(SYS_BOOT3),	(IEN  | PTD | DIS | M4)) \
+	MUX_VAL(CP(SYS_BOOT4),	(IEN  | PTD | DIS | M4)) \
+	MUX_VAL(CP(SYS_BOOT5),	(IEN  | PTD | DIS | M4)) \
+	MUX_VAL(CP(SYS_BOOT6),	(IDIS | PTD | DIS | M4))  \
+	/* - VIO_1V8*/\
+	MUX_VAL(CP(SYS_OFF_MODE), (IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SYS_CLKOUT1), (IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SYS_CLKOUT2), (IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(JTAG_nTRST),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_TCK),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_TMS),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_TDI),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_EMU0),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_EMU1),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTU | EN  | M4)) \
+	MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M4)) \
+	MUX_VAL(CP(ETK_D0_ES2),	(IEN  | PTU | DIS | M1)) \
+	MUX_VAL(CP(ETK_D1_ES2),	(IEN  | PTU | DIS | M1)) \
+	MUX_VAL(CP(ETK_D2_ES2),	(IEN  | PTU | DIS | M1)) \
+	MUX_VAL(CP(ETK_D3_ES2),	(IEN  | PTU | DIS | M1)) \
+	MUX_VAL(CP(ETK_D4_ES2),	(IEN  | PTU | EN | M4)) \
+	MUX_VAL(CP(ETK_D5_ES2),	(IEN  | PTU | EN | M4)) \
+	MUX_VAL(CP(ETK_D6_ES2),	(IEN  | PTU | EN | M4)) \
+	MUX_VAL(CP(ETK_D7_ES2),	(IEN  | PTU | DIS | M1)) \
+	MUX_VAL(CP(ETK_D8_ES2),	(IEN  | PTU | EN | M4)) \
+	MUX_VAL(CP(ETK_D9_ES2),	(IEN  | PTD | EN | M4)) \
+	MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)) \
+	MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)) \
+	MUX_VAL(CP(ETK_D12_ES2), (IEN  | PTU | DIS | M3)) \
+	MUX_VAL(CP(ETK_D13_ES2), (IEN  | PTU | DIS | M3)) \
+	MUX_VAL(CP(ETK_D14_ES2), (IEN|PTU|DIS|M3)) \
+	MUX_VAL(CP(ETK_D15_ES2), (IEN  | PTU | DIS | M3)) \
+	MUX_VAL(CP(D2D_MCAD1),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD2),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD3),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD4),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD5),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD6),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD7),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD8),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD9),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD10),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD11),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD12),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD13),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD14),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD15),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD16),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD17),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD18),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD19),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD20),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD21),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD22),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD23),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD24),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD25),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD26),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD27),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD28),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD29),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD30),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD31),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD32),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD33),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD34),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD35),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD36),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_CLK26MI), (IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_NRESPWRON), (IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_NRESWARM), (IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(D2D_ARM9NIRQ), (IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_SPINT),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_FRINT),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_DMAREQ0), (IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_DMAREQ1), (IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_DMAREQ2), (IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_DMAREQ3), (IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTRST), (IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTDI),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTDO),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTMS),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTCK),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GRTCK), (IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_MSTDBY),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(D2D_SWAKEUP), (IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_IDLEREQ), (IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_IDLEACK), (IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(D2D_MWRITE),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_SWRITE),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_MREAD),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_SREAD),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_MBUSFLAG), (IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_SBUSFLAG), (IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_CKE0),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(SDRC_CKE1),	(IDIS | PTU | EN  | M0))
+
+#endif
diff --git a/boards.cfg b/boards.cfg
index 343e82f..6143671 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -189,6 +189,7 @@  omap3_zoom1                  arm         armv7       zoom1               logicpd
 omap3_zoom2                  arm         armv7       zoom2               logicpd        omap3
 omap3_mvblx                  arm         armv7       mvblx               matrix_vision  omap3
 tam3517                      arm         armv7       tam3517             technexion     omap3
+tao3530                      arm         armv7       tao3530             technexion     omap3
 omap3_beagle                 arm         armv7       beagle              ti             omap3
 omap3_evm                    arm         armv7       evm                 ti             omap3
 omap3_evm_quick_mmc          arm         armv7       evm                 ti             omap3
diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h
new file mode 100644
index 0000000..30d2ef9
--- /dev/null
+++ b/include/configs/tao3530.h
@@ -0,0 +1,362 @@ 
+/*
+ * Configuration settings for the TechNexion TAO-3530 board.
+ *
+ * Edward Lin <linuxfae@technexion.com>
+ * Tapani Utriainen <linuxfae@technexion.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* #define DEBUG */
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMV7		1	/* This is an ARM V7 CPU core */
+#define CONFIG_OMAP		1	/* in a TI OMAP core */
+#define CONFIG_OMAP34XX		1	/* which is a 34XX */
+#define CONFIG_OMAP3430		1	/* which is in a 3430 */
+#define CONFIG_OMAP3_TAO3530	1	/* working with TAO-3530 */
+
+#define CONFIG_SDRC			/* Has an SDRC controller */
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO		1
+#define CONFIG_DISPLAY_BOARDINFO	1
+
+/* Clock Defines */
+#define V_OSCK			26000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+#undef CONFIG_USE_IRQ				/* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_OF_LIBFDT		1
+/*
+ * The early kernel mapping on ARM currently only maps from the base of DRAM
+ * to the end of the kernel image.  The kernel is loaded at DRAM base + 0x8000.
+ * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000,
+ * so that leaves DRAM base to DRAM base + 0x4000 available.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	        0x4000
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+#define CONFIG_REVISION_TAG		1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
+						/* Sector */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
+						/* initial data */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX		3
+#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
+#define CONFIG_SERIAL3			3	/* UART3 */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
+					115200}
+#define CONFIG_GENERIC_MMC		1
+#define CONFIG_MMC			1
+#define CONFIG_OMAP_HSMMC		1
+#define CONFIG_DOS_PARTITION		1
+
+/* DDR - I use Micron DDR */
+#define CONFIG_OMAP3_MICRON_DDR		1
+
+/* USB */
+#define CONFIG_MUSB_UDC			1
+#define CONFIG_USB_OMAP3		1
+#define CONFIG_TWL4030_USB		1
+
+#ifdef CONFIG_MUSB_UDC
+/* USB device configuration */
+#define CONFIG_USB_DEVICE		1
+#define CONFIG_USB_TTY			1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
+
+/* Change these to suit your needs */
+#define CONFIG_USBD_VENDORID		0x0451
+#define CONFIG_USBD_PRODUCTID		0x5678
+#define CONFIG_USBD_MANUFACTURER	"Texas Instruments"
+#define CONFIG_USBD_PRODUCT_NAME	"EVM"
+#endif /* CONFIG_MUSB_UDC */
+
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
+#define CONFIG_CMD_FAT		/* FAT support			*/
+#define CONFIG_CMD_JFFS2	/* JFFS2 support		*/
+#define CONFIG_CMD_MTDPARTS	/* Enable MTD parts commands */
+#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
+#define MTDIDS_DEFAULT			"nand0=nand"
+#define MTDPARTS_DEFAULT		"mtdparts=nand:512k(x-loader),"\
+					"1920k(u-boot),128k(u-boot-env),"\
+					"4m(kernel),-(fs)"
+
+#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
+#define CONFIG_CMD_MMC		/* MMC support			*/
+#define CONFIG_CMD_NAND		/* NAND support			*/
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+
+#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
+#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
+#undef CONFIG_CMD_IMI		/* iminfo			*/
+#undef CONFIG_CMD_IMLS		/* List all found images	*/
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_HARD_I2C			1
+#define CONFIG_SYS_I2C_SPEED		400000
+#define CONFIG_SYS_I2C_SLAVE		1
+#define CONFIG_SYS_I2C_BUS		0
+#define CONFIG_SYS_I2C_BUS_SELECT	1
+#define CONFIG_I2C_MULTI_BUS		1
+#define CONFIG_DRIVER_OMAP34XX_I2C	1
+
+#if defined(CONFIG_CMD_JFFS2)
+#define CONFIG_JFFS2_NAND
+#define CONFIG_JFFS2_DEV		"nand0"
+#define CONFIG_JFFS2_PART_OFFSET	0x680000
+#define CONFIG_JFFS2_PART_SIZE		0xf980000
+#endif /* CONFIG_CMD_JFFS2 */
+
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER		1
+#define CONFIG_TWL4030_LED		1
+
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_SYS_NAND_QUIET_TEST	1
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
+							/* to access nand */
+#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
+							/* to access nand at */
+							/* CS0 */
+#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
+							/* devices */
+/* Environment information */
+#define CONFIG_BOOTDELAY		2
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x82000000\0" \
+	"console=ttyO2,115200n8\0" \
+	"mpurate=600\0" \
+	"dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \
+	"tv_mode=omapfb.mode=tv:ntsc\0" \
+	"video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \
+	"lcd_mode=omapfb.mode=lcd:800x480@60 \0" \
+	"extra_options= \0" \
+	"mem_size=mem=128M \0" \
+	"mmcdev=0\0" \
+	"mmcroot=/dev/mmcblk0p2 rw\0" \
+	"mmcrootfstype=ext3 rootwait\0" \
+	"nandroot=ubi0:rootfs ubi.mtd=4\0" \
+	"nandrootfstype=ubifs\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"${mem_size} " \
+		"mpurate=${mpurate} " \
+		"${video_mode} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype} " \
+		"${extra_options}\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"${mem_size} " \
+		"mpurate=${mpurate} " \
+		"${video_mode} " \
+		"${network_setting} " \
+		"root=${nandroot} " \
+		"rootfstype=${nandrootfstype} "\
+		"${extra_options}\0" \
+	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source ${loadaddr}\0" \
+	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nand read ${loadaddr} 280000 400000; " \
+		"bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"if mmc rescan ${mmcdev}; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"else run nandboot; " \
+			"fi; " \
+		"fi; " \
+	"else run nandboot; fi"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_PROMPT		"TAO-3530 # "
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+
+/* turn on command-line edit/hist/auto */
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_COMMAND_HISTORY
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_AUTOCOMPLETE
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
+
+#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)	/* memtest */
+								/* works on */
+#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
+					0x01F00000) /* 31MB */
+
+#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)	/* default */
+							/* load address */
+#define CONFIG_SYS_TEXT_BASE           0x80008000
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
+#define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ			1000
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4 << 10)	/* IRQ stack 4 KiB */
+#define CONFIG_STACKSIZE_FIQ	(4 << 10)	/* FIQ stack 4 KiB */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
+#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 MiB */
+#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
+
+/* SDRAM Bank Allocation method */
+#define SDRC_R_B_C		1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+
+/* Configure the PISMO */
+#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
+#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
+#define CONFIG_SYS_FLASH_BASE		PISMO1_NAND_BASE
+
+/* Monitor at start of flash */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
+
+#define CONFIG_ENV_IS_IN_NAND		1
+#define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
+#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
+
+#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)
+#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
+#define CONFIG_ENV_ADDR			CONFIG_ENV_OFFSET
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE	0x800
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_OMAP3_SPI
+
+/*----------------------------------------------------------------------------
+ * SMSC9115 Ethernet from SMSC9118 family
+ *----------------------------------------------------------------------------
+ */
+#if defined(CONFIG_CMD_NET)
+
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_32_BIT
+#define CONFIG_SMC911X_BASE	0x2C000000
+
+/* BOOTP fields */
+#define CONFIG_BOOTP_SUBNETMASK		0x00000001
+#define CONFIG_BOOTP_GATEWAY		0x00000002
+#define CONFIG_BOOTP_HOSTNAME		0x00000004
+#define CONFIG_BOOTP_BOOTPATH		0x00000010
+
+#endif /* (CONFIG_CMD_NET) */
+
+#endif /* __CONFIG_H */