Message ID | 1319686540-999-1-git-send-email-Chang-Ming.Huang@freescale.com |
---|---|
State | Superseded |
Delegated to: | Kim Phillips |
Headers | show |
Dear Chang-Ming.Huang@freescale.com, In message <1319686540-999-1-git-send-email-Chang-Ming.Huang@freescale.com> you wrote: > From: Jerry Huang <Chang-Ming.Huang@freescale.com> > > This patch: > 1. Support 512MB DDR. > 2. Support 33.33MHz oscillator. > 3. QE clock is changed to 500MHz as the default value. > > The new MPC8360EMDS board changes the oscillator to 33.33MHz in order to > support QE 500MHZ and this new board supports 512MB DDR since 2008, > but the u-boot only supports 256MB DDR and 66.6MHz oscillator on top tree, > > For 512MB DDR: > BAT0 is used for the first 256MB memory, BAT4 is used for the second > 256MB memory and the address space of SDRAM follows the DDR, so if the size > of DDR is 256MB, the BAT4 will be used for SDRAM and if the size of DDR > is 512MB, the BAT4 will be used for the second 256MB memory and there is no BAT > for SDRAM. > Therefore, if the size of DDR is 512MB, this patch will use BAT6 for SDRAM > and BAT5 will be used for PCI MEM to replace the BAT6 after the codes relocates > to the DDR. > > Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> > --- > arch/powerpc/lib/board.c | 19 +++++++++++++++++-- > board/freescale/mpc8360emds/mpc8360emds.c | 17 +++++++++++++++++ > include/configs/MPC8360EMDS.h | 11 ++++++----- > 3 files changed, 40 insertions(+), 7 deletions(-) You post 3 different (?) versions of this patch, but fail to proovide any information what has changed. Read http://www.denx.de/wiki/view/U-Boot/Patches#Sending_updated_patch_versions and then add the mandatory history of changes. Best regards, Wolfgang Denk
Hi Jerry Hunag, 2011/10/27 <Chang-Ming.Huang@freescale.com>: > From: Jerry Huang <Chang-Ming.Huang@freescale.com> > > This patch: > 1. Support 512MB DDR. > 2. Support 33.33MHz oscillator. > 3. QE clock is changed to 500MHz as the default value. [snip] > Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Please add change log between each different version of patches. Could you please follow the patch rules that listed on u-boot wiki? Like, Changes for v2 - blah blah blah Changes for v3 - meow meow meow And please also remember to CC the custodian who should be in charge of dealing with the patch. Thanks!
diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c index 9885b14..8a97c1b 100644 --- a/arch/powerpc/lib/board.c +++ b/arch/powerpc/lib/board.c @@ -75,9 +75,7 @@ #include <keyboard.h> #endif -#ifdef CONFIG_ADDR_MAP #include <asm/mmu.h> -#endif #ifdef CONFIG_MP #include <asm/mp.h> @@ -642,6 +640,23 @@ void board_init_r (gd_t *id, ulong dest_addr) gd = id; /* initialize RAM version of global data */ bd = gd->bd; +#ifdef CONFIG_MPC8360EMDS + /* + * BAT6 is used for SDRAM when DDR size is 512MB or larger than 256MB + * So re-setup PCI MEM space used BAT5 after relocated to DDR + */ + if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { + /* Clear the BAT5 */ + write_bat(DBAT5, 0, 0); + write_bat(IBAT5, 0, 0); + asm("sync"); + /* Setup BAT5 for PCI MEM */ + write_bat(DBAT5, CONFIG_SYS_DBAT6U, CONFIG_SYS_DBAT6L); + write_bat(IBAT5, CONFIG_SYS_IBAT6U, CONFIG_SYS_IBAT6L); + asm("sync"); + } +#endif + gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ /* The Malloc area is immediately below the monitor copy in DRAM */ diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c index 51d8035..3bd108d 100644 --- a/board/freescale/mpc8360emds/mpc8360emds.c +++ b/board/freescale/mpc8360emds/mpc8360emds.c @@ -24,6 +24,7 @@ #include <asm/mmu.h> #include <asm/io.h> #include <asm/fsl_enet.h> +#include <asm/mmu.h> #if defined(CONFIG_OF_LIBFDT) #include <libfdt.h> #endif @@ -292,6 +293,22 @@ static int sdram_init(unsigned int base) if (rem) base = base - rem + sdram_size; + /* + * Setup BAT6 for SDRAM when DDR size is 512MB or larger than 256MB + * After relocated to DDR, re-setup PCI MEM space used BAT5 + */ + if (base > CONFIG_MAX_MEM_MAPPED) { + unsigned long batl = base | BATL_PP_10 | BATL_MEMCOHERENCE; + unsigned long batu = base | BATU_BL_64M | BATU_VS | BATU_VP; + + write_bat(DBAT6, 0, 0); /* Clear the BAT6 */ + write_bat(IBAT6, 0, 0); + asm("sync"); + write_bat(DBAT6, batu, batl); /* Setup the BAT6 for SDRAM */ + write_bat(IBAT6, batu, batl); + asm("sync"); + } + sdram_addr = (uint *)base; /* * Setup SDRAM Base and Option Registers diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index 49d64a5..b4b385a 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -40,13 +40,13 @@ * System Clock Setup */ #ifdef CONFIG_PCISLAVE -#define CONFIG_83XX_PCICLK 66000000 /* in HZ */ +#define CONFIG_83XX_PCICLK 33330000 /* in HZ */ #else -#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ +#define CONFIG_83XX_CLKIN 33330000 /* in Hz */ #endif #ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ 66000000 +#define CONFIG_SYS_CLK_FREQ 33330000 #endif /* @@ -55,11 +55,11 @@ #define CONFIG_SYS_HRCW_LOW (\ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN_4X1 |\ + HRCWL_CSB_TO_CLKIN_8X1 |\ HRCWL_VCO_1X2 |\ HRCWL_CE_PLL_VCO_DIV_4 |\ HRCWL_CE_PLL_DIV_1X1 |\ - HRCWL_CE_TO_PLL_1X6 |\ + HRCWL_CE_TO_PLL_1X15 |\ HRCWL_CORE_TO_CSB_2X1) #ifdef CONFIG_PCISLAVE @@ -506,6 +506,7 @@ */ #define CONFIG_HIGH_BATS 1 /* High BATs supported */ +#define CONFIG_BAT_RW /* DDR/LBC SDRAM: cacheable */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)