Message ID | 1318397647-10601-1-git-send-email-hs@denx.de |
---|---|
State | Changes Requested |
Headers | show |
Ah, but we asked (and you agreed) to name the option generically since it's about OOB position rather than ECC size. And the help should reflect that it's about changing the OOB position relative to data as foudn on some davinci platforms rather than just being to enable support in davinci SoCs. Other boards might need this :) On Tue, Oct 11, 2011 at 10:34 PM, Heiko Schocher <hs@denx.de> wrote: > Signed-off-by: Heiko Schocher <hs@denx.de> > Cc: Paulraj Sandeep <s-paulraj@ti.com> > Cc: Scott Wood <scottwood@freescale.com> > --- > README | 4 ++++ > 1 files changed, 4 insertions(+), 0 deletions(-) > > diff --git a/README b/README > index 0868531..f6fa2c1 100644 > --- a/README > +++ b/README > @@ -3075,6 +3075,10 @@ Low Level (hardware related) configuration options: > - CONFIG_SYS_SRIOn_MEM_SIZE: > Size of SRIO port 'n' memory region > > +- CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST > + enable 4bit ECC hardware calculation algorithm, used on > + davinci soc. > + > - CONFIG_SYS_NDFC_16 > Defined to tell the NDFC that the NAND chip is using a > 16 bit bus. > -- > 1.7.6.2 > > _______________________________________________ > U-Boot mailing list > U-Boot@lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot >
Hello Tom, added Sandeep Paulraj to cc, as he is the ti custodian ... Tom Rini wrote: > Ah, but we asked (and you agreed) to name the option generically since Where do you read, that I agreed to rename this config option? I just wrote: http://lists.denx.de/pipermail/u-boot/2011-October/104784.html "Ok, you are right, there is no documentation of this config option. Should I add this documentation in this patch or in a seperate patch?" and Wolfgang Denk said here: http://lists.denx.de/pipermail/u-boot/2011-October/104786.html "Separate, please. Thanks." ... > it's about OOB position rather than ECC size. And the help should > reflect that it's about changing the OOB position relative to data as > foudn on some davinci platforms rather than just being to enable > support in davinci SoCs. Other boards might need this :) Maybe I oversee something, but as I see in Code, this feature is davinci only (as this is a CPU feature) ... Ah, maybe I got it! I added this option to "drivers/mtd/nand/nand_spl_simple.c" and there it should get a more common name, right? ... Ok, so I see the following to do: rework patch: http://lists.denx.de/pipermail/u-boot/2011-October/104769.html - rename "CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST" to "CONFIG_SYS_NAND_ECC_OOBFIRST"? - add a doc for this new config option - add this new config option to the enbw_cmc board support This doc patch: http://lists.denx.de/pipermail/u-boot/2011-October/104907.html - This can go to mainline, as it just documents the existing CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST config option for davinci socs. Ok? bye, Heiko
On Tuesday, October 18, 2011, Heiko Schocher <hs@denx.de> wrote: > Hello Tom, > > added Sandeep Paulraj to cc, as he is the ti custodian ... > > Tom Rini wrote: >> Ah, but we asked (and you agreed) to name the option generically since > > Where do you read, that I agreed to rename this config option? I must have misremembered things, sorry. [snip] > > - rename "CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST" to > "CONFIG_SYS_NAND_ECC_OOBFIRST"? > - add a doc for this new config option > - add this new config option to the enbw_cmc board support > > This doc patch: > http://lists.denx.de/pipermail/u-boot/2011-October/104907.html > > - This can go to mainline, as it just documents the existing > CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST config option for davinci > socs. > > Ok? > Works for me, thanks again.
diff --git a/README b/README index 0868531..f6fa2c1 100644 --- a/README +++ b/README @@ -3075,6 +3075,10 @@ Low Level (hardware related) configuration options: - CONFIG_SYS_SRIOn_MEM_SIZE: Size of SRIO port 'n' memory region +- CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST + enable 4bit ECC hardware calculation algorithm, used on + davinci soc. + - CONFIG_SYS_NDFC_16 Defined to tell the NDFC that the NAND chip is using a 16 bit bus.
Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Paulraj Sandeep <s-paulraj@ti.com> Cc: Scott Wood <scottwood@freescale.com> --- README | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-)