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apic: test tsc deadline timer

Message ID BC00F5384FCFC9499AF06F92E8B78A9E265DEF3266@shsmsx502.ccr.corp.intel.com
State New
Headers show

Commit Message

Liu, Jinsong Oct. 9, 2011, 3:32 p.m. UTC 
Updated test case for kvm tsc deadline timer https://github.com/avikivity/kvm-unit-tests, as attached.

Thanks,
Jinsong

Comments

Avi Kivity Oct. 10, 2011, 10:30 a.m. UTC | #1 
On 10/09/2011 05:32 PM, Liu, Jinsong wrote:
> Updated test case for kvm tsc deadline timer https://github.com/avikivity/kvm-unit-tests, as attached.
>

Applied, thanks.
Liu, Jinsong Oct. 13, 2011, 7:56 a.m. UTC | #2 
Avi Kivity wrote:
> On 10/09/2011 05:32 PM, Liu, Jinsong wrote:
>> Updated test case for kvm tsc deadline timer
>> https://github.com/avikivity/kvm-unit-tests, as attached. 
>> 
> 
> Applied, thanks.

Which tree? I didn't find it at git://github.com/avikivity/kvm-unit-tests.git

Thanks,
Jinsong
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Patch

=================
From 2b476cf741b36da5df35cf2e8f7f9562e8245fcd Mon Sep 17 00:00:00 2001
From: Liu, Jinsong <jinsong.liu@intel.com>
Date: Sun, 9 Oct 2011 22:45:39 +0800
Subject: [PATCH] apic: test tsc deadline timer

Test tsc deadline timer: detect tsc deadline timer support by CPUID,
enable tsc deadline timer mode by MMIO, then start tsc deadline timer by WRMSR.

Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
---
 x86/apic.c |   47 +++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 47 insertions(+), 0 deletions(-)

diff --git a/x86/apic.c b/x86/apic.c
index c51e6a5..2725b9a 100644
--- a/x86/apic.c
+++ b/x86/apic.c
@@ -25,6 +25,51 @@  static void test_lapic_existence(void)
     report("apic existence", (u16)lvr == 0x14);
 }
 
+#define TSC_DEADLINE_TIMER_MODE (2 << 17)
+#define TSC_DEADLINE_TIMER_VECTOR 0xef
+#define MSR_IA32_TSC            0x00000010
+#define MSR_IA32_TSCDEADLINE    0x000006e0
+
+static int tdt_count;
+
+static void tsc_deadline_timer_isr(isr_regs_t *regs)
+{
+    ++tdt_count;
+}
+
+static void start_tsc_deadline_timer(void)
+{
+    handle_irq(TSC_DEADLINE_TIMER_VECTOR, tsc_deadline_timer_isr);
+    irq_enable();
+
+    wrmsr(MSR_IA32_TSCDEADLINE, rdmsr(MSR_IA32_TSC));
+    asm volatile ("nop");
+    report("tsc deadline timer", tdt_count == 1);
+}
+
+static int enable_tsc_deadline_timer(void)
+{
+    uint32_t lvtt;
+
+    if (cpuid(1).c & (1 << 24)) {
+        lvtt = TSC_DEADLINE_TIMER_MODE | TSC_DEADLINE_TIMER_VECTOR;
+        apic_write(APIC_LVTT, lvtt);
+        start_tsc_deadline_timer();
+        return 1;
+    } else {
+        return 0;
+    }
+}
+
+static void test_tsc_deadline_timer(void)
+{
+    if(enable_tsc_deadline_timer()) {
+        printf("tsc deadline timer enabled\n");
+    } else {
+        printf("tsc deadline timer not detected\n");
+    }
+}
+
 #define MSR_APIC_BASE 0x0000001b
 
 void test_enable_x2apic(void)
@@ -291,6 +336,8 @@  int main()
     test_sti_nmi();
     test_multiple_nmi();
 
+    test_tsc_deadline_timer();
+
     printf("\nsummary: %d tests, %d failures\n", g_tests, g_fail);
 
     return g_fail != 0;