diff mbox

[1/1] kvm: support TSC deadline MSR

Message ID bfc2455ddbb41148494a084d15777e6bed7533c3.1317675329.git.mtosatti@redhat.com
State New
Headers show

Commit Message

Marcelo Tosatti Oct. 3, 2011, 8:55 p.m. UTC 
From: "Liu, Jinsong" <jinsong.liu@intel.com>

KVM add emulation of lapic tsc deadline timer for guest.
This patch is co-operation work at qemu side.

Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
---
 target-i386/cpu.h     |    4 +++-
 target-i386/kvm.c     |   14 ++++++++++++++
 target-i386/machine.c |    1 +
 3 files changed, 18 insertions(+), 1 deletions(-)

Comments

Avi Kivity Oct. 4, 2011, 5:53 p.m. UTC | #1 
On 10/03/2011 10:55 PM, Marcelo Tosatti wrote:
> From: "Liu, Jinsong"<jinsong.liu@intel.com>
>
> KVM add emulation of lapic tsc deadline timer for guest.
> This patch is co-operation work at qemu side.
>
> -#define CPU_SAVE_VERSION 12
> +#define CPU_SAVE_VERSION 13
>
>

Unfortunate.  Can't we use subsections?
Marcelo Tosatti Oct. 4, 2011, 10:20 p.m. UTC | #2 
On Tue, Oct 04, 2011 at 07:53:42PM +0200, Avi Kivity wrote:
> On 10/03/2011 10:55 PM, Marcelo Tosatti wrote:
> >From: "Liu, Jinsong"<jinsong.liu@intel.com>
> >
> >KVM add emulation of lapic tsc deadline timer for guest.
> >This patch is co-operation work at qemu side.
> >
> >-#define CPU_SAVE_VERSION 12
> >+#define CPU_SAVE_VERSION 13
> >
> >
> 
> Unfortunate.  Can't we use subsections?

Yes, i'll look into it tomorrow.
Anthony Liguori Oct. 10, 2011, 2:54 p.m. UTC | #3 
On 10/04/2011 05:20 PM, Marcelo Tosatti wrote:
> On Tue, Oct 04, 2011 at 07:53:42PM +0200, Avi Kivity wrote:
>> On 10/03/2011 10:55 PM, Marcelo Tosatti wrote:
>>> From: "Liu, Jinsong"<jinsong.liu@intel.com>
>>>
>>> KVM add emulation of lapic tsc deadline timer for guest.
>>> This patch is co-operation work at qemu side.
>>>
>>> -#define CPU_SAVE_VERSION 12
>>> +#define CPU_SAVE_VERSION 13
>>>
>>>
>>
>> Unfortunate.  Can't we use subsections?
>
> Yes, i'll look into it tomorrow.

Subsections are still broken at the moment although Juan has some patches. 
Bumping the version is the safe thing to do.

Regards,

Anthony Liguori

>
>
>
Avi Kivity Oct. 10, 2011, 2:58 p.m. UTC | #4 
On 10/10/2011 04:54 PM, Anthony Liguori wrote:
> On 10/04/2011 05:20 PM, Marcelo Tosatti wrote:
>> On Tue, Oct 04, 2011 at 07:53:42PM +0200, Avi Kivity wrote:
>>> On 10/03/2011 10:55 PM, Marcelo Tosatti wrote:
>>>> From: "Liu, Jinsong"<jinsong.liu@intel.com>
>>>>
>>>> KVM add emulation of lapic tsc deadline timer for guest.
>>>> This patch is co-operation work at qemu side.
>>>>
>>>> -#define CPU_SAVE_VERSION 12
>>>> +#define CPU_SAVE_VERSION 13
>>>>
>>>>
>>>
>>> Unfortunate.  Can't we use subsections?
>>
>> Yes, i'll look into it tomorrow.
>
> Subsections are still broken at the moment although Juan has some 
> patches. Bumping the version is the safe thing to do.
>

It's irreversible, once we release a version with a bumped ID we can't 
go back.
Anthony Liguori Oct. 10, 2011, 3:10 p.m. UTC | #5 
On 10/10/2011 09:58 AM, Avi Kivity wrote:
> On 10/10/2011 04:54 PM, Anthony Liguori wrote:
>> On 10/04/2011 05:20 PM, Marcelo Tosatti wrote:
>>> On Tue, Oct 04, 2011 at 07:53:42PM +0200, Avi Kivity wrote:
>>>> On 10/03/2011 10:55 PM, Marcelo Tosatti wrote:
>>>>> From: "Liu, Jinsong"<jinsong.liu@intel.com>
>>>>>
>>>>> KVM add emulation of lapic tsc deadline timer for guest.
>>>>> This patch is co-operation work at qemu side.
>>>>>
>>>>> -#define CPU_SAVE_VERSION 12
>>>>> +#define CPU_SAVE_VERSION 13
>>>>>
>>>>>
>>>>
>>>> Unfortunate. Can't we use subsections?
>>>
>>> Yes, i'll look into it tomorrow.
>>
>> Subsections are still broken at the moment although Juan has some patches.
>> Bumping the version is the safe thing to do.
>>
>
> It's irreversible, once we release a version with a bumped ID we can't go back.

But the question is whether we've bumped *any* versions of common devices since 
0.15 because if so, it's moot here.  Once any device bumps a version id, 
migration is incompatible.

Subsections are nice for stable branches, but they don't solve inter-version 
compatibility.  Most importantly, subsections are broken today so until we 
straighten things out there, we can't rely on them.

Regards,

Anthony Liguori
Avi Kivity Oct. 10, 2011, 3:29 p.m. UTC | #6 
On 10/10/2011 05:10 PM, Anthony Liguori wrote:
>> It's irreversible, once we release a version with a bumped ID we 
>> can't go back.
>
>
> But the question is whether we've bumped *any* versions of common 
> devices since 0.15 because if so, it's moot here. 

What's the answer?  And if the answer is we did, why did we?

> Once any device bumps a version id, migration is incompatible.
>
> Subsections are nice for stable branches, but they don't solve 
> inter-version compatibility.

Why not?  Though I agree it's a long shot to get it to work, since there 
are so many changes and it's easy to get any one of them wrong.

You had an idea once to fingerprint the migration format and compare it 
across versions?  I assume the almighty visitor can make this very simple?

>   Most importantly, subsections are broken today so until we 
> straighten things out there, we can't rely on them.
>

Let's not throw a permanent baby out with the temporary bath water.
diff mbox

Patch

diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index ae36489..a973f2e 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -283,6 +283,7 @@ 
 #define MSR_IA32_APICBASE_BSP           (1<<8)
 #define MSR_IA32_APICBASE_ENABLE        (1<<11)
 #define MSR_IA32_APICBASE_BASE          (0xfffff<<12)
+#define MSR_IA32_TSCDEADLINE            0x6e0
 
 #define MSR_MTRRcap			0xfe
 #define MSR_MTRRcap_VCNT		8
@@ -687,6 +688,7 @@  typedef struct CPUX86State {
     uint64_t async_pf_en_msr;
 
     uint64_t tsc;
+    uint64_t tsc_deadline;
 
     uint64_t mcg_status;
 
@@ -947,7 +949,7 @@  uint64_t cpu_get_tsc(CPUX86State *env);
 #define cpu_list_id x86_cpu_list
 #define cpudef_setup	x86_cpudef_setup
 
-#define CPU_SAVE_VERSION 12
+#define CPU_SAVE_VERSION 13
 
 /* MMU modes definitions */
 #define MMU_MODE0_SUFFIX _kernel
diff --git a/target-i386/kvm.c b/target-i386/kvm.c
index b6eef04..90a6ffb 100644
--- a/target-i386/kvm.c
+++ b/target-i386/kvm.c
@@ -59,6 +59,7 @@  const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
 
 static bool has_msr_star;
 static bool has_msr_hsave_pa;
+static bool has_msr_tsc_deadline;
 static bool has_msr_async_pf_en;
 static int lm_capable_kernel;
 
@@ -568,6 +569,10 @@  static int kvm_get_supported_msrs(KVMState *s)
                     has_msr_hsave_pa = true;
                     continue;
                 }
+                if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
+                    has_msr_tsc_deadline = true;
+                    continue;
+                }
             }
         }
 
@@ -881,6 +886,9 @@  static int kvm_put_msrs(CPUState *env, int level)
     if (has_msr_hsave_pa) {
         kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
     }
+    if (has_msr_tsc_deadline) {
+        kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
+    }
 #ifdef TARGET_X86_64
     if (lm_capable_kernel) {
         kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
@@ -1127,6 +1135,9 @@  static int kvm_get_msrs(CPUState *env)
     if (has_msr_hsave_pa) {
         msrs[n++].index = MSR_VM_HSAVE_PA;
     }
+    if (has_msr_tsc_deadline) {
+        msrs[n++].index = MSR_IA32_TSCDEADLINE;
+    }
 
     if (!env->tsc_valid) {
         msrs[n++].index = MSR_IA32_TSC;
@@ -1195,6 +1206,9 @@  static int kvm_get_msrs(CPUState *env)
         case MSR_IA32_TSC:
             env->tsc = msrs[i].data;
             break;
+        case MSR_IA32_TSCDEADLINE:
+            env->tsc_deadline = msrs[i].data;
+            break;
         case MSR_VM_HSAVE_PA:
             env->vm_hsave = msrs[i].data;
             break;
diff --git a/target-i386/machine.c b/target-i386/machine.c
index 9aca8e0..25fa97d 100644
--- a/target-i386/machine.c
+++ b/target-i386/machine.c
@@ -410,6 +410,7 @@  static const VMStateDescription vmstate_cpu = {
         VMSTATE_UINT64_V(xcr0, CPUState, 12),
         VMSTATE_UINT64_V(xstate_bv, CPUState, 12),
         VMSTATE_YMMH_REGS_VARS(ymmh_regs, CPUState, CPU_NB_REGS, 12),
+        VMSTATE_UINT64_V(tsc_deadline, CPUState, 13),
         VMSTATE_END_OF_LIST()
         /* The above list is not sorted /wrt version numbers, watch out! */
     },