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Add VIS intrinsics header for sparc.

Message ID alpine.LNX.2.00.1109260048020.4092@gerinyyl.fvgr
State New
Headers show

Commit Message

Gerald Pfeifer Sept. 25, 2011, 10:50 p.m. UTC 
On Sun, 25 Sep 2011, David Miller wrote:
> I'll add a note about this to gcc-4.7/changes.html along with
> the FMAF stuff I'm about to commit.

Thanks for doing that, David.  I believe my automated tester has
naged you over a small markup issue in the patch which I am 
addressing thusly (together with some more markup).

Gerald

>

Comments

David Miller Sept. 26, 2011, 5:07 a.m. UTC | #1 
From: Gerald Pfeifer <gerald@pfeifer.com>
Date: Mon, 26 Sep 2011 00:50:22 +0200 (CEST)

> On Sun, 25 Sep 2011, David Miller wrote:
>> I'll add a note about this to gcc-4.7/changes.html along with
>> the FMAF stuff I'm about to commit.
> 
> Thanks for doing that, David.  I believe my automated tester has
> naged you over a small markup issue in the patch which I am 
> addressing thusly (together with some more markup).

Thanks a lot Gerald.
diff mbox

Patch

Index: changes.html
===================================================================
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-4.7/changes.html,v
retrieving revision 1.32
diff -u -r1.32 changes.html
--- changes.html	25 Sep 2011 22:39:05 -0000	1.32
+++ changes.html	25 Sep 2011 22:47:14 -0000
@@ -322,15 +322,16 @@ 
             operations.</li>
         <li>The compiler now properly tracks the <code>%gsr</code> register,
             and how it behaves as an input for various VIS instructions.</li>
-        <li>Akin to 'fzero', the compiler can now generate 'fone' instructions
-            in order to set all of the bits of a floating-point register to one.
+        <li>Akin to <code>fzero</code>, the compiler can now generate
+            <code>fone</code> instructions in order to set all of the bits
+            of a floating-point register to one.</li>
         <li>The documentation for the VIS intrinsics in the GCC manual has
             been brought up to date and many inaccuracies were fixed.</li>
       </ul>
     </li>
-    <li>Support for UltraSPARC Fused Multiply-Add Floating-point
+    <li>Support for UltraSPARC Fused Multiply-Add floating-point
         extensions has been added.  These instructions are enabled by
-        default on UltraSPARC T3 (Niagara 3) and later cpus.</li>
+        default on UltraSPARC T3 (Niagara 3) and later CPUs.</li>
   </ul>
 
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