Qemu co-operation with kvm tsc deadline timer

From 8c39f2ddbf7069342826a83e535c0c7b641d6501 Mon Sep 17 00:00:00 2001
From: Liu, Jinsong <jinsong.liu@intel.com>
Date: Thu, 22 Sep 2011 16:28:13 +0800
Subject: [PATCH] Qemu co-operation with kvm tsc deadline timer

KVM add emulation of lapic tsc deadline timer for guest.
This patch is co-operation work at qemu side.

Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
---
 target-i386/cpu.h     |    2 ++
 target-i386/kvm.c     |    7 +++++++
 target-i386/machine.c |    1 +
 3 files changed, 10 insertions(+), 0 deletions(-)

On Thu, Sep 22, 2011 at 04:57:14PM +0800, Liu, Jinsong wrote:
> >From 8c39f2ddbf7069342826a83e535c0c7b641d6501 Mon Sep 17 00:00:00 2001
> From: Liu, Jinsong <jinsong.liu@intel.com>
> Date: Thu, 22 Sep 2011 16:28:13 +0800
> Subject: [PATCH] Qemu co-operation with kvm tsc deadline timer
> 
> KVM add emulation of lapic tsc deadline timer for guest.
> This patch is co-operation work at qemu side.
> 
> Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
> ---
>  target-i386/cpu.h     |    2 ++
>  target-i386/kvm.c     |    7 +++++++
>  target-i386/machine.c |    1 +
>  3 files changed, 10 insertions(+), 0 deletions(-)

Please add back has_msr_tsc_deadline checks, otherwise users are scared
with "unsupported MSR" messages on older kernels.

On 2011-09-22 10:57, Liu, Jinsong wrote:
> From 8c39f2ddbf7069342826a83e535c0c7b641d6501 Mon Sep 17 00:00:00 2001
> From: Liu, Jinsong <jinsong.liu@intel.com>
> Date: Thu, 22 Sep 2011 16:28:13 +0800
> Subject: [PATCH] Qemu co-operation with kvm tsc deadline timer
> 
> KVM add emulation of lapic tsc deadline timer for guest.
> This patch is co-operation work at qemu side.
> 
> Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
> ---
>  target-i386/cpu.h     |    2 ++
>  target-i386/kvm.c     |    7 +++++++
>  target-i386/machine.c |    1 +
>  3 files changed, 10 insertions(+), 0 deletions(-)
> 
> diff --git a/target-i386/cpu.h b/target-i386/cpu.h
> index 935d08a..62ff73c 100644
> --- a/target-i386/cpu.h
> +++ b/target-i386/cpu.h
> @@ -283,6 +283,7 @@
>  #define MSR_IA32_APICBASE_BSP           (1<<8)
>  #define MSR_IA32_APICBASE_ENABLE        (1<<11)
>  #define MSR_IA32_APICBASE_BASE          (0xfffff<<12)
> +#define MSR_IA32_TSCDEADLINE            0x6e0
>  
>  #define MSR_MTRRcap			0xfe
>  #define MSR_MTRRcap_VCNT		8
> @@ -687,6 +688,7 @@ typedef struct CPUX86State {
>      uint64_t async_pf_en_msr;
>  
>      uint64_t tsc;
> +    uint64_t tsc_deadline;
>  
>      uint64_t mcg_status;
>  
> diff --git a/target-i386/kvm.c b/target-i386/kvm.c
> index aa843f0..2d55070 100644
> --- a/target-i386/kvm.c
> +++ b/target-i386/kvm.c
> @@ -942,6 +942,8 @@ static int kvm_put_msrs(CPUState *env, int level)
>          }
>      }
>  
> +    kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
> +
>      msr_data.info.nmsrs = n;
>  
>      return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
> @@ -1173,6 +1175,8 @@ static int kvm_get_msrs(CPUState *env)
>          }
>      }
>  
> +    msrs[n++].index = MSR_IA32_TSCDEADLINE;
> +
>      msr_data.info.nmsrs = n;
>      ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
>      if (ret < 0) {
> @@ -1213,6 +1217,9 @@ static int kvm_get_msrs(CPUState *env)
>          case MSR_IA32_TSC:
>              env->tsc = msrs[i].data;
>              break;
> +        case MSR_IA32_TSCDEADLINE:
> +            env->tsc_deadline = msrs[i].data;
> +            break;
>          case MSR_VM_HSAVE_PA:
>              env->vm_hsave = msrs[i].data;
>              break;
> diff --git a/target-i386/machine.c b/target-i386/machine.c
> index 9aca8e0..25fa97d 100644
> --- a/target-i386/machine.c
> +++ b/target-i386/machine.c
> @@ -410,6 +410,7 @@ static const VMStateDescription vmstate_cpu = {
>          VMSTATE_UINT64_V(xcr0, CPUState, 12),
>          VMSTATE_UINT64_V(xstate_bv, CPUState, 12),
>          VMSTATE_YMMH_REGS_VARS(ymmh_regs, CPUState, CPU_NB_REGS, 12),
> +        VMSTATE_UINT64_V(tsc_deadline, CPUState, 13),

Don't forget to update CPU_SAVE_VERSION.

Jan