diff mbox series

[v3,09/10] target/mips: Simplify 64-bit ifdef'ry of MXU code

Message ID 20210222223901.2792336-10-f4bug@amsat.org
State New
Headers show
Series target/mips: Extract MXU code to new mxu_translate.c file | expand

Commit Message

Philippe Mathieu-Daudé Feb. 22, 2021, 10:39 p.m. UTC 
Check for 'TARGET_LONG_BITS == 32' and simplify 64-bit ifdef'ry.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/translate.h |  2 --
 target/mips/translate.c | 18 ++++++++++--------
 2 files changed, 10 insertions(+), 10 deletions(-)

Comments

Richard Henderson Feb. 24, 2021, 1:48 a.m. UTC | #1 
On 2/22/21 2:39 PM, Philippe Mathieu-Daudé wrote:
> +#else /* !defined(TARGET_MIPS64) */
> +
> +bool decode_ase_mxu(DisasContext *ctx, uint32_t insn)
> +{
> +    return false;

Also seems suspect, but harmless.

> -#if !defined(TARGET_MIPS64)
> -        if (ctx->insn_flags & ASE_MXU) {
> +        if ((TARGET_LONG_BITS == 32) && (ctx->insn_flags & ASE_MXU)) {
>              decode_opc_mxu(ctx, ctx->opcode);

(1) Unnecessary () around ==.

(2) The call to decode_opc_mxu should be eliminated by the compiler because of
the constant false test.  You can (a) retain the function above and omit the
new test, (b) add the new test and leave the function undefined, a diagnostic
link error, or you can re-declare the function with QEMU_ERROR.


> @@ -28081,9 +28085,7 @@ void mips_tcg_init(void)
>      cpu_llval = tcg_global_mem_new(cpu_env, offsetof(CPUMIPSState, llval),
>                                     "llval");
>  
> -#if !defined(TARGET_MIPS64)
>      mxu_translate_init();
> -#endif /* !TARGET_MIPS64 */

This one won't be eliminated, and is an abort for MIPS64 per patch 8, so all
mips64 now aborts on startup.


r~
diff mbox series

Patch

diff --git a/target/mips/translate.h b/target/mips/translate.h
index 1801e7f819e..a807b3d2566 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -179,10 +179,8 @@  extern TCGv bcond;
 void msa_translate_init(void);
 
 /* MXU */
-#if !defined(TARGET_MIPS64)
 void mxu_translate_init(void);
 bool decode_ase_mxu(DisasContext *ctx, uint32_t insn);
-#endif /* !TARGET_MIPS64 */
 
 /* decodetree generated */
 bool decode_isa_rel6(DisasContext *ctx, uint32_t insn);
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 609798a0bee..68b5dee4bab 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -25850,6 +25850,15 @@  bool decode_ase_mxu(DisasContext *ctx, uint32_t insn)
     return true;
 }
 
+#else /* !defined(TARGET_MIPS64) */
+
+bool decode_ase_mxu(DisasContext *ctx, uint32_t insn)
+{
+    return false;
+}
+
+#endif /* defined(TARGET_MIPS64) */
+
 /*
  * Main MXU decoding function
  */
@@ -25871,9 +25880,6 @@  static void decode_opc_mxu(DisasContext *ctx, uint32_t insn)
     decode_ase_mxu(ctx, insn);
 }
 
-#endif /* !defined(TARGET_MIPS64) */
-
-
 static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
 {
     int rs, rt, rd;
@@ -27017,12 +27023,10 @@  static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
             break;
         }
 #endif
-#if !defined(TARGET_MIPS64)
-        if (ctx->insn_flags & ASE_MXU) {
+        if ((TARGET_LONG_BITS == 32) && (ctx->insn_flags & ASE_MXU)) {
             decode_opc_mxu(ctx, ctx->opcode);
             break;
         }
-#endif
         decode_opc_special2_legacy(env, ctx);
         break;
     case OPC_SPECIAL3:
@@ -28081,9 +28085,7 @@  void mips_tcg_init(void)
     cpu_llval = tcg_global_mem_new(cpu_env, offsetof(CPUMIPSState, llval),
                                    "llval");
 
-#if !defined(TARGET_MIPS64)
     mxu_translate_init();
-#endif /* !TARGET_MIPS64 */
 }
 
 void restore_state_to_opc(CPUMIPSState *env, TranslationBlock *tb,