| Message ID | 1611274735-303873-2-git-send-email-komlodi@xilinx.com |
|---|---|
| State | New |
| Headers | show |
| Series | target/microblaze: Add memattrs on transactions | expand |
On Thu, Jan 21, 2021 at 04:18:53PM -0800, Joe Komlodi wrote: > This property is used to control the security of the following interfaces > on MicroBlaze: > M_AXI_DP - data interface > M_AXI_IP - instruction interface > M_AXI_DC - dcache interface > M_AXI_IC - icache interface > > It works by enabling or disabling the use of the non_secure[3:0] signals. > > Interfaces and their corresponding values are taken from: > https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_2/ug984-vivado-microblaze-ref.pdf > page 153. Thanks Joe! Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> > > Signed-off-by: Joe Komlodi <komlodi@xilinx.com> > --- > target/microblaze/cpu.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++ > target/microblaze/cpu.h | 11 +++++++++++ > 2 files changed, 57 insertions(+) > > diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c > index c8e754c..accfb23 100644 > --- a/target/microblaze/cpu.c > +++ b/target/microblaze/cpu.c > @@ -98,6 +98,38 @@ static bool mb_cpu_has_work(CPUState *cs) > } > > #ifndef CONFIG_USER_ONLY > +static void mb_cpu_ns_axi_dp(void *opaque, int irq, int level) > +{ > + MicroBlazeCPU *cpu = opaque; > + bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_DP_MASK; > + > + cpu->ns_axi_dp = level & en; > +} > + > +static void mb_cpu_ns_axi_ip(void *opaque, int irq, int level) > +{ > + MicroBlazeCPU *cpu = opaque; > + bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_IP_MASK; > + > + cpu->ns_axi_ip = level & en; > +} > + > +static void mb_cpu_ns_axi_dc(void *opaque, int irq, int level) > +{ > + MicroBlazeCPU *cpu = opaque; > + bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_DC_MASK; > + > + cpu->ns_axi_dc = level & en; > +} > + > +static void mb_cpu_ns_axi_ic(void *opaque, int irq, int level) > +{ > + MicroBlazeCPU *cpu = opaque; > + bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_IC_MASK; > + > + cpu->ns_axi_ic = level & en; > +} > + > static void microblaze_cpu_set_irq(void *opaque, int irq, int level) > { > MicroBlazeCPU *cpu = opaque; > @@ -248,6 +280,10 @@ static void mb_cpu_initfn(Object *obj) > #ifndef CONFIG_USER_ONLY > /* Inbound IRQ and FIR lines */ > qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2); > + qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_dp, "ns_axi_dp", 1); > + qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_ip, "ns_axi_ip", 1); > + qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_dc, "ns_axi_dc", 1); > + qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_ic, "ns_axi_ic", 1); > #endif > } > > @@ -277,6 +313,16 @@ static Property mb_properties[] = { > DEFINE_PROP_BOOL("use-msr-instr", MicroBlazeCPU, cfg.use_msr_instr, true), > DEFINE_PROP_BOOL("use-pcmp-instr", MicroBlazeCPU, cfg.use_pcmp_instr, true), > DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true), > + /* > + * use-non-secure enables/disables the use of the non_secure[3:0] signals. > + * It is a bitfield where 1 = non-secure for the following bits and their > + * corresponding interfaces: > + * 0x1 - M_AXI_DP > + * 0x2 - M_AXI_IP > + * 0x4 - M_AXI_DC > + * 0x8 - M_AXI_IC > + */ > + DEFINE_PROP_UINT8("use-non-secure", MicroBlazeCPU, cfg.use_non_secure, 0), > DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback, > false), > DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false), > diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h > index c1c2641..199cfb0 100644 > --- a/target/microblaze/cpu.h > +++ b/target/microblaze/cpu.h > @@ -233,6 +233,12 @@ typedef struct CPUMBState CPUMBState; > > #define TARGET_INSN_START_EXTRA_WORDS 1 > > +/* use-non-secure property masks */ > +#define USE_NON_SECURE_M_AXI_DP_MASK 0x1 > +#define USE_NON_SECURE_M_AXI_IP_MASK 0x2 > +#define USE_NON_SECURE_M_AXI_DC_MASK 0x4 > +#define USE_NON_SECURE_M_AXI_IC_MASK 0x8 > + > struct CPUMBState { > uint32_t bvalue; /* TCG temporary, only valid during a TB */ > uint32_t btarget; /* Full resolved branch destination */ > @@ -316,6 +322,7 @@ typedef struct { > bool use_msr_instr; > bool use_pcmp_instr; > bool use_mmu; > + uint8_t use_non_secure; > bool dcache_writeback; > bool endi; > bool dopb_bus_exception; > @@ -337,6 +344,10 @@ struct MicroBlazeCPU { > CPUState parent_obj; > > /*< public >*/ > + bool ns_axi_dp; > + bool ns_axi_ip; > + bool ns_axi_dc; > + bool ns_axi_ic; > > CPUNegativeOffsetState neg; > CPUMBState env; > -- > 2.7.4 >
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index c8e754c..accfb23 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -98,6 +98,38 @@ static bool mb_cpu_has_work(CPUState *cs) } #ifndef CONFIG_USER_ONLY +static void mb_cpu_ns_axi_dp(void *opaque, int irq, int level) +{ + MicroBlazeCPU *cpu = opaque; + bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_DP_MASK; + + cpu->ns_axi_dp = level & en; +} + +static void mb_cpu_ns_axi_ip(void *opaque, int irq, int level) +{ + MicroBlazeCPU *cpu = opaque; + bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_IP_MASK; + + cpu->ns_axi_ip = level & en; +} + +static void mb_cpu_ns_axi_dc(void *opaque, int irq, int level) +{ + MicroBlazeCPU *cpu = opaque; + bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_DC_MASK; + + cpu->ns_axi_dc = level & en; +} + +static void mb_cpu_ns_axi_ic(void *opaque, int irq, int level) +{ + MicroBlazeCPU *cpu = opaque; + bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_IC_MASK; + + cpu->ns_axi_ic = level & en; +} + static void microblaze_cpu_set_irq(void *opaque, int irq, int level) { MicroBlazeCPU *cpu = opaque; @@ -248,6 +280,10 @@ static void mb_cpu_initfn(Object *obj) #ifndef CONFIG_USER_ONLY /* Inbound IRQ and FIR lines */ qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2); + qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_dp, "ns_axi_dp", 1); + qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_ip, "ns_axi_ip", 1); + qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_dc, "ns_axi_dc", 1); + qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_ic, "ns_axi_ic", 1); #endif } @@ -277,6 +313,16 @@ static Property mb_properties[] = { DEFINE_PROP_BOOL("use-msr-instr", MicroBlazeCPU, cfg.use_msr_instr, true), DEFINE_PROP_BOOL("use-pcmp-instr", MicroBlazeCPU, cfg.use_pcmp_instr, true), DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true), + /* + * use-non-secure enables/disables the use of the non_secure[3:0] signals. + * It is a bitfield where 1 = non-secure for the following bits and their + * corresponding interfaces: + * 0x1 - M_AXI_DP + * 0x2 - M_AXI_IP + * 0x4 - M_AXI_DC + * 0x8 - M_AXI_IC + */ + DEFINE_PROP_UINT8("use-non-secure", MicroBlazeCPU, cfg.use_non_secure, 0), DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback, false), DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false), diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index c1c2641..199cfb0 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -233,6 +233,12 @@ typedef struct CPUMBState CPUMBState; #define TARGET_INSN_START_EXTRA_WORDS 1 +/* use-non-secure property masks */ +#define USE_NON_SECURE_M_AXI_DP_MASK 0x1 +#define USE_NON_SECURE_M_AXI_IP_MASK 0x2 +#define USE_NON_SECURE_M_AXI_DC_MASK 0x4 +#define USE_NON_SECURE_M_AXI_IC_MASK 0x8 + struct CPUMBState { uint32_t bvalue; /* TCG temporary, only valid during a TB */ uint32_t btarget; /* Full resolved branch destination */ @@ -316,6 +322,7 @@ typedef struct { bool use_msr_instr; bool use_pcmp_instr; bool use_mmu; + uint8_t use_non_secure; bool dcache_writeback; bool endi; bool dopb_bus_exception; @@ -337,6 +344,10 @@ struct MicroBlazeCPU { CPUState parent_obj; /*< public >*/ + bool ns_axi_dp; + bool ns_axi_ip; + bool ns_axi_dc; + bool ns_axi_ic; CPUNegativeOffsetState neg; CPUMBState env;
This property is used to control the security of the following interfaces on MicroBlaze: M_AXI_DP - data interface M_AXI_IP - instruction interface M_AXI_DC - dcache interface M_AXI_IC - icache interface It works by enabling or disabling the use of the non_secure[3:0] signals. Interfaces and their corresponding values are taken from: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_2/ug984-vivado-microblaze-ref.pdf page 153. Signed-off-by: Joe Komlodi <komlodi@xilinx.com> --- target/microblaze/cpu.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++ target/microblaze/cpu.h | 11 +++++++++++ 2 files changed, 57 insertions(+)