| Message ID | 20201130102228.2395100-1-f4bug@amsat.org |
|---|---|
| State | New |
| Headers | show |
| Series | target/mips: Allow executing MSA instructions on Loongson-3A4000 | expand |
On 11/30/20 4:22 AM, Philippe Mathieu-Daudé wrote: > The Loongson-3A4000 is a GS464V-based processor with MIPS MSA ASE: > https://www.mail-archive.com/qemu-devel@nongnu.org/msg763059.html > > Commit af868995e1b correctly set the 'MSA present' bit of Config3 > register, but forgot to allow the MSA instructions decoding in > insn_flags, so executing them triggers a 'Reserved Instruction'. > > Fix by adding the ASE_MSA mask to insn_flags. > > Fixes: af868995e1b ("target/mips: Add Loongson-3 CPU definition") > Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > --- > Buggy since 5.1, so probably not a big deal. > --- > target/mips/translate_init.c.inc | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
Reviewed-by: Huacai Chen <chenhc@lemote.com> On Tue, Dec 1, 2020 at 2:24 AM Richard Henderson <richard.henderson@linaro.org> wrote: > > On 11/30/20 4:22 AM, Philippe Mathieu-Daudé wrote: > > The Loongson-3A4000 is a GS464V-based processor with MIPS MSA ASE: > > https://www.mail-archive.com/qemu-devel@nongnu.org/msg763059.html > > > > Commit af868995e1b correctly set the 'MSA present' bit of Config3 > > register, but forgot to allow the MSA instructions decoding in > > insn_flags, so executing them triggers a 'Reserved Instruction'. > > > > Fix by adding the ASE_MSA mask to insn_flags. > > > > Fixes: af868995e1b ("target/mips: Add Loongson-3 CPU definition") > > Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > > --- > > Buggy since 5.1, so probably not a big deal. > > --- > > target/mips/translate_init.c.inc | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > > r~ >
On 11/30/20 11:22 AM, Philippe Mathieu-Daudé wrote: > The Loongson-3A4000 is a GS464V-based processor with MIPS MSA ASE: > https://www.mail-archive.com/qemu-devel@nongnu.org/msg763059.html > > Commit af868995e1b correctly set the 'MSA present' bit of Config3 > register, but forgot to allow the MSA instructions decoding in > insn_flags, so executing them triggers a 'Reserved Instruction'. > > Fix by adding the ASE_MSA mask to insn_flags. > > Fixes: af868995e1b ("target/mips: Add Loongson-3 CPU definition") > Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > --- > Buggy since 5.1, so probably not a big deal. > --- > target/mips/translate_init.c.inc | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Thanks, applied to mips-next.
diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc index ea85d5c6a79..79f75ed863c 100644 --- a/target/mips/translate_init.c.inc +++ b/target/mips/translate_init.c.inc @@ -832,7 +832,7 @@ const mips_def_t mips_defs[] = .mmu_type = MMU_TYPE_R4000, }, { - .name = "Loongson-3A4000", + .name = "Loongson-3A4000", /* GS464V-based */ .CP0_PRid = 0x14C000, /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | @@ -885,7 +885,7 @@ const mips_def_t mips_defs[] = .CP1_fcr31_rw_bitmask = 0xFF83FFFF, .SEGBITS = 48, .PABITS = 48, - .insn_flags = CPU_LOONGSON3A, + .insn_flags = CPU_LOONGSON3A | ASE_MSA, .mmu_type = MMU_TYPE_R4000, }, {
The Loongson-3A4000 is a GS464V-based processor with MIPS MSA ASE: https://www.mail-archive.com/qemu-devel@nongnu.org/msg763059.html Commit af868995e1b correctly set the 'MSA present' bit of Config3 register, but forgot to allow the MSA instructions decoding in insn_flags, so executing them triggers a 'Reserved Instruction'. Fix by adding the ASE_MSA mask to insn_flags. Fixes: af868995e1b ("target/mips: Add Loongson-3 CPU definition") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> --- Buggy since 5.1, so probably not a big deal. --- target/mips/translate_init.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)