diff mbox series

[1/3] imx: imx8mm: Update clock bindings header

Message ID 20201204232747.223325-1-aford173@gmail.com
State Accepted
Commit d72cecec7fc0b04d6d52df44ae1e7033ee7e4099
Delegated to: Stefano Babic
Headers show
Series [1/3] imx: imx8mm: Update clock bindings header | expand

Commit Message

Adam Ford Dec. 4, 2020, 11:27 p.m. UTC
Import clock bindings header file from Linux 5.10-rc6

Signed-off-by: Adam Ford <aford173@gmail.com>

Comments

Peng Fan Dec. 7, 2020, 2:11 a.m. UTC | #1
> Subject: [PATCH 1/3] imx: imx8mm: Update clock bindings header
> 
> Import clock bindings header file from Linux 5.10-rc6
> 
> Signed-off-by: Adam Ford <aford173@gmail.com>

Acked-by: Peng Fan <peng.fan@nxp.com>

> 
> diff --git a/include/dt-bindings/clock/imx8mm-clock.h
> b/include/dt-bindings/clock/imx8mm-clock.h
> index 07e6c686f3..e63a5530ae 100644
> --- a/include/dt-bindings/clock/imx8mm-clock.h
> +++ b/include/dt-bindings/clock/imx8mm-clock.h
> @@ -248,6 +248,32 @@
>  #define IMX8MM_CLK_SNVS_ROOT			228
>  #define IMX8MM_CLK_GIC				229
> 
> -#define IMX8MM_CLK_END				230
> +#define IMX8MM_SYS_PLL1_40M_CG			230
> +#define IMX8MM_SYS_PLL1_80M_CG			231
> +#define IMX8MM_SYS_PLL1_100M_CG			232
> +#define IMX8MM_SYS_PLL1_133M_CG			233
> +#define IMX8MM_SYS_PLL1_160M_CG			234
> +#define IMX8MM_SYS_PLL1_200M_CG			235
> +#define IMX8MM_SYS_PLL1_266M_CG			236
> +#define IMX8MM_SYS_PLL1_400M_CG			237
> +#define IMX8MM_SYS_PLL2_50M_CG			238
> +#define IMX8MM_SYS_PLL2_100M_CG			239
> +#define IMX8MM_SYS_PLL2_125M_CG			240
> +#define IMX8MM_SYS_PLL2_166M_CG			241
> +#define IMX8MM_SYS_PLL2_200M_CG			242
> +#define IMX8MM_SYS_PLL2_250M_CG			243
> +#define IMX8MM_SYS_PLL2_333M_CG			244
> +#define IMX8MM_SYS_PLL2_500M_CG			245
> +
> +#define IMX8MM_CLK_M4_CORE			246
> +#define IMX8MM_CLK_VPU_CORE			247
> +#define IMX8MM_CLK_GPU3D_CORE			248
> +#define IMX8MM_CLK_GPU2D_CORE			249
> +
> +#define IMX8MM_CLK_CLKO2			250
> +
> +#define IMX8MM_CLK_A53_CORE			251
> +
> +#define IMX8MM_CLK_END				252
> 
>  #endif
> --
> 2.25.1
Stefano Babic Dec. 26, 2020, 3:53 p.m. UTC | #2
> Import clock bindings header file from Linux 5.10-rc6
> Signed-off-by: Adam Ford <aford173@gmail.com>
> Acked-by: Peng Fan <peng.fan@nxp.com>
> diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings/clock/imx8mm-clock.h
> index 07e6c686f3..e63a5530ae 100644
> --- a/include/dt-bindings/clock/imx8mm-clock.h
> +++ b/include/dt-bindings/clock/imx8mm-clock.h
> @@ -248,6 +248,32 @@
>  #define IMX8MM_CLK_SNVS_ROOT			228
>  #define IMX8MM_CLK_GIC				229
>  
> -#define IMX8MM_CLK_END				230
> +#define IMX8MM_SYS_PLL1_40M_CG			230
> +#define IMX8MM_SYS_PLL1_80M_CG			231
> +#define IMX8MM_SYS_PLL1_100M_CG			232
> +#define IMX8MM_SYS_PLL1_133M_CG			233
> +#define IMX8MM_SYS_PLL1_160M_CG			234
> +#define IMX8MM_SYS_PLL1_200M_CG			235
> +#define IMX8MM_SYS_PLL1_266M_CG			236
> +#define IMX8MM_SYS_PLL1_400M_CG			237
> +#define IMX8MM_SYS_PLL2_50M_CG			238
> +#define IMX8MM_SYS_PLL2_100M_CG			239
> +#define IMX8MM_SYS_PLL2_125M_CG			240
> +#define IMX8MM_SYS_PLL2_166M_CG			241
> +#define IMX8MM_SYS_PLL2_200M_CG			242
> +#define IMX8MM_SYS_PLL2_250M_CG			243
> +#define IMX8MM_SYS_PLL2_333M_CG			244
> +#define IMX8MM_SYS_PLL2_500M_CG			245
> +
> +#define IMX8MM_CLK_M4_CORE			246
> +#define IMX8MM_CLK_VPU_CORE			247
> +#define IMX8MM_CLK_GPU3D_CORE			248
> +#define IMX8MM_CLK_GPU2D_CORE			249
> +
> +#define IMX8MM_CLK_CLKO2			250
> +
> +#define IMX8MM_CLK_A53_CORE			251
> +
> +#define IMX8MM_CLK_END				252
>  
>  #endif
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic
diff mbox series

Patch

diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings/clock/imx8mm-clock.h
index 07e6c686f3..e63a5530ae 100644
--- a/include/dt-bindings/clock/imx8mm-clock.h
+++ b/include/dt-bindings/clock/imx8mm-clock.h
@@ -248,6 +248,32 @@ 
 #define IMX8MM_CLK_SNVS_ROOT			228
 #define IMX8MM_CLK_GIC				229
 
-#define IMX8MM_CLK_END				230
+#define IMX8MM_SYS_PLL1_40M_CG			230
+#define IMX8MM_SYS_PLL1_80M_CG			231
+#define IMX8MM_SYS_PLL1_100M_CG			232
+#define IMX8MM_SYS_PLL1_133M_CG			233
+#define IMX8MM_SYS_PLL1_160M_CG			234
+#define IMX8MM_SYS_PLL1_200M_CG			235
+#define IMX8MM_SYS_PLL1_266M_CG			236
+#define IMX8MM_SYS_PLL1_400M_CG			237
+#define IMX8MM_SYS_PLL2_50M_CG			238
+#define IMX8MM_SYS_PLL2_100M_CG			239
+#define IMX8MM_SYS_PLL2_125M_CG			240
+#define IMX8MM_SYS_PLL2_166M_CG			241
+#define IMX8MM_SYS_PLL2_200M_CG			242
+#define IMX8MM_SYS_PLL2_250M_CG			243
+#define IMX8MM_SYS_PLL2_333M_CG			244
+#define IMX8MM_SYS_PLL2_500M_CG			245
+
+#define IMX8MM_CLK_M4_CORE			246
+#define IMX8MM_CLK_VPU_CORE			247
+#define IMX8MM_CLK_GPU3D_CORE			248
+#define IMX8MM_CLK_GPU2D_CORE			249
+
+#define IMX8MM_CLK_CLKO2			250
+
+#define IMX8MM_CLK_A53_CORE			251
+
+#define IMX8MM_CLK_END				252
 
 #endif