| Message ID | 20201130023535.16689-16-cfontana@suse.de |
|---|---|
| State | New |
| Headers | show |
| Series | i386 cleanup | expand |
On 11/30/20 3:35 AM, Claudio Fontana wrote: > From: Eduardo Habkost <ehabkost@redhat.com> > > Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> > --- > accel/tcg/cputlb.c | 6 +++--- > accel/tcg/user-exec.c | 6 +++--- > include/hw/core/cpu.h | 9 --------- > include/hw/core/tcg-cpu-ops.h | 12 ++++++++++++ > target/alpha/cpu.c | 2 +- > target/arm/cpu.c | 2 +- > target/avr/cpu.c | 2 +- > target/cris/cpu.c | 2 +- > target/hppa/cpu.c | 2 +- > target/i386/tcg-cpu.c | 2 +- > target/lm32/cpu.c | 2 +- > target/m68k/cpu.c | 2 +- > target/microblaze/cpu.c | 2 +- > target/mips/cpu.c | 2 +- > target/moxie/cpu.c | 2 +- > target/nios2/cpu.c | 2 +- > target/openrisc/cpu.c | 2 +- > target/ppc/translate_init.c.inc | 2 +- > target/riscv/cpu.c | 2 +- > target/rx/cpu.c | 2 +- > target/s390x/cpu.c | 2 +- > target/sh4/cpu.c | 2 +- > target/sparc/cpu.c | 2 +- > target/tilegx/cpu.c | 2 +- > target/tricore/cpu.c | 2 +- > target/unicore32/cpu.c | 2 +- > target/xtensa/cpu.c | 2 +- > 27 files changed, 41 insertions(+), 38 deletions(-) With cc->tcg_ops.* guarded with #ifdef CONFIG_TCG: Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
On Fri, Dec 04, 2020 at 06:14:07PM +0100, Philippe Mathieu-Daudé wrote: > On 11/30/20 3:35 AM, Claudio Fontana wrote: > > From: Eduardo Habkost <ehabkost@redhat.com> > > > > Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> > > --- > > accel/tcg/cputlb.c | 6 +++--- > > accel/tcg/user-exec.c | 6 +++--- > > include/hw/core/cpu.h | 9 --------- > > include/hw/core/tcg-cpu-ops.h | 12 ++++++++++++ > > target/alpha/cpu.c | 2 +- > > target/arm/cpu.c | 2 +- > > target/avr/cpu.c | 2 +- > > target/cris/cpu.c | 2 +- > > target/hppa/cpu.c | 2 +- > > target/i386/tcg-cpu.c | 2 +- > > target/lm32/cpu.c | 2 +- > > target/m68k/cpu.c | 2 +- > > target/microblaze/cpu.c | 2 +- > > target/mips/cpu.c | 2 +- > > target/moxie/cpu.c | 2 +- > > target/nios2/cpu.c | 2 +- > > target/openrisc/cpu.c | 2 +- > > target/ppc/translate_init.c.inc | 2 +- > > target/riscv/cpu.c | 2 +- > > target/rx/cpu.c | 2 +- > > target/s390x/cpu.c | 2 +- > > target/sh4/cpu.c | 2 +- > > target/sparc/cpu.c | 2 +- > > target/tilegx/cpu.c | 2 +- > > target/tricore/cpu.c | 2 +- > > target/unicore32/cpu.c | 2 +- > > target/xtensa/cpu.c | 2 +- > > 27 files changed, 41 insertions(+), 38 deletions(-) > > With cc->tcg_ops.* guarded with #ifdef CONFIG_TCG: > Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Thanks! Are the #ifdefs a hard condition for your Reviewed-by? Even if we agree #ifdef CONFIG_TCG is the way to go, I don't think this should block a series that's a step in the right direction. It can be done in a separate patch. (Unless the lack of #ifdef introduces regressions, of course)
On 12/4/20 6:37 PM, Eduardo Habkost wrote: > On Fri, Dec 04, 2020 at 06:14:07PM +0100, Philippe Mathieu-Daudé wrote: >> On 11/30/20 3:35 AM, Claudio Fontana wrote: >>> From: Eduardo Habkost <ehabkost@redhat.com> >>> >>> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> >>> --- >>> accel/tcg/cputlb.c | 6 +++--- >>> accel/tcg/user-exec.c | 6 +++--- >>> include/hw/core/cpu.h | 9 --------- >>> include/hw/core/tcg-cpu-ops.h | 12 ++++++++++++ >>> target/alpha/cpu.c | 2 +- >>> target/arm/cpu.c | 2 +- >>> target/avr/cpu.c | 2 +- >>> target/cris/cpu.c | 2 +- >>> target/hppa/cpu.c | 2 +- >>> target/i386/tcg-cpu.c | 2 +- >>> target/lm32/cpu.c | 2 +- >>> target/m68k/cpu.c | 2 +- >>> target/microblaze/cpu.c | 2 +- >>> target/mips/cpu.c | 2 +- >>> target/moxie/cpu.c | 2 +- >>> target/nios2/cpu.c | 2 +- >>> target/openrisc/cpu.c | 2 +- >>> target/ppc/translate_init.c.inc | 2 +- >>> target/riscv/cpu.c | 2 +- >>> target/rx/cpu.c | 2 +- >>> target/s390x/cpu.c | 2 +- >>> target/sh4/cpu.c | 2 +- >>> target/sparc/cpu.c | 2 +- >>> target/tilegx/cpu.c | 2 +- >>> target/tricore/cpu.c | 2 +- >>> target/unicore32/cpu.c | 2 +- >>> target/xtensa/cpu.c | 2 +- >>> 27 files changed, 41 insertions(+), 38 deletions(-) >> >> With cc->tcg_ops.* guarded with #ifdef CONFIG_TCG: >> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> > > Thanks! > > Are the #ifdefs a hard condition for your Reviewed-by? No, as you said, this is fine as a first step, so you can include them. > Even if we agree #ifdef CONFIG_TCG is the way to go, I don't > think this should block a series that's a step in the right > direction. It can be done in a separate patch. > > (Unless the lack of #ifdef introduces regressions, of course) I'm worried about the +system -tcg build configuration. s390x is the only target testing for such regressions (see "[s390x] Clang (disable-tcg)" on Travis-CI.
On 12/4/20 6:37 PM, Eduardo Habkost wrote: > On Fri, Dec 04, 2020 at 06:14:07PM +0100, Philippe Mathieu-Daudé wrote: >> On 11/30/20 3:35 AM, Claudio Fontana wrote: >>> From: Eduardo Habkost <ehabkost@redhat.com> >>> >>> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> >>> --- >>> accel/tcg/cputlb.c | 6 +++--- >>> accel/tcg/user-exec.c | 6 +++--- >>> include/hw/core/cpu.h | 9 --------- >>> include/hw/core/tcg-cpu-ops.h | 12 ++++++++++++ >>> target/alpha/cpu.c | 2 +- >>> target/arm/cpu.c | 2 +- >>> target/avr/cpu.c | 2 +- >>> target/cris/cpu.c | 2 +- >>> target/hppa/cpu.c | 2 +- >>> target/i386/tcg-cpu.c | 2 +- >>> target/lm32/cpu.c | 2 +- >>> target/m68k/cpu.c | 2 +- >>> target/microblaze/cpu.c | 2 +- >>> target/mips/cpu.c | 2 +- >>> target/moxie/cpu.c | 2 +- >>> target/nios2/cpu.c | 2 +- >>> target/openrisc/cpu.c | 2 +- >>> target/ppc/translate_init.c.inc | 2 +- >>> target/riscv/cpu.c | 2 +- >>> target/rx/cpu.c | 2 +- >>> target/s390x/cpu.c | 2 +- >>> target/sh4/cpu.c | 2 +- >>> target/sparc/cpu.c | 2 +- >>> target/tilegx/cpu.c | 2 +- >>> target/tricore/cpu.c | 2 +- >>> target/unicore32/cpu.c | 2 +- >>> target/xtensa/cpu.c | 2 +- >>> 27 files changed, 41 insertions(+), 38 deletions(-) >> >> With cc->tcg_ops.* guarded with #ifdef CONFIG_TCG: >> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> > > Thanks! > > Are the #ifdefs a hard condition for your Reviewed-by? > > Even if we agree #ifdef CONFIG_TCG is the way to go, I don't > think this should block a series that's a step in the right > direction. It can be done in a separate patch. > > (Unless the lack of #ifdef introduces regressions, of course) > Hi, I would add ifdefs to all targets that are not TCG-only (for now). If a target is tcg-only, there is of course no point in adding ifdefs. For the others, the ifdefs is something that helps us reorg the code into separate blocks, and then we can move them to separate .c files and remove the ifdefs. Ciao, Claudio
On 12/4/20 7:00 PM, Philippe Mathieu-Daudé wrote: > On 12/4/20 6:37 PM, Eduardo Habkost wrote: >> On Fri, Dec 04, 2020 at 06:14:07PM +0100, Philippe Mathieu-Daudé wrote: >>> On 11/30/20 3:35 AM, Claudio Fontana wrote: >>>> From: Eduardo Habkost <ehabkost@redhat.com> >>>> >>>> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> >>>> --- >>>> accel/tcg/cputlb.c | 6 +++--- >>>> accel/tcg/user-exec.c | 6 +++--- >>>> include/hw/core/cpu.h | 9 --------- >>>> include/hw/core/tcg-cpu-ops.h | 12 ++++++++++++ >>>> target/alpha/cpu.c | 2 +- >>>> target/arm/cpu.c | 2 +- >>>> target/avr/cpu.c | 2 +- >>>> target/cris/cpu.c | 2 +- >>>> target/hppa/cpu.c | 2 +- >>>> target/i386/tcg-cpu.c | 2 +- >>>> target/lm32/cpu.c | 2 +- >>>> target/m68k/cpu.c | 2 +- >>>> target/microblaze/cpu.c | 2 +- >>>> target/mips/cpu.c | 2 +- >>>> target/moxie/cpu.c | 2 +- >>>> target/nios2/cpu.c | 2 +- >>>> target/openrisc/cpu.c | 2 +- >>>> target/ppc/translate_init.c.inc | 2 +- >>>> target/riscv/cpu.c | 2 +- >>>> target/rx/cpu.c | 2 +- >>>> target/s390x/cpu.c | 2 +- >>>> target/sh4/cpu.c | 2 +- >>>> target/sparc/cpu.c | 2 +- >>>> target/tilegx/cpu.c | 2 +- >>>> target/tricore/cpu.c | 2 +- >>>> target/unicore32/cpu.c | 2 +- >>>> target/xtensa/cpu.c | 2 +- >>>> 27 files changed, 41 insertions(+), 38 deletions(-) >>> >>> With cc->tcg_ops.* guarded with #ifdef CONFIG_TCG: >>> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> >> >> Thanks! >> >> Are the #ifdefs a hard condition for your Reviewed-by? > > No, as you said, this is fine as a first step, so you can > include them. > >> Even if we agree #ifdef CONFIG_TCG is the way to go, I don't >> think this should block a series that's a step in the right >> direction. It can be done in a separate patch. >> >> (Unless the lack of #ifdef introduces regressions, of course) > > I'm worried about the +system -tcg build configuration. > > s390x is the only target testing for such regressions > (see "[s390x] Clang (disable-tcg)" on Travis-CI. > which exact configure options are concerned about? --disable-tcg --enable-kvm --target="*-system"? Or something else? this is something I am testing (and found the issues). I am currently testing (and a result fixing) for each patch: --disable-tcg --enable-kvm --enable-tcg --disable-kvm --enable-tcg --enable-kvm --enable-hax --disable-system With targets (when compatible): TARGET_LIST="x86_64-softmmu,x86_64-linux-user,arm-softmmu,arm-linux-user,aarch64-softmmu,aarch64-linux-user,s390x-softmmu,s390x-linux-user" and yes, should offload much of this to CI.. Ciao, Claudio
On 12/4/20 7:14 PM, Claudio Fontana wrote: > On 12/4/20 7:00 PM, Philippe Mathieu-Daudé wrote: >> On 12/4/20 6:37 PM, Eduardo Habkost wrote: >>> On Fri, Dec 04, 2020 at 06:14:07PM +0100, Philippe Mathieu-Daudé wrote: >>>> On 11/30/20 3:35 AM, Claudio Fontana wrote: >>>>> From: Eduardo Habkost <ehabkost@redhat.com> >>>>> >>>>> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> >>>>> --- >>>>> accel/tcg/cputlb.c | 6 +++--- >>>>> accel/tcg/user-exec.c | 6 +++--- >>>>> include/hw/core/cpu.h | 9 --------- >>>>> include/hw/core/tcg-cpu-ops.h | 12 ++++++++++++ >>>>> target/alpha/cpu.c | 2 +- >>>>> target/arm/cpu.c | 2 +- >>>>> target/avr/cpu.c | 2 +- >>>>> target/cris/cpu.c | 2 +- >>>>> target/hppa/cpu.c | 2 +- >>>>> target/i386/tcg-cpu.c | 2 +- >>>>> target/lm32/cpu.c | 2 +- >>>>> target/m68k/cpu.c | 2 +- >>>>> target/microblaze/cpu.c | 2 +- >>>>> target/mips/cpu.c | 2 +- >>>>> target/moxie/cpu.c | 2 +- >>>>> target/nios2/cpu.c | 2 +- >>>>> target/openrisc/cpu.c | 2 +- >>>>> target/ppc/translate_init.c.inc | 2 +- >>>>> target/riscv/cpu.c | 2 +- >>>>> target/rx/cpu.c | 2 +- >>>>> target/s390x/cpu.c | 2 +- >>>>> target/sh4/cpu.c | 2 +- >>>>> target/sparc/cpu.c | 2 +- >>>>> target/tilegx/cpu.c | 2 +- >>>>> target/tricore/cpu.c | 2 +- >>>>> target/unicore32/cpu.c | 2 +- >>>>> target/xtensa/cpu.c | 2 +- >>>>> 27 files changed, 41 insertions(+), 38 deletions(-) >>>> >>>> With cc->tcg_ops.* guarded with #ifdef CONFIG_TCG: >>>> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> >>> >>> Thanks! >>> >>> Are the #ifdefs a hard condition for your Reviewed-by? >> >> No, as you said, this is fine as a first step, so you can >> include them. >> >>> Even if we agree #ifdef CONFIG_TCG is the way to go, I don't >>> think this should block a series that's a step in the right >>> direction. It can be done in a separate patch. >>> >>> (Unless the lack of #ifdef introduces regressions, of course) >> >> I'm worried about the +system -tcg build configuration. >> >> s390x is the only target testing for such regressions >> (see "[s390x] Clang (disable-tcg)" on Travis-CI. >> > > which exact configure options are concerned about? > > --disable-tcg --enable-kvm --target="*-system"? > > Or something else? Basically --disable-tcg --enable-$ACCEL [--enable-$ACCEL] > > this is something I am testing (and found the issues). > > I am currently testing (and a result fixing) for each patch: > > --disable-tcg --enable-kvm This one is meaningful to check the host, so I run it on: - x86 [ok] - s390x [ok] - aarch64 [done, waiting for your effort before respining] - ppc64 [done, I was postponing the series submission waiting for aa64 to be merged, but I might go back to it as aa64 is taking too long]. - mips: no hardware access > --enable-tcg --disable-kvm > --enable-tcg --enable-kvm --enable-hax > --disable-system I also use: * --disable-tcg --disable-kvm --enable-xen [x86 host works] [aa64 host needs Alex Bennée patches] * --disable-tcg --disable-system --disable-user --enable-tools * --disable-system --static --disable-capstone (experimental, not supported, don't waste time with it). The most useful is --enable-tools with all accelerators disabled, as it quickly triggers linking errors when you miss-place a handler between #ifdefs. > With targets (when compatible): > TARGET_LIST="x86_64-softmmu,x86_64-linux-user,arm-softmmu,arm-linux-user,aarch64-softmmu,aarch64-linux-user,s390x-softmmu,s390x-linux-user" "first class KVM users" include PPC64 too. > > and yes, should offload much of this to CI.. > > Ciao, > > Claudio >
On 12/4/20 8:27 PM, Philippe Mathieu-Daudé wrote: > On 12/4/20 7:14 PM, Claudio Fontana wrote: >> On 12/4/20 7:00 PM, Philippe Mathieu-Daudé wrote: >>> On 12/4/20 6:37 PM, Eduardo Habkost wrote: >>>> On Fri, Dec 04, 2020 at 06:14:07PM +0100, Philippe Mathieu-Daudé wrote: >>>>> On 11/30/20 3:35 AM, Claudio Fontana wrote: >>>>>> From: Eduardo Habkost <ehabkost@redhat.com> >>>>>> >>>>>> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> >>>>>> --- >>>>>> accel/tcg/cputlb.c | 6 +++--- >>>>>> accel/tcg/user-exec.c | 6 +++--- >>>>>> include/hw/core/cpu.h | 9 --------- >>>>>> include/hw/core/tcg-cpu-ops.h | 12 ++++++++++++ >>>>>> target/alpha/cpu.c | 2 +- >>>>>> target/arm/cpu.c | 2 +- >>>>>> target/avr/cpu.c | 2 +- >>>>>> target/cris/cpu.c | 2 +- >>>>>> target/hppa/cpu.c | 2 +- >>>>>> target/i386/tcg-cpu.c | 2 +- >>>>>> target/lm32/cpu.c | 2 +- >>>>>> target/m68k/cpu.c | 2 +- >>>>>> target/microblaze/cpu.c | 2 +- >>>>>> target/mips/cpu.c | 2 +- >>>>>> target/moxie/cpu.c | 2 +- >>>>>> target/nios2/cpu.c | 2 +- >>>>>> target/openrisc/cpu.c | 2 +- >>>>>> target/ppc/translate_init.c.inc | 2 +- >>>>>> target/riscv/cpu.c | 2 +- >>>>>> target/rx/cpu.c | 2 +- >>>>>> target/s390x/cpu.c | 2 +- >>>>>> target/sh4/cpu.c | 2 +- >>>>>> target/sparc/cpu.c | 2 +- >>>>>> target/tilegx/cpu.c | 2 +- >>>>>> target/tricore/cpu.c | 2 +- >>>>>> target/unicore32/cpu.c | 2 +- >>>>>> target/xtensa/cpu.c | 2 +- >>>>>> 27 files changed, 41 insertions(+), 38 deletions(-) >>>>> >>>>> With cc->tcg_ops.* guarded with #ifdef CONFIG_TCG: >>>>> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> >>>> >>>> Thanks! >>>> >>>> Are the #ifdefs a hard condition for your Reviewed-by? >>> >>> No, as you said, this is fine as a first step, so you can >>> include them. >>> >>>> Even if we agree #ifdef CONFIG_TCG is the way to go, I don't >>>> think this should block a series that's a step in the right >>>> direction. It can be done in a separate patch. >>>> >>>> (Unless the lack of #ifdef introduces regressions, of course) >>> >>> I'm worried about the +system -tcg build configuration. >>> >>> s390x is the only target testing for such regressions >>> (see "[s390x] Clang (disable-tcg)" on Travis-CI. >>> >> >> which exact configure options are concerned about? >> >> --disable-tcg --enable-kvm --target="*-system"? >> >> Or something else? > > Basically --disable-tcg --enable-$ACCEL [--enable-$ACCEL] > >> >> this is something I am testing (and found the issues). >> >> I am currently testing (and a result fixing) for each patch: >> >> --disable-tcg --enable-kvm > > This one is meaningful to check the host, so I run it on: > - x86 [ok] > - s390x [ok] > - aarch64 [done, waiting for your effort before respining] > - ppc64 [done, I was postponing the series submission waiting > for aa64 to be merged, but I might go back to it as > aa64 is taking too long]. > - mips: no hardware access > >> --enable-tcg --disable-kvm >> --enable-tcg --enable-kvm --enable-hax >> --disable-system > > I also use: > > * --disable-tcg --disable-kvm --enable-xen > [x86 host works] > [aa64 host needs Alex Bennée patches] > > * --disable-tcg --disable-system --disable-user --enable-tools > > * --disable-system --static --disable-capstone > (experimental, not supported, don't waste time with it). > > The most useful is --enable-tools with all accelerators disabled, > as it quickly triggers linking errors when you miss-place a > handler between #ifdefs. Hi, seems good, however if I configure with --disable-tcg --disable-kvm --disable-hax --enable-tools make works fine, while make check errors out with 'qemu' not found. Running test fp-test-rem Running test fp-test-sqrt Running test QAPI schema regression tests check: qemu not found make: *** [/dev/shm/cfontana/qemu/tests/Makefile.include:144: check-block] Error 1 make: *** Waiting for unfinished jobs.... Maybe something to improve in the build system? I'd expect only the tools check to run (if any), if only tools are built... Thanks, Ciao Claudio > >> With targets (when compatible): >> TARGET_LIST="x86_64-softmmu,x86_64-linux-user,arm-softmmu,arm-linux-user,aarch64-softmmu,aarch64-linux-user,s390x-softmmu,s390x-linux-user" > > "first class KVM users" include PPC64 too. > >> >> and yes, should offload much of this to CI.. >> >> Ciao, >> >> Claudio >> > >
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 42ab79c1a5..2dc71b5528 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1286,7 +1286,7 @@ static void tlb_fill(CPUState *cpu, target_ulong addr, int size, * This is not a probe, so only valid return is success; failure * should result in exception + longjmp to the cpu loop. */ - ok = cc->tlb_fill(cpu, addr, size, access_type, mmu_idx, false, retaddr); + ok = cc->tcg_ops.tlb_fill(cpu, addr, size, access_type, mmu_idx, false, retaddr); assert(ok); } @@ -1557,8 +1557,8 @@ static int probe_access_internal(CPUArchState *env, target_ulong addr, CPUState *cs = env_cpu(env); CPUClass *cc = CPU_GET_CLASS(cs); - if (!cc->tlb_fill(cs, addr, fault_size, access_type, - mmu_idx, nonfault, retaddr)) { + if (!cc->tcg_ops.tlb_fill(cs, addr, fault_size, access_type, + mmu_idx, nonfault, retaddr)) { /* Non-faulting page table read failed. */ *phost = NULL; return TLB_INVALID_MASK; diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 4ebe25461a..7f53992251 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -186,7 +186,7 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, clear_helper_retaddr(); cc = CPU_GET_CLASS(cpu); - cc->tlb_fill(cpu, address, 0, access_type, MMU_USER_IDX, false, pc); + cc->tcg_ops.tlb_fill(cpu, address, 0, access_type, MMU_USER_IDX, false, pc); g_assert_not_reached(); } @@ -216,8 +216,8 @@ static int probe_access_internal(CPUArchState *env, target_ulong addr, } else { CPUState *cpu = env_cpu(env); CPUClass *cc = CPU_GET_CLASS(cpu); - cc->tlb_fill(cpu, addr, fault_size, access_type, - MMU_USER_IDX, false, ra); + cc->tcg_ops.tlb_fill(cpu, addr, fault_size, access_type, + MMU_USER_IDX, false, ra); g_assert_not_reached(); } } diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 538f3e6cd3..67cc147aae 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -110,12 +110,6 @@ struct TranslationBlock; * If the target behaviour here is anything other than "set * the PC register to the value passed in" then the target must * also implement the synchronize_from_tb hook. - * @tlb_fill: Callback for handling a softmmu tlb miss or user-only - * address fault. For system mode, if the access is valid, call - * tlb_set_page and return true; if the access is invalid, and - * probe is true, return false; otherwise raise an exception and - * do not return. For user-only mode, always raise an exception - * and do not return. * @get_phys_page_debug: Callback for obtaining a physical address. * @get_phys_page_attrs_debug: Callback for obtaining a physical address and the * associated memory transaction attributes to use for the access. @@ -183,9 +177,6 @@ struct CPUClass { void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, Error **errp); void (*set_pc)(CPUState *cpu, vaddr value); - bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, MemTxAttrs *attrs); diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index e12f32919b..2ea94acca0 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -37,6 +37,18 @@ typedef struct TcgCpuOperations { void (*cpu_exec_exit)(CPUState *cpu); /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */ bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); + /** + * @tlb_fill: Handle a softmmu tlb miss or user-only address fault + * + * For system mode, if the access is valid, call tlb_set_page + * and return true; if the access is invalid, and probe is + * true, return false; otherwise raise an exception and do + * not return. For user-only mode, always raise an exception + * and do not return. + */ + bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); } TcgCpuOperations; #endif /* TCG_CPU_OPS_H */ diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 4f206c154d..0369d5a99c 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -222,7 +222,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data) cc->set_pc = alpha_cpu_set_pc; cc->gdb_read_register = alpha_cpu_gdb_read_register; cc->gdb_write_register = alpha_cpu_gdb_write_register; - cc->tlb_fill = alpha_cpu_tlb_fill; + cc->tcg_ops.tlb_fill = alpha_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->do_transaction_failed = alpha_cpu_do_transaction_failed; cc->do_unaligned_access = alpha_cpu_do_unaligned_access; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index d72a123527..f117ae4b2d 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2262,7 +2262,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) cc->disas_set_info = arm_disas_set_info; #ifdef CONFIG_TCG cc->tcg_ops.initialize = arm_translate_init; - cc->tlb_fill = arm_cpu_tlb_fill; + cc->tcg_ops.tlb_fill = arm_cpu_tlb_fill; cc->debug_excp_handler = arm_debug_excp_handler; cc->debug_check_watchpoint = arm_debug_check_watchpoint; cc->do_unaligned_access = arm_cpu_do_unaligned_access; diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 277b00dbfc..699055de7c 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -203,7 +203,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data) cc->set_pc = avr_cpu_set_pc; cc->memory_rw_debug = avr_cpu_memory_rw_debug; cc->get_phys_page_debug = avr_cpu_get_phys_page_debug; - cc->tlb_fill = avr_cpu_tlb_fill; + cc->tcg_ops.tlb_fill = avr_cpu_tlb_fill; cc->vmsd = &vms_avr_cpu; cc->disas_set_info = avr_cpu_disas_set_info; cc->tcg_ops.initialize = avr_cpu_tcg_init; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 7489fc20c8..9222717f3e 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -274,7 +274,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data) cc->set_pc = cris_cpu_set_pc; cc->gdb_read_register = cris_cpu_gdb_read_register; cc->gdb_write_register = cris_cpu_gdb_write_register; - cc->tlb_fill = cris_cpu_tlb_fill; + cc->tcg_ops.tlb_fill = cris_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug = cris_cpu_get_phys_page_debug; dc->vmsd = &vmstate_cris_cpu; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 61444753f2..e2d79f954e 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -146,7 +146,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data) cc->tcg_ops.synchronize_from_tb = hppa_cpu_synchronize_from_tb; cc->gdb_read_register = hppa_cpu_gdb_read_register; cc->gdb_write_register = hppa_cpu_gdb_write_register; - cc->tlb_fill = hppa_cpu_tlb_fill; + cc->tcg_ops.tlb_fill = hppa_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug; dc->vmsd = &vmstate_hppa_cpu; diff --git a/target/i386/tcg-cpu.c b/target/i386/tcg-cpu.c index 5e0f2a2fae..8606dd6a3e 100644 --- a/target/i386/tcg-cpu.c +++ b/target/i386/tcg-cpu.c @@ -64,7 +64,7 @@ void tcg_cpu_common_class_init(CPUClass *cc) cc->tcg_ops.cpu_exec_enter = x86_cpu_exec_enter; cc->tcg_ops.cpu_exec_exit = x86_cpu_exec_exit; cc->tcg_ops.initialize = tcg_x86_init; - cc->tlb_fill = x86_cpu_tlb_fill; + cc->tcg_ops.tlb_fill = x86_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->debug_excp_handler = breakpoint_handler; #endif diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index eea2d3e515..76dc728858 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -228,7 +228,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data) cc->set_pc = lm32_cpu_set_pc; cc->gdb_read_register = lm32_cpu_gdb_read_register; cc->gdb_write_register = lm32_cpu_gdb_write_register; - cc->tlb_fill = lm32_cpu_tlb_fill; + cc->tcg_ops.tlb_fill = lm32_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug; cc->vmsd = &vmstate_lm32_cpu; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index c0fa517fc3..bc109faa21 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -283,7 +283,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data) cc->set_pc = m68k_cpu_set_pc; cc->gdb_read_register = m68k_cpu_gdb_read_register; cc->gdb_write_register = m68k_cpu_gdb_write_register; - cc->tlb_fill = m68k_cpu_tlb_fill; + cc->tcg_ops.tlb_fill = m68k_cpu_tlb_fill; #if defined(CONFIG_SOFTMMU) cc->do_transaction_failed = m68k_cpu_transaction_failed; cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 833d7f2d59..6e660a27b8 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -325,7 +325,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data) cc->tcg_ops.synchronize_from_tb = mb_cpu_synchronize_from_tb; cc->gdb_read_register = mb_cpu_gdb_read_register; cc->gdb_write_register = mb_cpu_gdb_write_register; - cc->tlb_fill = mb_cpu_tlb_fill; + cc->tcg_ops.tlb_fill = mb_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->do_transaction_failed = mb_cpu_transaction_failed; cc->get_phys_page_debug = mb_cpu_get_phys_page_debug; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 4028d6a4ae..02fae64ce7 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -250,7 +250,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data) cc->disas_set_info = mips_cpu_disas_set_info; #ifdef CONFIG_TCG cc->tcg_ops.initialize = mips_tcg_init; - cc->tlb_fill = mips_cpu_tlb_fill; + cc->tcg_ops.tlb_fill = mips_cpu_tlb_fill; #endif cc->gdb_num_core_regs = 73; diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index 224cfc8361..1177d092c1 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -110,7 +110,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data) cc->do_interrupt = moxie_cpu_do_interrupt; cc->dump_state = moxie_cpu_dump_state; cc->set_pc = moxie_cpu_set_pc; - cc->tlb_fill = moxie_cpu_tlb_fill; + cc->tcg_ops.tlb_fill = moxie_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug = moxie_cpu_get_phys_page_debug; cc->vmsd = &vmstate_moxie_cpu; diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 9eeb01fb5b..a96b74b00c 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -197,7 +197,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data) cc->dump_state = nios2_cpu_dump_state; cc->set_pc = nios2_cpu_set_pc; cc->disas_set_info = nios2_cpu_disas_set_info; - cc->tlb_fill = nios2_cpu_tlb_fill; + cc->tcg_ops.tlb_fill = nios2_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->do_unaligned_access = nios2_cpu_do_unaligned_access; cc->get_phys_page_debug = nios2_cpu_get_phys_page_debug; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index df8a41f956..e6d1c9764b 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -160,7 +160,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data) cc->set_pc = openrisc_cpu_set_pc; cc->gdb_read_register = openrisc_cpu_gdb_read_register; cc->gdb_write_register = openrisc_cpu_gdb_write_register; - cc->tlb_fill = openrisc_cpu_tlb_fill; + cc->tcg_ops.tlb_fill = openrisc_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug; dc->vmsd = &vmstate_openrisc_cpu; diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc index 2d7f70d2ba..e6426a96b5 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10946,7 +10946,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data) #endif #ifdef CONFIG_TCG cc->tcg_ops.initialize = ppc_translate_init; - cc->tlb_fill = ppc_cpu_tlb_fill; + cc->tcg_ops.tlb_fill = ppc_cpu_tlb_fill; #endif #ifndef CONFIG_USER_ONLY cc->tcg_ops.cpu_exec_enter = ppc_cpu_exec_enter; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 97dbe1a08c..022b4271d4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -563,7 +563,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) #endif #ifdef CONFIG_TCG cc->tcg_ops.initialize = riscv_translate_init; - cc->tlb_fill = riscv_cpu_tlb_fill; + cc->tcg_ops.tlb_fill = riscv_cpu_tlb_fill; #endif device_class_set_props(dc, riscv_cpu_properties); } diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 3ba93590d2..c815533223 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -195,7 +195,7 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data) cc->get_phys_page_debug = rx_cpu_get_phys_page_debug; cc->disas_set_info = rx_cpu_disas_set_info; cc->tcg_ops.initialize = rx_translate_init; - cc->tlb_fill = rx_cpu_tlb_fill; + cc->tcg_ops.tlb_fill = rx_cpu_tlb_fill; cc->gdb_num_core_regs = 26; cc->gdb_core_xml_file = "rx-core.xml"; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index add2f4b21f..6cd2b30192 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -513,7 +513,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data) cc->disas_set_info = s390_cpu_disas_set_info; #ifdef CONFIG_TCG cc->tcg_ops.initialize = s390x_translate_init; - cc->tlb_fill = s390_cpu_tlb_fill; + cc->tcg_ops.tlb_fill = s390_cpu_tlb_fill; #endif cc->gdb_num_core_regs = S390_NUM_CORE_REGS; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 0574194cd0..7a9019edec 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -225,7 +225,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data) cc->tcg_ops.synchronize_from_tb = superh_cpu_synchronize_from_tb; cc->gdb_read_register = superh_cpu_gdb_read_register; cc->gdb_write_register = superh_cpu_gdb_write_register; - cc->tlb_fill = superh_cpu_tlb_fill; + cc->tcg_ops.tlb_fill = superh_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->do_unaligned_access = superh_cpu_do_unaligned_access; cc->get_phys_page_debug = superh_cpu_get_phys_page_debug; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index c559f15e14..760e0ea92c 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -871,7 +871,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data) cc->tcg_ops.synchronize_from_tb = sparc_cpu_synchronize_from_tb; cc->gdb_read_register = sparc_cpu_gdb_read_register; cc->gdb_write_register = sparc_cpu_gdb_write_register; - cc->tlb_fill = sparc_cpu_tlb_fill; + cc->tcg_ops.tlb_fill = sparc_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->do_transaction_failed = sparc_cpu_do_transaction_failed; cc->do_unaligned_access = sparc_cpu_do_unaligned_access; diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c index 4c6176d26e..75b3a4bae3 100644 --- a/target/tilegx/cpu.c +++ b/target/tilegx/cpu.c @@ -151,7 +151,7 @@ static void tilegx_cpu_class_init(ObjectClass *oc, void *data) cc->tcg_ops.cpu_exec_interrupt = tilegx_cpu_exec_interrupt; cc->dump_state = tilegx_cpu_dump_state; cc->set_pc = tilegx_cpu_set_pc; - cc->tlb_fill = tilegx_cpu_tlb_fill; + cc->tcg_ops.tlb_fill = tilegx_cpu_tlb_fill; cc->gdb_num_core_regs = 0; cc->tcg_ops.initialize = tilegx_tcg_init; } diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 5edf96c600..89a14f81d7 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -165,7 +165,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data) cc->tcg_ops.synchronize_from_tb = tricore_cpu_synchronize_from_tb; cc->get_phys_page_debug = tricore_cpu_get_phys_page_debug; cc->tcg_ops.initialize = tricore_tcg_init; - cc->tlb_fill = tricore_cpu_tlb_fill; + cc->tcg_ops.tlb_fill = tricore_cpu_tlb_fill; } #define DEFINE_TRICORE_CPU_TYPE(cpu_model, initfn) \ diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index 84c3419989..a57d315d2f 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -135,7 +135,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data) cc->tcg_ops.cpu_exec_interrupt = uc32_cpu_exec_interrupt; cc->dump_state = uc32_cpu_dump_state; cc->set_pc = uc32_cpu_set_pc; - cc->tlb_fill = uc32_cpu_tlb_fill; + cc->tcg_ops.tlb_fill = uc32_cpu_tlb_fill; cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug; cc->tcg_ops.initialize = uc32_translate_init; dc->vmsd = &vmstate_uc32_cpu; diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 42a5e4ebe8..e764dbeb73 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -201,7 +201,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data) cc->gdb_read_register = xtensa_cpu_gdb_read_register; cc->gdb_write_register = xtensa_cpu_gdb_write_register; cc->gdb_stop_before_watchpoint = true; - cc->tlb_fill = xtensa_cpu_tlb_fill; + cc->tcg_ops.tlb_fill = xtensa_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->do_unaligned_access = xtensa_cpu_do_unaligned_access; cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;