diff mbox series

[3/3] riscv: Complete efi header for RV32/64

Message ID 20201117080657.GA9968@andestech.com
State Accepted
Commit 9afaeec6ef8bbc6cf936d2a9c3d28caffca5bf7e
Delegated to: Andes
Headers show
Series Complete Optional Header fields in EFI header | expand

Commit Message

Leo Liang Nov. 17, 2020, 8:07 a.m. UTC
Date: Mon, 16 Nov 2020 17:07:41 +0800
From: Leo Yu-Chi Liang <ycliang@andestech.com>
Subject: [PATCH 3/3] riscv: Complete efi header for RV32/64

This patch depends on Atish's patch.
(https://patchwork.ozlabs.org/project/uboot/patch/20201013192331.3236458-1-atish.patra@wdc.com/)

Add fields to complete Optional Header "Data Directories" specified in the document.
(https://docs.microsoft.com/en-us/windows/win32/debug/pe-format)

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Cc: rick@andestech.com
Cc: alankao@andestech.com
Cc: atish.patra@wdc.com
Cc: xypron.glpk@gmx.de
Cc: bmeng.cn@gmail.com
---
 arch/riscv/lib/crt0_riscv_efi.S | 10 ++++++++++
 1 file changed, 10 insertions(+)

Comments

Heinrich Schuchardt Nov. 18, 2020, 3:47 p.m. UTC | #1
On 17.11.20 09:07, Leo Liang wrote:
> Date: Mon, 16 Nov 2020 17:07:41 +0800
> From: Leo Yu-Chi Liang <ycliang@andestech.com>
> Subject: [PATCH 3/3] riscv: Complete efi header for RV32/64
>
> This patch depends on Atish's patch.
> (https://patchwork.ozlabs.org/project/uboot/patch/20201013192331.3236458-1-atish.patra@wdc.com/)
>
> Add fields to complete Optional Header "Data Directories" specified in the document.
> (https://docs.microsoft.com/en-us/windows/win32/debug/pe-format)
>
> Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>

Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>

> Cc: rick@andestech.com
> Cc: alankao@andestech.com
> Cc: atish.patra@wdc.com
> Cc: xypron.glpk@gmx.de
> Cc: bmeng.cn@gmail.com
> ---
>  arch/riscv/lib/crt0_riscv_efi.S | 10 ++++++++++
>  1 file changed, 10 insertions(+)
>
> diff --git a/arch/riscv/lib/crt0_riscv_efi.S b/arch/riscv/lib/crt0_riscv_efi.S
> index 48ff89553b..e7c4d99c21 100644
> --- a/arch/riscv/lib/crt0_riscv_efi.S
> +++ b/arch/riscv/lib/crt0_riscv_efi.S
> @@ -107,6 +107,16 @@ extra_header_fields:
>  	.quad	0				/* ExceptionTable */
>  	.quad	0				/* CertificationTable */
>  	.quad	0				/* BaseRelocationTable */
> +	.quad	0				/* Debug */
> +	.quad	0				/* Architecture */
> +	.quad	0				/* Global Ptr */
> +	.quad	0				/* TLS Table */
> +	.quad	0				/* Load Config Table */
> +	.quad	0				/* Bound Import */
> +	.quad	0				/* IAT */
> +	.quad	0				/* Delay Import Descriptor */
> +	.quad	0				/* CLR Runtime Header */
> +	.quad	0				/* Reserved */
>
>  	/* Section table */
>  section_table:
>
Atish Patra Nov. 23, 2020, 4:59 p.m. UTC | #2
On Tue, Nov 17, 2020 at 12:07 AM Leo Liang <ycliang@andestech.com> wrote:
>
> Date: Mon, 16 Nov 2020 17:07:41 +0800
> From: Leo Yu-Chi Liang <ycliang@andestech.com>
> Subject: [PATCH 3/3] riscv: Complete efi header for RV32/64
>
> This patch depends on Atish's patch.
> (https://patchwork.ozlabs.org/project/uboot/patch/20201013192331.3236458-1-atish.patra@wdc.com/)
>
> Add fields to complete Optional Header "Data Directories" specified in the document.
> (https://docs.microsoft.com/en-us/windows/win32/debug/pe-format)
>
> Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
> Cc: rick@andestech.com
> Cc: alankao@andestech.com
> Cc: atish.patra@wdc.com
> Cc: xypron.glpk@gmx.de
> Cc: bmeng.cn@gmail.com
> ---
>  arch/riscv/lib/crt0_riscv_efi.S | 10 ++++++++++
>  1 file changed, 10 insertions(+)
>
> diff --git a/arch/riscv/lib/crt0_riscv_efi.S b/arch/riscv/lib/crt0_riscv_efi.S
> index 48ff89553b..e7c4d99c21 100644
> --- a/arch/riscv/lib/crt0_riscv_efi.S
> +++ b/arch/riscv/lib/crt0_riscv_efi.S
> @@ -107,6 +107,16 @@ extra_header_fields:
>         .quad   0                               /* ExceptionTable */
>         .quad   0                               /* CertificationTable */
>         .quad   0                               /* BaseRelocationTable */
> +       .quad   0                               /* Debug */
> +       .quad   0                               /* Architecture */
> +       .quad   0                               /* Global Ptr */
> +       .quad   0                               /* TLS Table */
> +       .quad   0                               /* Load Config Table */
> +       .quad   0                               /* Bound Import */
> +       .quad   0                               /* IAT */
> +       .quad   0                               /* Delay Import Descriptor */
> +       .quad   0                               /* CLR Runtime Header */
> +       .quad   0                               /* Reserved */
>
>         /* Section table */
>  section_table:
> --
> 2.17.0


Reviewed-by: Atish Patra <atish.patra@wdc.com>
diff mbox series

Patch

diff --git a/arch/riscv/lib/crt0_riscv_efi.S b/arch/riscv/lib/crt0_riscv_efi.S
index 48ff89553b..e7c4d99c21 100644
--- a/arch/riscv/lib/crt0_riscv_efi.S
+++ b/arch/riscv/lib/crt0_riscv_efi.S
@@ -107,6 +107,16 @@  extra_header_fields:
 	.quad	0				/* ExceptionTable */
 	.quad	0				/* CertificationTable */
 	.quad	0				/* BaseRelocationTable */
+	.quad	0				/* Debug */
+	.quad	0				/* Architecture */
+	.quad	0				/* Global Ptr */
+	.quad	0				/* TLS Table */
+	.quad	0				/* Load Config Table */
+	.quad	0				/* Bound Import */
+	.quad	0				/* IAT */
+	.quad	0				/* Delay Import Descriptor */
+	.quad	0				/* CLR Runtime Header */
+	.quad	0				/* Reserved */
 
 	/* Section table */
 section_table: