| Message ID | 20201116171159.1735315-1-gregory.clement@bootlin.com |
|---|---|
| Headers | show |
| Series | Improve reset for ocelot and add support for new platfrom | expand |
Hi, On 16/11/2020 18:11:58+0100, Gregory CLEMENT wrote: > This adds reset support for Luton and Jaguar2 in the ocelot-reset > driver. They are both MIPS based belonging to the VvoreIII family. > > Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> > --- > drivers/power/reset/ocelot-reset.c | 30 +++++++++++++++++++++++++++--- > 1 file changed, 27 insertions(+), 3 deletions(-) > > diff --git a/drivers/power/reset/ocelot-reset.c b/drivers/power/reset/ocelot-reset.c > index a203c42e99d4..0f92416f2907 100644 > --- a/drivers/power/reset/ocelot-reset.c > +++ b/drivers/power/reset/ocelot-reset.c > @@ -29,6 +29,8 @@ struct ocelot_reset_context { > struct notifier_block restart_handler; > }; > > +#define BIT_OFF_INVALID 32 > + > #define SOFT_SWC_RST BIT(1) > #define SOFT_CHIP_RST BIT(0) > > @@ -77,9 +79,11 @@ static int ocelot_restart_handle(struct notifier_block *this, > ctx->props->vcore_protect, 0); > > /* Make the SI back to boot mode */ > - regmap_update_bits(ctx->cpu_ctrl, ICPU_CFG_CPU_SYSTEM_CTRL_GENERAL_CTRL, > - IF_SI_OWNER_MASK << if_si_owner_bit, > - IF_SI_OWNER_SIBM << if_si_owner_bit); > + if (if_si_owner_bit != BIT_OFF_INVALID) > + regmap_update_bits(ctx->cpu_ctrl, > + ICPU_CFG_CPU_SYSTEM_CTRL_GENERAL_CTRL, > + IF_SI_OWNER_MASK << if_si_owner_bit, > + IF_SI_OWNER_SIBM << if_si_owner_bit); > > pr_emerg("Resetting SoC\n"); > > @@ -127,6 +131,20 @@ static int ocelot_reset_probe(struct platform_device *pdev) > return err; > } > > +static const struct reset_props reset_props_jaguar2 = { > + .syscon = "mscc,ocelot-cpu-syscon", > + .protect_reg = 0x20, > + .vcore_protect = BIT(2), > + .if_si_owner_bit = 6, > +}; > + > +static const struct reset_props reset_props_luton = { > + .syscon = "mscc,ocelot-cpu-syscon", > + .protect_reg = 0x20, > + .vcore_protect = BIT(2), > + .if_si_owner_bit = BIT_OFF_INVALID, /* n/a */ > +}; > + > static const struct reset_props reset_props_ocelot = { > .syscon = "mscc,ocelot-cpu-syscon", > .protect_reg = 0x20, > @@ -143,6 +161,12 @@ static const struct reset_props reset_props_sparx5 = { > > static const struct of_device_id ocelot_reset_of_match[] = { > { > + .compatible = "mscc,jaguar2-chip-reset", > + .data = &reset_props_jaguar2 > + }, { > + .compatible = "mscc,luton-chip-reset", > + .data = &reset_props_luton > + }, { These compatible strings are undocumented. Else, Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> > .compatible = "mscc,ocelot-chip-reset", > .data = &reset_props_ocelot > }, { > -- > 2.29.2 >
Hello, This series first adds new feature to the ocelot reset driver and then it extends its support for 2 other MIPS based SoCs: Luton and Jaguar 2. Patches 1, 2 and 4 should be merged through the reset subsystem, while the device tree changes in patches 3 and 5 should go through the mips subsystem. Gregory Gregory CLEMENT (3): MIPS: dts: mscc: add reset switch property power: reset: ocelot: Add support 2 othe MIPS based SoCs MIPS: dts: mscc: add reset support for Luton and Jaguar2 Lars Povlsen (2): dt-bindings: reset: ocelot: Add documentation for 'microchip,reset-switch-core' property power: reset: ocelot: Add support for reset switch on load time .../bindings/power/reset/ocelot-reset.txt | 6 ++ arch/mips/boot/dts/mscc/jaguar2.dtsi | 6 ++ arch/mips/boot/dts/mscc/luton.dtsi | 5 ++ arch/mips/boot/dts/mscc/ocelot.dtsi | 1 + drivers/power/reset/ocelot-reset.c | 70 +++++++++++++++++-- 5 files changed, 83 insertions(+), 5 deletions(-)