| Message ID | 20201107081420.60325-3-damien.lemoal@wdc.com |
|---|---|
| State | New |
| Headers | show |
| Series | RISC-V Kendryte K210 support improvments | expand |
On 11/7/20 3:13 AM, Damien Le Moal wrote: > Synopsis DesignWare DW_apb_ssi version 4 defines a 32-bit layout of > the ctrlr0 register for SPI masters. The layout of ctrlr0 is: > > | 31 .. 23 | 22 .. 21 | 20 .. 16 | > | other stuff | spi_frf | dfs_32 | > > | 15 .. 10 | 9 .. 8 | 7 .. 6 | 5 .. 4 | 3 .. 0 | > | other stuff | tmod | mode | frf | dfs | > > Th main difference of this layout with the 16-bits version is the data > frame format field which resides in bits 16..20 instead of bits 3..0. > > Introduce the DW SPI capability flag DW_SPI_CAP_DFS_32 to let a > platform signal that this layout is in use. Modify > dw_spi_update_config() to test this capability flag to set the data > frame format field at the correct register location. > > Suggested-by: Sean Anderson <seanga2@gmail.com> > Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> > --- > drivers/spi/spi-dw-core.c | 8 ++++++-- > drivers/spi/spi-dw.h | 9 +++++++++ > 2 files changed, 15 insertions(+), 2 deletions(-) > > diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c > index 2e50cc0a9291..841c85247f01 100644 > --- a/drivers/spi/spi-dw-core.c > +++ b/drivers/spi/spi-dw-core.c > @@ -311,8 +311,12 @@ void dw_spi_update_config(struct dw_spi *dws, struct spi_device *spi, > u32 speed_hz; > u16 clk_div; > > - /* CTRLR0[ 4/3: 0] Data Frame Size */ > - cr0 |= (cfg->dfs - 1); > + if (!(dws->caps & DW_SPI_CAP_DFS_32)) > + /* CTRLR0[ 4/3: 0] Data Frame Size */ > + cr0 |= (cfg->dfs - 1); > + else > + /* CTRLR0[20: 16] Data Frame Size */ > + cr0 |= (cfg->dfs - 1) << DWC_APB_CTRLR0_32_DFS_OFFSET; > > if (!(dws->caps & DW_SPI_CAP_DWC_SSI)) > /* CTRLR0[ 9:8] Transfer Mode */ > diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h > index faf40cb66498..48a11a51a407 100644 > --- a/drivers/spi/spi-dw.h > +++ b/drivers/spi/spi-dw.h > @@ -9,6 +9,7 @@ > #include <linux/io.h> > #include <linux/scatterlist.h> > #include <linux/spi/spi-mem.h> > +#include <linux/bitfield.h> > > /* Register offsets */ > #define DW_SPI_CTRLR0 0x00 > @@ -72,6 +73,13 @@ > #define DWC_SSI_CTRLR0_FRF_OFFSET 6 > #define DWC_SSI_CTRLR0_DFS_OFFSET 0 > > +/* > + * Bit fields in CTRLR0 for DWC_apb_ssi v4 32-bits ctrlr0. > + * Based on DW_apb_ssi Databook v4.02a. > + */ > +#define DWC_APB_CTRLR0_32_DFS_OFFSET 16 > +#define DWC_APB_CTRLR0_32_DFS_MASK GENMASK(20, 16) > + > /* > * For Keem Bay, CTRLR0[31] is used to select controller mode. > * 0: SSI is slave > @@ -121,6 +129,7 @@ enum dw_ssi_type { > #define DW_SPI_CAP_CS_OVERRIDE BIT(0) > #define DW_SPI_CAP_KEEMBAY_MST BIT(1) > #define DW_SPI_CAP_DWC_SSI BIT(2) > +#define DW_SPI_CAP_DFS_32 BIT(3) > > /* Slave spi_transfer/spi_mem_op related */ > struct dw_spi_cfg { > Reviewed-by: Sean Anderson <seanga2@gmail.com>
Hello Damien, Thanks for your patches. My comments are below. On Sat, Nov 07, 2020 at 05:13:50PM +0900, Damien Le Moal wrote: > Synopsis DesignWare DW_apb_ssi version 4 defines a 32-bit layout of > the ctrlr0 register for SPI masters. The layout of ctrlr0 is: > > | 31 .. 23 | 22 .. 21 | 20 .. 16 | > | other stuff | spi_frf | dfs_32 | > > | 15 .. 10 | 9 .. 8 | 7 .. 6 | 5 .. 4 | 3 .. 0 | > | other stuff | tmod | mode | frf | dfs | > > Th main difference of this layout with the 16-bits version is the data ^ | e > frame format field which resides in bits 16..20 instead of bits 3..0. > Are you sure they have been moved from [0, 3] to [16, 20]? I don't have the manual for the 4.0x version of the core, but according to this patch: https://patchwork.kernel.org/project/spi-devel-general/patch/1575907443-26377-7-git-send-email-wan.ahmad.zainie.wan.mohamad@intel.com/ it has been ok to use the lowest four bits for DFS setting. Is the commit message misleading there? > Introduce the DW SPI capability flag DW_SPI_CAP_DFS_32 to let a > platform signal that this layout is in use. Modify > dw_spi_update_config() to test this capability flag to set the data > frame format field at the correct register location. > > Suggested-by: Sean Anderson <seanga2@gmail.com> > Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> > --- > drivers/spi/spi-dw-core.c | 8 ++++++-- > drivers/spi/spi-dw.h | 9 +++++++++ > 2 files changed, 15 insertions(+), 2 deletions(-) > > diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c > index 2e50cc0a9291..841c85247f01 100644 > --- a/drivers/spi/spi-dw-core.c > +++ b/drivers/spi/spi-dw-core.c > @@ -311,8 +311,12 @@ void dw_spi_update_config(struct dw_spi *dws, struct spi_device *spi, > u32 speed_hz; > u16 clk_div; > > - /* CTRLR0[ 4/3: 0] Data Frame Size */ > - cr0 |= (cfg->dfs - 1); > + if (!(dws->caps & DW_SPI_CAP_DFS_32)) > + /* CTRLR0[ 4/3: 0] Data Frame Size */ > + cr0 |= (cfg->dfs - 1); > + else > + /* CTRLR0[20: 16] Data Frame Size */ > + cr0 |= (cfg->dfs - 1) << DWC_APB_CTRLR0_32_DFS_OFFSET; If you extend the dfs field from four to five bits, then controller->bits_per_word_mask field should be properly updated too. Alas it hasn't been done for the DWC_ssi version of the core. So I suppose it should be fixed for the both of them. Just for the record. There are very handy macros for setting and getting bit fields to/from a variable. This is a good place to use them instead of manually shifting and defining the offsets. The macros are defined in linux/bitfield.h . Alas this driver hasn't been converted to using them. So I won't insist on using them here. But I hope someone will fix it sometime in future... -Sergey > > if (!(dws->caps & DW_SPI_CAP_DWC_SSI)) > /* CTRLR0[ 9:8] Transfer Mode */ > diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h > index faf40cb66498..48a11a51a407 100644 > --- a/drivers/spi/spi-dw.h > +++ b/drivers/spi/spi-dw.h > @@ -9,6 +9,7 @@ > #include <linux/io.h> > #include <linux/scatterlist.h> > #include <linux/spi/spi-mem.h> > +#include <linux/bitfield.h> > > /* Register offsets */ > #define DW_SPI_CTRLR0 0x00 > @@ -72,6 +73,13 @@ > #define DWC_SSI_CTRLR0_FRF_OFFSET 6 > #define DWC_SSI_CTRLR0_DFS_OFFSET 0 > > +/* > + * Bit fields in CTRLR0 for DWC_apb_ssi v4 32-bits ctrlr0. > + * Based on DW_apb_ssi Databook v4.02a. > + */ > +#define DWC_APB_CTRLR0_32_DFS_OFFSET 16 > +#define DWC_APB_CTRLR0_32_DFS_MASK GENMASK(20, 16) > + > /* > * For Keem Bay, CTRLR0[31] is used to select controller mode. > * 0: SSI is slave > @@ -121,6 +129,7 @@ enum dw_ssi_type { > #define DW_SPI_CAP_CS_OVERRIDE BIT(0) > #define DW_SPI_CAP_KEEMBAY_MST BIT(1) > #define DW_SPI_CAP_DWC_SSI BIT(2) > +#define DW_SPI_CAP_DFS_32 BIT(3) > > /* Slave spi_transfer/spi_mem_op related */ > struct dw_spi_cfg { > -- > 2.28.0 >
On 11/9/20 9:25 AM, Serge Semin wrote: > Hello Damien, > Thanks for your patches. My comments are below. > > On Sat, Nov 07, 2020 at 05:13:50PM +0900, Damien Le Moal wrote: >> Synopsis DesignWare DW_apb_ssi version 4 defines a 32-bit layout of >> the ctrlr0 register for SPI masters. The layout of ctrlr0 is: >> >> | 31 .. 23 | 22 .. 21 | 20 .. 16 | >> | other stuff | spi_frf | dfs_32 | >> >> | 15 .. 10 | 9 .. 8 | 7 .. 6 | 5 .. 4 | 3 .. 0 | >> | other stuff | tmod | mode | frf | dfs | >> > >> Th main difference of this layout with the 16-bits version is the data > ^ > | > e > >> frame format field which resides in bits 16..20 instead of bits 3..0. >> > > Are you sure they have been moved from [0, 3] to [16, 20]? I don't have the > manual for the 4.0x version of the core, but according to this patch: > https://patchwork.kernel.org/project/spi-devel-general/patch/1575907443-26377-7-git-send-email-wan.ahmad.zainie.wan.mohamad@intel.com/ > it has been ok to use the lowest four bits for DFS setting. Is the commit > message misleading there? This commit message is a truncated version of [1]. Importantly, DFS is valid when SSI_MAX_XFER_SIZE=16. When it =32, then DFS_32 must be used (since DFS is constant 0xF). Since SSI_MAX_XFER_SIZE is a synthesis parameter, there exist devices where DFS must be used, and also where DFS_32 must be used. [1] https://patchwork.ozlabs.org/project/uboot/patch/20201016225755.302659-10-seanga2@gmail.com/ --Sean > >> Introduce the DW SPI capability flag DW_SPI_CAP_DFS_32 to let a >> platform signal that this layout is in use. Modify >> dw_spi_update_config() to test this capability flag to set the data >> frame format field at the correct register location. >> >> Suggested-by: Sean Anderson <seanga2@gmail.com> >> Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> >> --- >> drivers/spi/spi-dw-core.c | 8 ++++++-- >> drivers/spi/spi-dw.h | 9 +++++++++ >> 2 files changed, 15 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c >> index 2e50cc0a9291..841c85247f01 100644 >> --- a/drivers/spi/spi-dw-core.c >> +++ b/drivers/spi/spi-dw-core.c >> @@ -311,8 +311,12 @@ void dw_spi_update_config(struct dw_spi *dws, struct spi_device *spi, >> u32 speed_hz; >> u16 clk_div; >> > >> - /* CTRLR0[ 4/3: 0] Data Frame Size */ >> - cr0 |= (cfg->dfs - 1); >> + if (!(dws->caps & DW_SPI_CAP_DFS_32)) >> + /* CTRLR0[ 4/3: 0] Data Frame Size */ >> + cr0 |= (cfg->dfs - 1); >> + else >> + /* CTRLR0[20: 16] Data Frame Size */ >> + cr0 |= (cfg->dfs - 1) << DWC_APB_CTRLR0_32_DFS_OFFSET; > > If you extend the dfs field from four to five bits, then > controller->bits_per_word_mask field should be properly updated too. > > Alas it hasn't been done for the DWC_ssi version of the core. So I suppose it > should be fixed for the both of them. > > Just for the record. There are very handy macros for setting and getting bit fields > to/from a variable. This is a good place to use them instead of manually > shifting and defining the offsets. The macros are defined in linux/bitfield.h . > Alas this driver hasn't been converted to using them. So I won't insist on using > them here. But I hope someone will fix it sometime in future... I second that request. > -Sergey > >> >> if (!(dws->caps & DW_SPI_CAP_DWC_SSI)) >> /* CTRLR0[ 9:8] Transfer Mode */ >> diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h >> index faf40cb66498..48a11a51a407 100644 >> --- a/drivers/spi/spi-dw.h >> +++ b/drivers/spi/spi-dw.h >> @@ -9,6 +9,7 @@ >> #include <linux/io.h> >> #include <linux/scatterlist.h> >> #include <linux/spi/spi-mem.h> >> +#include <linux/bitfield.h> >> >> /* Register offsets */ >> #define DW_SPI_CTRLR0 0x00 >> @@ -72,6 +73,13 @@ >> #define DWC_SSI_CTRLR0_FRF_OFFSET 6 >> #define DWC_SSI_CTRLR0_DFS_OFFSET 0 >> >> +/* >> + * Bit fields in CTRLR0 for DWC_apb_ssi v4 32-bits ctrlr0. >> + * Based on DW_apb_ssi Databook v4.02a. >> + */ >> +#define DWC_APB_CTRLR0_32_DFS_OFFSET 16 >> +#define DWC_APB_CTRLR0_32_DFS_MASK GENMASK(20, 16) >> + >> /* >> * For Keem Bay, CTRLR0[31] is used to select controller mode. >> * 0: SSI is slave >> @@ -121,6 +129,7 @@ enum dw_ssi_type { >> #define DW_SPI_CAP_CS_OVERRIDE BIT(0) >> #define DW_SPI_CAP_KEEMBAY_MST BIT(1) >> #define DW_SPI_CAP_DWC_SSI BIT(2) >> +#define DW_SPI_CAP_DFS_32 BIT(3) >> >> /* Slave spi_transfer/spi_mem_op related */ >> struct dw_spi_cfg { >> -- >> 2.28.0 >>
On 11/9/20 9:33 AM, Sean Anderson wrote: > On 11/9/20 9:25 AM, Serge Semin wrote: >> Hello Damien, >> Thanks for your patches. My comments are below. >> >> On Sat, Nov 07, 2020 at 05:13:50PM +0900, Damien Le Moal wrote: >>> Synopsis DesignWare DW_apb_ssi version 4 defines a 32-bit layout of >>> the ctrlr0 register for SPI masters. The layout of ctrlr0 is: >>> >>> | 31 .. 23 | 22 .. 21 | 20 .. 16 | >>> | other stuff | spi_frf | dfs_32 | >>> >>> | 15 .. 10 | 9 .. 8 | 7 .. 6 | 5 .. 4 | 3 .. 0 | >>> | other stuff | tmod | mode | frf | dfs | >>> >> >>> Th main difference of this layout with the 16-bits version is the data >> ^ >> | >> e >> >>> frame format field which resides in bits 16..20 instead of bits 3..0. >>> >> >> Are you sure they have been moved from [0, 3] to [16, 20]? I don't have the >> manual for the 4.0x version of the core, but according to this patch: >> https://patchwork.kernel.org/project/spi-devel-general/patch/1575907443-26377-7-git-send-email-wan.ahmad.zainie.wan.mohamad@intel.com/ >> it has been ok to use the lowest four bits for DFS setting. Is the commit >> message misleading there? > > This commit message is a truncated version of [1]. Importantly, DFS is > valid when SSI_MAX_XFER_SIZE=16. When it =32, then DFS_32 must be used > (since DFS is constant 0xF). Since SSI_MAX_XFER_SIZE is a synthesis s/0xF/0x0/ > parameter, there exist devices where DFS must be used, and also where > DFS_32 must be used. > > [1] https://patchwork.ozlabs.org/project/uboot/patch/20201016225755.302659-10-seanga2@gmail.com/ > > --Sean > >> >>> Introduce the DW SPI capability flag DW_SPI_CAP_DFS_32 to let a >>> platform signal that this layout is in use. Modify >>> dw_spi_update_config() to test this capability flag to set the data >>> frame format field at the correct register location. >>> >>> Suggested-by: Sean Anderson <seanga2@gmail.com> >>> Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> >>> --- >>> drivers/spi/spi-dw-core.c | 8 ++++++-- >>> drivers/spi/spi-dw.h | 9 +++++++++ >>> 2 files changed, 15 insertions(+), 2 deletions(-) >>> >>> diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c >>> index 2e50cc0a9291..841c85247f01 100644 >>> --- a/drivers/spi/spi-dw-core.c >>> +++ b/drivers/spi/spi-dw-core.c >>> @@ -311,8 +311,12 @@ void dw_spi_update_config(struct dw_spi *dws, struct spi_device *spi, >>> u32 speed_hz; >>> u16 clk_div; >>> >> >>> - /* CTRLR0[ 4/3: 0] Data Frame Size */ >>> - cr0 |= (cfg->dfs - 1); >>> + if (!(dws->caps & DW_SPI_CAP_DFS_32)) >>> + /* CTRLR0[ 4/3: 0] Data Frame Size */ >>> + cr0 |= (cfg->dfs - 1); >>> + else >>> + /* CTRLR0[20: 16] Data Frame Size */ >>> + cr0 |= (cfg->dfs - 1) << DWC_APB_CTRLR0_32_DFS_OFFSET; >> >> If you extend the dfs field from four to five bits, then >> controller->bits_per_word_mask field should be properly updated too. >> >> Alas it hasn't been done for the DWC_ssi version of the core. So I suppose it >> should be fixed for the both of them. >> >> Just for the record. There are very handy macros for setting and getting bit fields >> to/from a variable. This is a good place to use them instead of manually >> shifting and defining the offsets. The macros are defined in linux/bitfield.h . >> Alas this driver hasn't been converted to using them. So I won't insist on using >> them here. But I hope someone will fix it sometime in future... > > I second that request. > >> -Sergey >> >>> >>> if (!(dws->caps & DW_SPI_CAP_DWC_SSI)) >>> /* CTRLR0[ 9:8] Transfer Mode */ >>> diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h >>> index faf40cb66498..48a11a51a407 100644 >>> --- a/drivers/spi/spi-dw.h >>> +++ b/drivers/spi/spi-dw.h >>> @@ -9,6 +9,7 @@ >>> #include <linux/io.h> >>> #include <linux/scatterlist.h> >>> #include <linux/spi/spi-mem.h> >>> +#include <linux/bitfield.h> >>> >>> /* Register offsets */ >>> #define DW_SPI_CTRLR0 0x00 >>> @@ -72,6 +73,13 @@ >>> #define DWC_SSI_CTRLR0_FRF_OFFSET 6 >>> #define DWC_SSI_CTRLR0_DFS_OFFSET 0 >>> >>> +/* >>> + * Bit fields in CTRLR0 for DWC_apb_ssi v4 32-bits ctrlr0. >>> + * Based on DW_apb_ssi Databook v4.02a. >>> + */ >>> +#define DWC_APB_CTRLR0_32_DFS_OFFSET 16 >>> +#define DWC_APB_CTRLR0_32_DFS_MASK GENMASK(20, 16) >>> + >>> /* >>> * For Keem Bay, CTRLR0[31] is used to select controller mode. >>> * 0: SSI is slave >>> @@ -121,6 +129,7 @@ enum dw_ssi_type { >>> #define DW_SPI_CAP_CS_OVERRIDE BIT(0) >>> #define DW_SPI_CAP_KEEMBAY_MST BIT(1) >>> #define DW_SPI_CAP_DWC_SSI BIT(2) >>> +#define DW_SPI_CAP_DFS_32 BIT(3) >>> >>> /* Slave spi_transfer/spi_mem_op related */ >>> struct dw_spi_cfg { >>> -- >>> 2.28.0 >>> >
On Mon, Nov 9, 2020 at 4:25 PM Serge Semin <fancer.lancer@gmail.com> wrote: > > Hello Damien, > Thanks for your patches. My comments are below. > > On Sat, Nov 07, 2020 at 05:13:50PM +0900, Damien Le Moal wrote: > > Synopsis DesignWare DW_apb_ssi version 4 defines a 32-bit layout of > > the ctrlr0 register for SPI masters. The layout of ctrlr0 is: > > > > | 31 .. 23 | 22 .. 21 | 20 .. 16 | > > | other stuff | spi_frf | dfs_32 | > > > > | 15 .. 10 | 9 .. 8 | 7 .. 6 | 5 .. 4 | 3 .. 0 | > > | other stuff | tmod | mode | frf | dfs | > > > > > Th main difference of this layout with the 16-bits version is the data > ^ > | > e > > > frame format field which resides in bits 16..20 instead of bits 3..0. > > > > Are you sure they have been moved from [0, 3] to [16, 20]? I don't have the > manual for the 4.0x version of the core, but according to this patch: > https://patchwork.kernel.org/project/spi-devel-general/patch/1575907443-26377-7-git-send-email-wan.ahmad.zainie.wan.mohamad@intel.com/ > it has been ok to use the lowest four bits for DFS setting. Is the commit > message misleading there? 20:16 DFS_32 Data Frame Size in 32-bit transfer size mode. Used to select the data frame size in 32-bit transfer mode. These bits are only valid when SSI_MAX_XFER_SIZE is configured to 32. When the data frame size is programmed to be less than 32 bits, the receive data are automatically right-justified by the receive logic, with the upper bits of the receive FIFO zero- padded. 3:0 DFS Data Frame Size. This register field is only valid when SSI_MAX_XFER_SIZE is configured to 16. If SSI_MAX_XFER_SIZE is configured to 32, then writing to this field will not have any effect. As far as I can tell it's an extension to the existing one (which one in use depends on the SSI configuration). The comment you are referring to is about DW_ssi v1.x (vs. DW_apb_ssi v4.x).
On Mon, Nov 9, 2020 at 4:34 PM Sean Anderson <seanga2@gmail.com> wrote: > On 11/9/20 9:25 AM, Serge Semin wrote: > > On Sat, Nov 07, 2020 at 05:13:50PM +0900, Damien Le Moal wrote: ... > > Are you sure they have been moved from [0, 3] to [16, 20]? I don't have the > > manual for the 4.0x version of the core, but according to this patch: > > https://patchwork.kernel.org/project/spi-devel-general/patch/1575907443-26377-7-git-send-email-wan.ahmad.zainie.wan.mohamad@intel.com/ > > it has been ok to use the lowest four bits for DFS setting. Is the commit > > message misleading there? > > This commit message is a truncated version of [1]. I don't see how they are related. > Importantly, DFS is > valid when SSI_MAX_XFER_SIZE=16. When it =32, then DFS_32 must be used > (since DFS is constant 0xF). Since SSI_MAX_XFER_SIZE is a synthesis > parameter, there exist devices where DFS must be used, and also where > DFS_32 must be used. > > [1] https://patchwork.ozlabs.org/project/uboot/patch/20201016225755.302659-10-seanga2@gmail.com/
On Mon, Nov 9, 2020 at 4:40 PM Andy Shevchenko <andy.shevchenko@gmail.com> wrote: > > On Mon, Nov 9, 2020 at 4:34 PM Sean Anderson <seanga2@gmail.com> wrote: > > On 11/9/20 9:25 AM, Serge Semin wrote: > > > On Sat, Nov 07, 2020 at 05:13:50PM +0900, Damien Le Moal wrote: > > ... > > > > Are you sure they have been moved from [0, 3] to [16, 20]? I don't have the > > > manual for the 4.0x version of the core, but according to this patch: > > > https://patchwork.kernel.org/project/spi-devel-general/patch/1575907443-26377-7-git-send-email-wan.ahmad.zainie.wan.mohamad@intel.com/ > > > it has been ok to use the lowest four bits for DFS setting. Is the commit > > > message misleading there? > > > > This commit message is a truncated version of [1]. > > I don't see how they are related. For DW_ssi v1.x DFS is always for transfers up to 32-bit. > > Importantly, DFS is > > valid when SSI_MAX_XFER_SIZE=16. When it =32, then DFS_32 must be used > > (since DFS is constant 0xF). Since SSI_MAX_XFER_SIZE is a synthesis > > parameter, there exist devices where DFS must be used, and also where > > DFS_32 must be used. > > > > [1] https://patchwork.ozlabs.org/project/uboot/patch/20201016225755.302659-10-seanga2@gmail.com/
On 11/9/20 9:41 AM, Andy Shevchenko wrote: > On Mon, Nov 9, 2020 at 4:40 PM Andy Shevchenko > <andy.shevchenko@gmail.com> wrote: >> >> On Mon, Nov 9, 2020 at 4:34 PM Sean Anderson <seanga2@gmail.com> wrote: >>> On 11/9/20 9:25 AM, Serge Semin wrote: >>>> On Sat, Nov 07, 2020 at 05:13:50PM +0900, Damien Le Moal wrote: >> >> ... >> >>>> Are you sure they have been moved from [0, 3] to [16, 20]? I don't have the >>>> manual for the 4.0x version of the core, but according to this patch: >>>> https://patchwork.kernel.org/project/spi-devel-general/patch/1575907443-26377-7-git-send-email-wan.ahmad.zainie.wan.mohamad@intel.com/ >>>> it has been ok to use the lowest four bits for DFS setting. Is the commit >>>> message misleading there? >>> >>> This commit message is a truncated version of [1]. >> >> I don't see how they are related. I think this commit message is specifically taken from v3 of that patch [2]. However, I had not gotten a chance to have a look at the datasheet at that point, so it is a bit misleading (e.g. showing dfs for devices with SSI_MAX_XFER_SIZE=32, even though it is all zeros for those devices). In any case, the diagram is taken from that patch. [2] https://patchwork.ozlabs.org/project/uboot/patch/20200914153503.91983-7-seanga2@gmail.com/ > > For DW_ssi v1.x DFS is always for transfers up to 32-bit. Do you mean DWC_ssi? > >>> Importantly, DFS is >>> valid when SSI_MAX_XFER_SIZE=16. When it =32, then DFS_32 must be used >>> (since DFS is constant 0xF). Since SSI_MAX_XFER_SIZE is a synthesis >>> parameter, there exist devices where DFS must be used, and also where >>> DFS_32 must be used. >>> >>> [1] https://patchwork.ozlabs.org/project/uboot/patch/20201016225755.302659-10-seanga2@gmail.com/ > > >
On Mon, Nov 9, 2020 at 4:49 PM Sean Anderson <seanga2@gmail.com> wrote: > On 11/9/20 9:41 AM, Andy Shevchenko wrote: > > On Mon, Nov 9, 2020 at 4:40 PM Andy Shevchenko > > <andy.shevchenko@gmail.com> wrote: ... > > For DW_ssi v1.x DFS is always for transfers up to 32-bit. > > Do you mean DWC_ssi? One is called DWC_ssi (yes, the newer IP) The other is DW_apb_ssi (the older one) -- With Best Regards, Andy Shevchenko
Hello Andy, On Mon, Nov 09, 2020 at 04:36:51PM +0200, Andy Shevchenko wrote: > On Mon, Nov 9, 2020 at 4:25 PM Serge Semin <fancer.lancer@gmail.com> wrote: > > > > Hello Damien, > > Thanks for your patches. My comments are below. > > > > On Sat, Nov 07, 2020 at 05:13:50PM +0900, Damien Le Moal wrote: > > > Synopsis DesignWare DW_apb_ssi version 4 defines a 32-bit layout of > > > the ctrlr0 register for SPI masters. The layout of ctrlr0 is: > > > > > > | 31 .. 23 | 22 .. 21 | 20 .. 16 | > > > | other stuff | spi_frf | dfs_32 | > > > > > > | 15 .. 10 | 9 .. 8 | 7 .. 6 | 5 .. 4 | 3 .. 0 | > > > | other stuff | tmod | mode | frf | dfs | > > > > > > > > Th main difference of this layout with the 16-bits version is the data > > ^ > > | > > e > > > > > frame format field which resides in bits 16..20 instead of bits 3..0. > > > > > > > Are you sure they have been moved from [0, 3] to [16, 20]? I don't have the > > manual for the 4.0x version of the core, but according to this patch: > > https://patchwork.kernel.org/project/spi-devel-general/patch/1575907443-26377-7-git-send-email-wan.ahmad.zainie.wan.mohamad@intel.com/ > > it has been ok to use the lowest four bits for DFS setting. Is the commit > > message misleading there? > > 20:16 DFS_32 > Data Frame Size in 32-bit transfer size mode. Used to select > the data frame size in 32-bit transfer mode. These bits are > only valid when SSI_MAX_XFER_SIZE is configured to 32. > When the data frame size is programmed to be less than 32 > bits, the receive data are automatically right-justified by the > receive logic, with the upper bits of the receive FIFO zero- > padded. > > 3:0 DFS > Data Frame Size. > This register field is only valid when SSI_MAX_XFER_SIZE > is configured to 16. If SSI_MAX_XFER_SIZE is configured to > 32, then writing to this field will not have any effect. > > As far as I can tell it's an extension to the existing one (which one > in use depends on the SSI configuration). > > > The comment you are referring to is about DW_ssi v1.x (vs. DW_apb_ssi v4.x). Ok. Thanks for clarifying this. Now I see the way it's working. -Sergey > > > -- > With Best Regards, > Andy Shevchenko
diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c index 2e50cc0a9291..841c85247f01 100644 --- a/drivers/spi/spi-dw-core.c +++ b/drivers/spi/spi-dw-core.c @@ -311,8 +311,12 @@ void dw_spi_update_config(struct dw_spi *dws, struct spi_device *spi, u32 speed_hz; u16 clk_div; - /* CTRLR0[ 4/3: 0] Data Frame Size */ - cr0 |= (cfg->dfs - 1); + if (!(dws->caps & DW_SPI_CAP_DFS_32)) + /* CTRLR0[ 4/3: 0] Data Frame Size */ + cr0 |= (cfg->dfs - 1); + else + /* CTRLR0[20: 16] Data Frame Size */ + cr0 |= (cfg->dfs - 1) << DWC_APB_CTRLR0_32_DFS_OFFSET; if (!(dws->caps & DW_SPI_CAP_DWC_SSI)) /* CTRLR0[ 9:8] Transfer Mode */ diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h index faf40cb66498..48a11a51a407 100644 --- a/drivers/spi/spi-dw.h +++ b/drivers/spi/spi-dw.h @@ -9,6 +9,7 @@ #include <linux/io.h> #include <linux/scatterlist.h> #include <linux/spi/spi-mem.h> +#include <linux/bitfield.h> /* Register offsets */ #define DW_SPI_CTRLR0 0x00 @@ -72,6 +73,13 @@ #define DWC_SSI_CTRLR0_FRF_OFFSET 6 #define DWC_SSI_CTRLR0_DFS_OFFSET 0 +/* + * Bit fields in CTRLR0 for DWC_apb_ssi v4 32-bits ctrlr0. + * Based on DW_apb_ssi Databook v4.02a. + */ +#define DWC_APB_CTRLR0_32_DFS_OFFSET 16 +#define DWC_APB_CTRLR0_32_DFS_MASK GENMASK(20, 16) + /* * For Keem Bay, CTRLR0[31] is used to select controller mode. * 0: SSI is slave @@ -121,6 +129,7 @@ enum dw_ssi_type { #define DW_SPI_CAP_CS_OVERRIDE BIT(0) #define DW_SPI_CAP_KEEMBAY_MST BIT(1) #define DW_SPI_CAP_DWC_SSI BIT(2) +#define DW_SPI_CAP_DFS_32 BIT(3) /* Slave spi_transfer/spi_mem_op related */ struct dw_spi_cfg {
Synopsis DesignWare DW_apb_ssi version 4 defines a 32-bit layout of the ctrlr0 register for SPI masters. The layout of ctrlr0 is: | 31 .. 23 | 22 .. 21 | 20 .. 16 | | other stuff | spi_frf | dfs_32 | | 15 .. 10 | 9 .. 8 | 7 .. 6 | 5 .. 4 | 3 .. 0 | | other stuff | tmod | mode | frf | dfs | Th main difference of this layout with the 16-bits version is the data frame format field which resides in bits 16..20 instead of bits 3..0. Introduce the DW SPI capability flag DW_SPI_CAP_DFS_32 to let a platform signal that this layout is in use. Modify dw_spi_update_config() to test this capability flag to set the data frame format field at the correct register location. Suggested-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> --- drivers/spi/spi-dw-core.c | 8 ++++++-- drivers/spi/spi-dw.h | 9 +++++++++ 2 files changed, 15 insertions(+), 2 deletions(-)