diff mbox series

[5/8] pinctrl: renesas: r8a7795: Optimize pinctrl image size for R8A774E1

Message ID 20201028103429.3051-6-biju.das.jz@bp.renesas.com
State Accepted
Commit 2a589b7c51c843e84eb7dbe361c493c2a3551a74
Delegated to: Marek Vasut
Headers show
Series Pin control support for RZ/G2[HN] | expand

Commit Message

Biju Das Oct. 28, 2020, 10:34 a.m. UTC 
This driver supports both RZ/G2H and R-Car H3 SoCs.
Optimize pinctrl image size for RZ/G2H, when support for R-Car H3
(R8A7795) is not enabled

Based on the similar patch on Linux.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/pinctrl/renesas/pfc-r8a7795.c | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

Comments

Marek Vasut Nov. 1, 2020, 11:31 a.m. UTC | #1 
On 10/28/20 11:34 AM, Biju Das wrote:
> This driver supports both RZ/G2H and R-Car H3 SoCs.
> Optimize pinctrl image size for RZ/G2H, when support for R-Car H3
> (R8A7795) is not enabled
> 
> Based on the similar patch on Linux.

Applied, thanks
diff mbox series

Patch

diff --git a/drivers/pinctrl/renesas/pfc-r8a7795.c b/drivers/pinctrl/renesas/pfc-r8a7795.c
index b787c4883a..898f837950 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7795.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7795.c
@@ -1836,6 +1836,7 @@  static const unsigned int canfd1_data_mux[] = {
 	CANFD1_TX_MARK,         CANFD1_RX_MARK,
 };
 
+#ifdef CONFIG_PINCTRL_PFC_R8A7795
 /* - DRIF0 --------------------------------------------------------------- */
 static const unsigned int drif0_ctrl_a_pins[] = {
 	/* CLK, SYNC */
@@ -2050,6 +2051,7 @@  static const unsigned int drif3_data1_b_pins[] = {
 static const unsigned int drif3_data1_b_mux[] = {
 	RIF3_D1_B_MARK,
 };
+#endif /* CONFIG_PINCTRL_PFC_R8A7795 */
 
 /* - DU --------------------------------------------------------------------- */
 static const unsigned int du_rgb666_pins[] = {
@@ -4168,7 +4170,9 @@  static const unsigned int vin5_clk_mux[] = {
 
 static const struct {
 	struct sh_pfc_pin_group common[320];
+#ifdef CONFIG_PINCTRL_PFC_R8A7795
 	struct sh_pfc_pin_group automotive[30];
+#endif
 } pinmux_groups = {
 	.common = {
 		SH_PFC_PIN_GROUP(audio_clk_a_a),
@@ -4492,6 +4496,7 @@  static const struct {
 		SH_PFC_PIN_GROUP(vin5_clkenb),
 		SH_PFC_PIN_GROUP(vin5_clk),
 	},
+#ifdef CONFIG_PINCTRL_PFC_R8A7795
 	.automotive = {
 		SH_PFC_PIN_GROUP(drif0_ctrl_a),
 		SH_PFC_PIN_GROUP(drif0_data0_a),
@@ -4524,7 +4529,7 @@  static const struct {
 		SH_PFC_PIN_GROUP(drif3_data0_b),
 		SH_PFC_PIN_GROUP(drif3_data1_b),
 	}
-
+#endif /* CONFIG_PINCTRL_PFC_R8A7795 */
 };
 
 static const char * const audio_clk_groups[] = {
@@ -4583,6 +4588,7 @@  static const char * const canfd1_groups[] = {
 	"canfd1_data",
 };
 
+#ifdef CONFIG_PINCTRL_PFC_R8A7795
 static const char * const drif0_groups[] = {
 	"drif0_ctrl_a",
 	"drif0_data0_a",
@@ -4624,6 +4630,7 @@  static const char * const drif3_groups[] = {
 	"drif3_data0_b",
 	"drif3_data1_b",
 };
+#endif /* CONFIG_PINCTRL_PFC_R8A7795 */
 
 static const char * const du_groups[] = {
 	"du_rgb666",
@@ -5050,7 +5057,9 @@  static const char * const vin5_groups[] = {
 
 static const struct {
 	struct sh_pfc_function common[53];
+#ifdef CONFIG_PINCTRL_PFC_R8A7795
 	struct sh_pfc_function automotive[4];
+#endif
 } pinmux_functions = {
 	.common = {
 		SH_PFC_FUNCTION(audio_clk),
@@ -5107,13 +5116,14 @@  static const struct {
 		SH_PFC_FUNCTION(vin4),
 		SH_PFC_FUNCTION(vin5),
 	},
+#ifdef CONFIG_PINCTRL_PFC_R8A7795
 	.automotive = {
 		SH_PFC_FUNCTION(drif0),
 		SH_PFC_FUNCTION(drif1),
 		SH_PFC_FUNCTION(drif2),
 		SH_PFC_FUNCTION(drif3),
 	}
-
+#endif /* CONFIG_PINCTRL_PFC_R8A7795 */
 };
 
 static const struct pinmux_cfg_reg pinmux_config_regs[] = {