Message ID | 20201025221735.3062-4-digetx@gmail.com |
---|---|
State | Not Applicable, archived |
Headers | show |
Series | Introduce memory interconnect for NVIDIA Tegra SoCs | expand |
Context | Check | Description |
---|---|---|
robh/checkpatch | success |
On Mon, Oct 26, 2020 at 01:16:46AM +0300, Dmitry Osipenko wrote: > There is superfluous zero in the registers base address and registers > size should be twice bigger. > > Signed-off-by: Dmitry Osipenko <digetx@gmail.com> > --- > .../bindings/memory-controllers/nvidia,tegra20-emc.txt | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Acked-by: Thierry Reding <treding@nvidia.com>
On Mon, 26 Oct 2020 01:16:46 +0300, Dmitry Osipenko wrote: > There is superfluous zero in the registers base address and registers > size should be twice bigger. > > Signed-off-by: Dmitry Osipenko <digetx@gmail.com> > --- > .../bindings/memory-controllers/nvidia,tegra20-emc.txt | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Acked-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt index add95367640b..567cffd37f3f 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt @@ -21,7 +21,7 @@ Example: #address-cells = < 1 >; #size-cells = < 0 >; compatible = "nvidia,tegra20-emc"; - reg = <0x7000f4000 0x200>; + reg = <0x7000f400 0x400>; interrupts = <0 78 0x04>; clocks = <&tegra_car TEGRA20_CLK_EMC>; }
There is superfluous zero in the registers base address and registers size should be twice bigger. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> --- .../bindings/memory-controllers/nvidia,tegra20-emc.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)