| Message ID | 20201027141740.18336-3-bmeng.cn@gmail.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box | expand |
On Tue, Oct 27, 2020 at 7:46 AM Bin Meng <bmeng.cn@gmail.com> wrote: > > From: Bin Meng <bin.meng@windriver.com> > > Connect DDR SGMII PHY module and CFG module to the PolarFire SoC. > > Signed-off-by: Bin Meng <bin.meng@windriver.com> > --- > > hw/riscv/Kconfig | 1 + > hw/riscv/microchip_pfsoc.c | 18 ++++++++++++++++++ > include/hw/riscv/microchip_pfsoc.h | 5 +++++ > 3 files changed, 24 insertions(+) > > diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig > index 2df978fe8d..c8e50bde99 100644 > --- a/hw/riscv/Kconfig > +++ b/hw/riscv/Kconfig > @@ -4,6 +4,7 @@ config IBEX > config MICROCHIP_PFSOC > bool > select CADENCE_SDHCI > + select MCHP_PFSOC_DMC > select MCHP_PFSOC_MMUART > select MSI_NONBROKEN > select SIFIVE_CLINT > diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c > index 4627179cd3..85be2bcde8 100644 > --- a/hw/riscv/microchip_pfsoc.c > +++ b/hw/riscv/microchip_pfsoc.c > @@ -15,6 +15,7 @@ > * 4) Cadence eMMC/SDHC controller and an SD card connected to it > * 5) SiFive Platform DMA (Direct Memory Access Controller) > * 6) GEM (Gigabit Ethernet MAC Controller) > + * 7) DMC (DDR Memory Controller) > * > * This board currently generates devicetree dynamically that indicates at least > * two harts and up to five harts. > @@ -85,7 +86,9 @@ static const struct MemmapEntry { > [MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 }, > [MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 }, > [MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 }, > + [MICROCHIP_PFSOC_DDR_SGMII_PHY] = { 0x20007000, 0x1000 }, > [MICROCHIP_PFSOC_EMMC_SD] = { 0x20008000, 0x1000 }, > + [MICROCHIP_PFSOC_DDR_CFG] = { 0x20080000, 0x40000 }, Neither of these are documented.... Maybe just add a single comment above the memory layout clarifying that this is not what is documented from the SoC but is instead based on what guests do? It seems to be a constant problem with this board, unless I am really misreading the memory map. Alistair > [MICROCHIP_PFSOC_MMUART1] = { 0x20100000, 0x1000 }, > [MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 }, > [MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 }, > @@ -131,6 +134,11 @@ static void microchip_pfsoc_soc_instance_init(Object *obj) > object_initialize_child(obj, "dma-controller", &s->dma, > TYPE_SIFIVE_PDMA); > > + object_initialize_child(obj, "ddr-sgmii-phy", &s->ddr_sgmii_phy, > + TYPE_MCHP_PFSOC_DDR_SGMII_PHY); > + object_initialize_child(obj, "ddr-cfg", &s->ddr_cfg, > + TYPE_MCHP_PFSOC_DDR_CFG); > + > object_initialize_child(obj, "gem0", &s->gem0, TYPE_CADENCE_GEM); > object_initialize_child(obj, "gem1", &s->gem1, TYPE_CADENCE_GEM); > > @@ -260,6 +268,16 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) > memmap[MICROCHIP_PFSOC_MPUCFG].base, > memmap[MICROCHIP_PFSOC_MPUCFG].size); > > + /* DDR SGMII PHY */ > + sysbus_realize(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), errp); > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), 0, > + memmap[MICROCHIP_PFSOC_DDR_SGMII_PHY].base); > + > + /* DDR CFG */ > + sysbus_realize(SYS_BUS_DEVICE(&s->ddr_cfg), errp); > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_cfg), 0, > + memmap[MICROCHIP_PFSOC_DDR_CFG].base); > + > /* SDHCI */ > sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp); > sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, > diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h > index 8bfc7e1a85..5b81e26241 100644 > --- a/include/hw/riscv/microchip_pfsoc.h > +++ b/include/hw/riscv/microchip_pfsoc.h > @@ -24,6 +24,7 @@ > > #include "hw/char/mchp_pfsoc_mmuart.h" > #include "hw/dma/sifive_pdma.h" > +#include "hw/misc/mchp_pfsoc_dmc.h" > #include "hw/net/cadence_gem.h" > #include "hw/sd/cadence_sdhci.h" > > @@ -37,6 +38,8 @@ typedef struct MicrochipPFSoCState { > RISCVHartArrayState e_cpus; > RISCVHartArrayState u_cpus; > DeviceState *plic; > + MchpPfSoCDdrSgmiiPhyState ddr_sgmii_phy; > + MchpPfSoCDdrCfgState ddr_cfg; > MchpPfSoCMMUartState *serial0; > MchpPfSoCMMUartState *serial1; > MchpPfSoCMMUartState *serial2; > @@ -82,7 +85,9 @@ enum { > MICROCHIP_PFSOC_MMUART0, > MICROCHIP_PFSOC_SYSREG, > MICROCHIP_PFSOC_MPUCFG, > + MICROCHIP_PFSOC_DDR_SGMII_PHY, > MICROCHIP_PFSOC_EMMC_SD, > + MICROCHIP_PFSOC_DDR_CFG, > MICROCHIP_PFSOC_MMUART1, > MICROCHIP_PFSOC_MMUART2, > MICROCHIP_PFSOC_MMUART3, > -- > 2.25.1 > >
Hi Alistair, On Wed, Oct 28, 2020 at 1:49 AM Alistair Francis <alistair23@gmail.com> wrote: > > On Tue, Oct 27, 2020 at 7:46 AM Bin Meng <bmeng.cn@gmail.com> wrote: > > > > From: Bin Meng <bin.meng@windriver.com> > > > > Connect DDR SGMII PHY module and CFG module to the PolarFire SoC. > > > > Signed-off-by: Bin Meng <bin.meng@windriver.com> > > --- > > > > hw/riscv/Kconfig | 1 + > > hw/riscv/microchip_pfsoc.c | 18 ++++++++++++++++++ > > include/hw/riscv/microchip_pfsoc.h | 5 +++++ > > 3 files changed, 24 insertions(+) > > > > diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig > > index 2df978fe8d..c8e50bde99 100644 > > --- a/hw/riscv/Kconfig > > +++ b/hw/riscv/Kconfig > > @@ -4,6 +4,7 @@ config IBEX > > config MICROCHIP_PFSOC > > bool > > select CADENCE_SDHCI > > + select MCHP_PFSOC_DMC > > select MCHP_PFSOC_MMUART > > select MSI_NONBROKEN > > select SIFIVE_CLINT > > diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c > > index 4627179cd3..85be2bcde8 100644 > > --- a/hw/riscv/microchip_pfsoc.c > > +++ b/hw/riscv/microchip_pfsoc.c > > @@ -15,6 +15,7 @@ > > * 4) Cadence eMMC/SDHC controller and an SD card connected to it > > * 5) SiFive Platform DMA (Direct Memory Access Controller) > > * 6) GEM (Gigabit Ethernet MAC Controller) > > + * 7) DMC (DDR Memory Controller) > > * > > * This board currently generates devicetree dynamically that indicates at least > > * two harts and up to five harts. > > @@ -85,7 +86,9 @@ static const struct MemmapEntry { > > [MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 }, > > [MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 }, > > [MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 }, > > + [MICROCHIP_PFSOC_DDR_SGMII_PHY] = { 0x20007000, 0x1000 }, > > [MICROCHIP_PFSOC_EMMC_SD] = { 0x20008000, 0x1000 }, > > + [MICROCHIP_PFSOC_DDR_CFG] = { 0x20080000, 0x40000 }, > > Neither of these are documented.... It's documented in the "Register Map/PF_SoC_RegMap_V1_1/pfsoc_regmap.htm" in https://www.microsemi.com/document-portal/doc_download/1244581-polarfire-soc-register-map > > Maybe just add a single comment above the memory layout clarifying > that this is not what is documented from the SoC but is instead based > on what guests do? > I can add a link to the Microchip website that documents the memory map above the memory layout. > It seems to be a constant problem with this board, unless I am really > misreading the memory map. > Regards, Bin
On Tue, Oct 27, 2020 at 6:43 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > Hi Alistair, > > On Wed, Oct 28, 2020 at 1:49 AM Alistair Francis <alistair23@gmail.com> wrote: > > > > On Tue, Oct 27, 2020 at 7:46 AM Bin Meng <bmeng.cn@gmail.com> wrote: > > > > > > From: Bin Meng <bin.meng@windriver.com> > > > > > > Connect DDR SGMII PHY module and CFG module to the PolarFire SoC. > > > > > > Signed-off-by: Bin Meng <bin.meng@windriver.com> > > > --- > > > > > > hw/riscv/Kconfig | 1 + > > > hw/riscv/microchip_pfsoc.c | 18 ++++++++++++++++++ > > > include/hw/riscv/microchip_pfsoc.h | 5 +++++ > > > 3 files changed, 24 insertions(+) > > > > > > diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig > > > index 2df978fe8d..c8e50bde99 100644 > > > --- a/hw/riscv/Kconfig > > > +++ b/hw/riscv/Kconfig > > > @@ -4,6 +4,7 @@ config IBEX > > > config MICROCHIP_PFSOC > > > bool > > > select CADENCE_SDHCI > > > + select MCHP_PFSOC_DMC > > > select MCHP_PFSOC_MMUART > > > select MSI_NONBROKEN > > > select SIFIVE_CLINT > > > diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c > > > index 4627179cd3..85be2bcde8 100644 > > > --- a/hw/riscv/microchip_pfsoc.c > > > +++ b/hw/riscv/microchip_pfsoc.c > > > @@ -15,6 +15,7 @@ > > > * 4) Cadence eMMC/SDHC controller and an SD card connected to it > > > * 5) SiFive Platform DMA (Direct Memory Access Controller) > > > * 6) GEM (Gigabit Ethernet MAC Controller) > > > + * 7) DMC (DDR Memory Controller) > > > * > > > * This board currently generates devicetree dynamically that indicates at least > > > * two harts and up to five harts. > > > @@ -85,7 +86,9 @@ static const struct MemmapEntry { > > > [MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 }, > > > [MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 }, > > > [MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 }, > > > + [MICROCHIP_PFSOC_DDR_SGMII_PHY] = { 0x20007000, 0x1000 }, > > > [MICROCHIP_PFSOC_EMMC_SD] = { 0x20008000, 0x1000 }, > > > + [MICROCHIP_PFSOC_DDR_CFG] = { 0x20080000, 0x40000 }, > > > > Neither of these are documented.... > > It's documented in the "Register > Map/PF_SoC_RegMap_V1_1/pfsoc_regmap.htm" in > https://www.microsemi.com/document-portal/doc_download/1244581-polarfire-soc-register-map That doesn't seem to be an official version controled doc though and it seems to conflict with the other UG document. > > > > > Maybe just add a single comment above the memory layout clarifying > > that this is not what is documented from the SoC but is instead based > > on what guests do? > > > > I can add a link to the Microchip website that documents the memory > map above the memory layout. Thanks, that's at least something. Alistair > > > It seems to be a constant problem with this board, unless I am really > > misreading the memory map. > > > > Regards, > Bin
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index 2df978fe8d..c8e50bde99 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -4,6 +4,7 @@ config IBEX config MICROCHIP_PFSOC bool select CADENCE_SDHCI + select MCHP_PFSOC_DMC select MCHP_PFSOC_MMUART select MSI_NONBROKEN select SIFIVE_CLINT diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 4627179cd3..85be2bcde8 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -15,6 +15,7 @@ * 4) Cadence eMMC/SDHC controller and an SD card connected to it * 5) SiFive Platform DMA (Direct Memory Access Controller) * 6) GEM (Gigabit Ethernet MAC Controller) + * 7) DMC (DDR Memory Controller) * * This board currently generates devicetree dynamically that indicates at least * two harts and up to five harts. @@ -85,7 +86,9 @@ static const struct MemmapEntry { [MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 }, [MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 }, [MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 }, + [MICROCHIP_PFSOC_DDR_SGMII_PHY] = { 0x20007000, 0x1000 }, [MICROCHIP_PFSOC_EMMC_SD] = { 0x20008000, 0x1000 }, + [MICROCHIP_PFSOC_DDR_CFG] = { 0x20080000, 0x40000 }, [MICROCHIP_PFSOC_MMUART1] = { 0x20100000, 0x1000 }, [MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 }, [MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 }, @@ -131,6 +134,11 @@ static void microchip_pfsoc_soc_instance_init(Object *obj) object_initialize_child(obj, "dma-controller", &s->dma, TYPE_SIFIVE_PDMA); + object_initialize_child(obj, "ddr-sgmii-phy", &s->ddr_sgmii_phy, + TYPE_MCHP_PFSOC_DDR_SGMII_PHY); + object_initialize_child(obj, "ddr-cfg", &s->ddr_cfg, + TYPE_MCHP_PFSOC_DDR_CFG); + object_initialize_child(obj, "gem0", &s->gem0, TYPE_CADENCE_GEM); object_initialize_child(obj, "gem1", &s->gem1, TYPE_CADENCE_GEM); @@ -260,6 +268,16 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) memmap[MICROCHIP_PFSOC_MPUCFG].base, memmap[MICROCHIP_PFSOC_MPUCFG].size); + /* DDR SGMII PHY */ + sysbus_realize(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), errp); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), 0, + memmap[MICROCHIP_PFSOC_DDR_SGMII_PHY].base); + + /* DDR CFG */ + sysbus_realize(SYS_BUS_DEVICE(&s->ddr_cfg), errp); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_cfg), 0, + memmap[MICROCHIP_PFSOC_DDR_CFG].base); + /* SDHCI */ sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp); sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h index 8bfc7e1a85..5b81e26241 100644 --- a/include/hw/riscv/microchip_pfsoc.h +++ b/include/hw/riscv/microchip_pfsoc.h @@ -24,6 +24,7 @@ #include "hw/char/mchp_pfsoc_mmuart.h" #include "hw/dma/sifive_pdma.h" +#include "hw/misc/mchp_pfsoc_dmc.h" #include "hw/net/cadence_gem.h" #include "hw/sd/cadence_sdhci.h" @@ -37,6 +38,8 @@ typedef struct MicrochipPFSoCState { RISCVHartArrayState e_cpus; RISCVHartArrayState u_cpus; DeviceState *plic; + MchpPfSoCDdrSgmiiPhyState ddr_sgmii_phy; + MchpPfSoCDdrCfgState ddr_cfg; MchpPfSoCMMUartState *serial0; MchpPfSoCMMUartState *serial1; MchpPfSoCMMUartState *serial2; @@ -82,7 +85,9 @@ enum { MICROCHIP_PFSOC_MMUART0, MICROCHIP_PFSOC_SYSREG, MICROCHIP_PFSOC_MPUCFG, + MICROCHIP_PFSOC_DDR_SGMII_PHY, MICROCHIP_PFSOC_EMMC_SD, + MICROCHIP_PFSOC_DDR_CFG, MICROCHIP_PFSOC_MMUART1, MICROCHIP_PFSOC_MMUART2, MICROCHIP_PFSOC_MMUART3,