| Message ID | 1603863010-15807-2-git-send-email-bmeng.cn@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box | expand |
On Tue, Oct 27, 2020 at 10:31 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > From: Bin Meng <bin.meng@windriver.com> > > It is not easy to find out the memory map for a specific component > in the PolarFire SoC as the information is scattered in different > documents. Add some comments so that people can know where to get > such information from the Microchip website. > > Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > > --- > > Changes in v2: > - new patch: Document where to look at the PolarFire SoC memory maps > > hw/riscv/microchip_pfsoc.c | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c > index 4627179..6aac849 100644 > --- a/hw/riscv/microchip_pfsoc.c > +++ b/hw/riscv/microchip_pfsoc.c > @@ -66,6 +66,24 @@ > /* GEM version */ > #define GEM_REVISION 0x0107010c > > +/* > + * The complete description of the whole PolarFire SoC memory map is scattered > + * in different documents. There are several places to look at for memory maps: > + * > + * 1 Chapter 11 "MSS Memory Map", in the doc "UG0880: PolarFire SoC FPGA > + * Microprocessor Subsystem (MSS) User Guide", which can be downloaded from > + * https://www.microsemi.com/document-portal/doc_download/ > + * 1244570-ug0880-polarfire-soc-fpga-microprocessor-subsystem-mss-user-guide, > + * describes the whole picture of the PolarFire SoC memory map. > + * > + * 2 A zip file for PolarFire soC memory map, which can be downloaded from > + * https://www.microsemi.com/document-portal/doc_download/ > + * 1244581-polarfire-soc-register-map, contains the following 2 major parts: > + * - Register Map/PF_SoC_RegMap_V1_1/pfsoc_regmap.htm > + * describes the complete integrated peripherals memory map > + * - Register Map/PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.htm > + * describes the complete IOSCB modules memory maps > + */ > static const struct MemmapEntry { > hwaddr base; > hwaddr size; > -- > 2.7.4 > >
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 4627179..6aac849 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -66,6 +66,24 @@ /* GEM version */ #define GEM_REVISION 0x0107010c +/* + * The complete description of the whole PolarFire SoC memory map is scattered + * in different documents. There are several places to look at for memory maps: + * + * 1 Chapter 11 "MSS Memory Map", in the doc "UG0880: PolarFire SoC FPGA + * Microprocessor Subsystem (MSS) User Guide", which can be downloaded from + * https://www.microsemi.com/document-portal/doc_download/ + * 1244570-ug0880-polarfire-soc-fpga-microprocessor-subsystem-mss-user-guide, + * describes the whole picture of the PolarFire SoC memory map. + * + * 2 A zip file for PolarFire soC memory map, which can be downloaded from + * https://www.microsemi.com/document-portal/doc_download/ + * 1244581-polarfire-soc-register-map, contains the following 2 major parts: + * - Register Map/PF_SoC_RegMap_V1_1/pfsoc_regmap.htm + * describes the complete integrated peripherals memory map + * - Register Map/PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.htm + * describes the complete IOSCB modules memory maps + */ static const struct MemmapEntry { hwaddr base; hwaddr size;