diff mbox series

[v2,1/7] riscv: Add DMA 64-bit address support

Message ID 20201022070715.14759-2-padmarao.begari@microchip.com
State Superseded
Delegated to: Andes
Headers show
Series Microchip PolarFire SoC support | expand

Commit Message

Padmarao Begari Oct. 22, 2020, 7:07 a.m. UTC
dma_addr_t holds any valid DMA address. If the DMA API only uses 32/64-bit
addresses, dma_addr_t need only be 32/64 bits wide.

Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com>
---
 arch/riscv/Kconfig             | 5 +++++
 arch/riscv/include/asm/types.h | 4 ++++
 2 files changed, 9 insertions(+)

Comments

Anup Patel Oct. 25, 2020, 5:42 a.m. UTC | #1
On Thu, Oct 22, 2020 at 1:23 PM Padmarao Begari
<padmarao.begari@microchip.com> wrote:
>
> dma_addr_t holds any valid DMA address. If the DMA API only uses 32/64-bit
> addresses, dma_addr_t need only be 32/64 bits wide.
>
> Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com>
> ---
>  arch/riscv/Kconfig             | 5 +++++
>  arch/riscv/include/asm/types.h | 4 ++++
>  2 files changed, 9 insertions(+)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index aaa3b833a5..7ab1ccff40 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -152,6 +152,11 @@ config 32BIT
>  config 64BIT
>         bool
>
> +config DMA_ADDR_T_64BIT
> +       bool
> +       depends on 64BIT
> +       default n

This should be "default y if 64BIT".

> +
>  config SIFIVE_CLINT
>         bool
>         depends on RISCV_MMODE || SPL_RISCV_MMODE
> diff --git a/arch/riscv/include/asm/types.h b/arch/riscv/include/asm/types.h
> index 403cf9a48f..b800b2d221 100644
> --- a/arch/riscv/include/asm/types.h
> +++ b/arch/riscv/include/asm/types.h
> @@ -29,7 +29,11 @@ typedef unsigned short umode_t;
>
>  #include <stddef.h>
>
> +#ifdef CONFIG_DMA_ADDR_T_64BIT
> +typedef u64 dma_addr_t;
> +#else
>  typedef u32 dma_addr_t;
> +#endif
>
>  typedef unsigned long phys_addr_t;
>  typedef unsigned long phys_size_t;
> --
> 2.17.1
>

Apart from above, looks good to me.

Reviewed-by: Anup Patel <anup.patel@wdc.com>

Regards,
Anup
Padmarao Begari Oct. 28, 2020, 4:56 a.m. UTC | #2
Hi Anup,

On Sun, Oct 25, 2020 at 11:13 AM Anup Patel <anup@brainfault.org> wrote:

> On Thu, Oct 22, 2020 at 1:23 PM Padmarao Begari
> <padmarao.begari@microchip.com> wrote:
> >
> > dma_addr_t holds any valid DMA address. If the DMA API only uses
> 32/64-bit
> > addresses, dma_addr_t need only be 32/64 bits wide.
> >
> > Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com>
> > ---
> >  arch/riscv/Kconfig             | 5 +++++
> >  arch/riscv/include/asm/types.h | 4 ++++
> >  2 files changed, 9 insertions(+)
> >
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > index aaa3b833a5..7ab1ccff40 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -152,6 +152,11 @@ config 32BIT
> >  config 64BIT
> >         bool
> >
> > +config DMA_ADDR_T_64BIT
> > +       bool
> > +       depends on 64BIT
> > +       default n
>
> This should be "default y if 64BIT".
>

Ok

>
> > +
> >  config SIFIVE_CLINT
> >         bool
> >         depends on RISCV_MMODE || SPL_RISCV_MMODE
> > diff --git a/arch/riscv/include/asm/types.h
> b/arch/riscv/include/asm/types.h
> > index 403cf9a48f..b800b2d221 100644
> > --- a/arch/riscv/include/asm/types.h
> > +++ b/arch/riscv/include/asm/types.h
> > @@ -29,7 +29,11 @@ typedef unsigned short umode_t;
> >
> >  #include <stddef.h>
> >
> > +#ifdef CONFIG_DMA_ADDR_T_64BIT
> > +typedef u64 dma_addr_t;
> > +#else
> >  typedef u32 dma_addr_t;
> > +#endif
> >
> >  typedef unsigned long phys_addr_t;
> >  typedef unsigned long phys_size_t;
> > --
> > 2.17.1
> >
>
> Apart from above, looks good to me.
>
> Reviewed-by: Anup Patel <anup.patel@wdc.com>
>

Thank you for review

Regards
Padmarao

>
> Regards,
> Anup
>
diff mbox series

Patch

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index aaa3b833a5..7ab1ccff40 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -152,6 +152,11 @@  config 32BIT
 config 64BIT
 	bool
 
+config DMA_ADDR_T_64BIT
+	bool
+	depends on 64BIT
+	default n
+
 config SIFIVE_CLINT
 	bool
 	depends on RISCV_MMODE || SPL_RISCV_MMODE
diff --git a/arch/riscv/include/asm/types.h b/arch/riscv/include/asm/types.h
index 403cf9a48f..b800b2d221 100644
--- a/arch/riscv/include/asm/types.h
+++ b/arch/riscv/include/asm/types.h
@@ -29,7 +29,11 @@  typedef unsigned short umode_t;
 
 #include <stddef.h>
 
+#ifdef CONFIG_DMA_ADDR_T_64BIT
+typedef u64 dma_addr_t;
+#else
 typedef u32 dma_addr_t;
+#endif
 
 typedef unsigned long phys_addr_t;
 typedef unsigned long phys_size_t;