| Message ID | 20200916002359.10823-1-nicoleotsuka@gmail.com |
|---|---|
| State | Deferred |
| Headers | show |
| Series | iommu/tegra-smmu: Fix tlb_mask | expand |
On Tue, Sep 15, 2020 at 05:23:59PM -0700, Nicolin Chen wrote: > The "num_tlb_lines" might not be a power-of-2 value, being 48 on > Tegra210 for example. So the current way of calculating tlb_mask > using the num_tlb_lines is not correct: tlb_mask=0x5f in case of > num_tlb_lines=48, which will trim a setting of 0x30 (48) to 0x10. > > Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> > --- > drivers/iommu/tegra-smmu.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) This is technically a prerequisite for this patch you sent out earlier: https://patchwork.ozlabs.org/project/linux-tegra/patch/20200915232803.26163-1-nicoleotsuka@gmail.com/ You should send both of those out as one series and add maintainers for both subsystems to both patches so that they can work out who will be applying them. For this pair it's probably best for Joerg to pick up both patches because this primarily concerns the Tegra SMMU, whereas the above patch only provides the per-SoC data update for the SMMU. Obviously if Joerg prefers for Krzysztof to pick up both patches that's fine with me too. In either case, please send this out as a series so that both Joerg and Krzysztof (Cc'ed for visibility) are aware of both patches. From the Tegra side: Acked-by: Thierry Reding <treding@nvidia.com> > diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c > index 84fdee473873..0becdbfea306 100644 > --- a/drivers/iommu/tegra-smmu.c > +++ b/drivers/iommu/tegra-smmu.c > @@ -1120,7 +1120,7 @@ struct tegra_smmu *tegra_smmu_probe(struct device *dev, > BIT_MASK(mc->soc->num_address_bits - SMMU_PTE_SHIFT) - 1; > dev_dbg(dev, "address bits: %u, PFN mask: %#lx\n", > mc->soc->num_address_bits, smmu->pfn_mask); > - smmu->tlb_mask = (smmu->soc->num_tlb_lines << 1) - 1; > + smmu->tlb_mask = (1 << fls(smmu->soc->num_tlb_lines)) - 1; > dev_dbg(dev, "TLB lines: %u, mask: %#lx\n", smmu->soc->num_tlb_lines, > smmu->tlb_mask); > > -- > 2.17.1 >
diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index 84fdee473873..0becdbfea306 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c @@ -1120,7 +1120,7 @@ struct tegra_smmu *tegra_smmu_probe(struct device *dev, BIT_MASK(mc->soc->num_address_bits - SMMU_PTE_SHIFT) - 1; dev_dbg(dev, "address bits: %u, PFN mask: %#lx\n", mc->soc->num_address_bits, smmu->pfn_mask); - smmu->tlb_mask = (smmu->soc->num_tlb_lines << 1) - 1; + smmu->tlb_mask = (1 << fls(smmu->soc->num_tlb_lines)) - 1; dev_dbg(dev, "TLB lines: %u, mask: %#lx\n", smmu->soc->num_tlb_lines, smmu->tlb_mask);
The "num_tlb_lines" might not be a power-of-2 value, being 48 on Tegra210 for example. So the current way of calculating tlb_mask using the num_tlb_lines is not correct: tlb_mask=0x5f in case of num_tlb_lines=48, which will trim a setting of 0x30 (48) to 0x10. Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> --- drivers/iommu/tegra-smmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)