| Message ID | 20200910074342.20421-2-kele.hwang@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | accel/tcg: Fix computing is_write for mips | expand |
On 9/10/20 12:43 AM, Kele Huang wrote: > Detect mips store instructions SWXC1 and SDXC1 for MIPS64 since > MIPS64r1, and MIPS32 since MIPS32r2. > > Signed-off-by: Kele Huang <kele.hwang@gmail.com> > --- > accel/tcg/user-exec.c | 21 +++++++++++++++++++++ > 1 file changed, 21 insertions(+) > > diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c > index bb039eb32d..e69b4d8780 100644 > --- a/accel/tcg/user-exec.c > +++ b/accel/tcg/user-exec.c > @@ -712,6 +712,27 @@ int cpu_signal_handler(int host_signum, void *pinfo, > > /* XXX: compute is_write */ > is_write = 0; > + > + /* > + * Detect store instructions. Required in all versions of MIPS64 > + * since MIPS64r1. Not available in MIPS32r1. Required by MIPS32r2 > + * and subsequent versions of MIPS32. > + */ > + switch ((insn >> 3) & 0x7) { > + case 0x1: > + switch (insn & 0x7) { > + case 0x0: /* SWXC1 */ > + case 0x1: /* SDXC1 */ > + is_write = 1; > + break; > + default: > + break; > + } > + break; > + default: > + break; You should detect all of the store instructions, not just the coprocessor ones. Compare, for example, the Sparc version around line 485. Once done, you can also remove that /* XXX */ comment just above, which indicates that there is work that needs doing. r~
Sorry for the late reply. We make a new version submit as below. Subject: [PATCH v2 1/1] accel/tcg: Fix computing of is_write for mips Detect mips store instructions in cpu_signal_handler for all MIPS versions, and set is_write if encountering such store instructions. This fixed the error while dealing with self-modified code for MIPS. Signed-off-by: Kele Huang <kele.hwang@gmail.com> Signed-off-by: Xu Zou <iwatchnima@gmail.com> --- accel/tcg/user-exec.c | 51 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 50 insertions(+), 1 deletion(-) diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index bb039eb32d..18784516e5 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -710,11 +710,60 @@ int cpu_signal_handler(int host_signum, void *pinfo, greg_t pc = uc->uc_mcontext.pc; int is_write; - /* XXX: compute is_write */ is_write = 0; + + /* Detect store by reading the instruction at the program counter. */ + uint32_t insn = *(uint32_t *)pc; + switch(insn>>29) { + case 0x5: + switch((insn>>26) & 0x7) { + case 0x0: /* SB */ + case 0x1: /* SH */ + case 0x2: /* SWL */ + case 0x3: /* SW */ + case 0x4: /* SDL */ + case 0x5: /* SDR */ + case 0x6: /* SWR */ + is_write = 1; + } + break; + case 0x7: + switch((insn>>26) & 0x7) { + case 0x0: /* SC */ + case 0x1: /* SWC1 */ + case 0x4: /* SCD */ + case 0x5: /* SDC1 */ + case 0x7: /* SD */ +#if !defined(__mips_isa_rev) || __mips_isa_rev < 6 + case 0x2: /* SWC2 */ + case 0x6: /* SDC2 */ +#endif + is_write = 1; + } + break; + } + + /* + * Required in all versions of MIPS64 since MIPS64r1. Not available + * in MIPS32r1. Required by MIPS32r2 and subsequent versions of MIPS32. + */ + switch ((insn >> 3) & 0x7) { + case 0x1: + switch (insn & 0x7) { + case 0x0: /* SWXC1 */ + case 0x1: /* SDXC1 */ + is_write = 1; + } + break; + } + return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); } +#elif defined(__misp16) || defined(__mips_micromips) + +#error "Unsupported encoding" + #elif defined(__riscv) int cpu_signal_handler(int host_signum, void *pinfo,
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index bb039eb32d..e69b4d8780 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -712,6 +712,27 @@ int cpu_signal_handler(int host_signum, void *pinfo, /* XXX: compute is_write */ is_write = 0; + + /* + * Detect store instructions. Required in all versions of MIPS64 + * since MIPS64r1. Not available in MIPS32r1. Required by MIPS32r2 + * and subsequent versions of MIPS32. + */ + switch ((insn >> 3) & 0x7) { + case 0x1: + switch (insn & 0x7) { + case 0x0: /* SWXC1 */ + case 0x1: /* SDXC1 */ + is_write = 1; + break; + default: + break; + } + break; + default: + break; + } + return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); }
Detect mips store instructions SWXC1 and SDXC1 for MIPS64 since MIPS64r1, and MIPS32 since MIPS32r2. Signed-off-by: Kele Huang <kele.hwang@gmail.com> --- accel/tcg/user-exec.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+)