| Message ID | 1312068829-8498-1-git-send-email-wd@denx.de |
|---|---|
| State | Accepted |
| Commit | e6a857da746d5d7d450e59c0f86664c6b279b1c2 |
| Headers | show |
Wolfgang, thanks for fixing. > Fix compiler warning: > > cmd_fpga.c:318: warning: passing argument 3 of 'fit_image_get_data' > from incompatible pointer type > > Adding the needed 'const' here entails a whole bunch of additonal > changes all over the FPGA code. > > Signed-off-by: Wolfgang Denk<wd@denx.de> > Cc: Andre Schwarz<andre.schwarz@matrix-vision.de> > Cc: Murray Jensen<Murray.Jensen@csiro.au> Acked-by: Andre Schwarz<andre.schwarz@matrix-vision.de> > --- > board/hymod/bsp.c | 4 ++-- > board/matrix_vision/mergerbox/fpga.c | 2 +- > board/matrix_vision/mergerbox/fpga.h | 2 +- > board/matrix_vision/mvbc_p/fpga.c | 2 +- > board/matrix_vision/mvbc_p/fpga.h | 2 +- > board/matrix_vision/mvblm7/fpga.c | 2 +- > board/matrix_vision/mvblm7/fpga.h | 2 +- > common/cmd_fpga.c | 2 +- > drivers/fpga/ACEX1K.c | 14 +++++++------- > drivers/fpga/altera.c | 4 ++-- > drivers/fpga/cyclon2.c | 12 ++++++------ > drivers/fpga/fpga.c | 8 ++++---- > drivers/fpga/spartan2.c | 24 ++++++++++++------------ > drivers/fpga/spartan3.c | 24 ++++++++++++------------ > drivers/fpga/virtex2.c | 20 ++++++++++---------- > drivers/fpga/xilinx.c | 4 ++-- > include/ACEX1K.h | 12 ++++++------ > include/altera.h | 8 ++++---- > include/fpga.h | 12 ++++++------ > include/spartan2.h | 6 +++--- > include/spartan3.h | 6 +++--- > include/virtex2.h | 6 +++--- > include/xilinx.h | 6 +++--- > 23 files changed, 92 insertions(+), 92 deletions(-) > > diff --git a/board/hymod/bsp.c b/board/hymod/bsp.c > index 9a92941..9b5895d 100644 > --- a/board/hymod/bsp.c > +++ b/board/hymod/bsp.c > @@ -75,14 +75,14 @@ DECLARE_GLOBAL_DATA_PTR; > */ > > int > -fpga_load (int mezz, uchar *addr, ulong size) > +fpga_load(int mezz, const uchar *addr, ulong size) > { > hymod_conf_t *cp =&gd->bd->bi_hymod_conf; > xlx_info_t *fp; > xlx_iopins_t *fpgaio; > volatile uchar *fpgabase; > volatile uint cnt; > - uchar *eaddr = addr + size; > + const uchar *eaddr = addr + size; > int result; > > if (mezz) > diff --git a/board/matrix_vision/mergerbox/fpga.c b/board/matrix_vision/mergerbox/fpga.c > index 673bc2c..021e9c4 100644 > --- a/board/matrix_vision/mergerbox/fpga.c > +++ b/board/matrix_vision/mergerbox/fpga.c > @@ -161,7 +161,7 @@ static inline int _write_fpga(u8 val, int dump) > return 0; > } > > -int fpga_wr_fn(void *buf, size_t len, int flush, int cookie) > +int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie) > { > unsigned char *data = (unsigned char *) buf; > int i; > diff --git a/board/matrix_vision/mergerbox/fpga.h b/board/matrix_vision/mergerbox/fpga.h > index fccff9f..89f879a 100644 > --- a/board/matrix_vision/mergerbox/fpga.h > +++ b/board/matrix_vision/mergerbox/fpga.h > @@ -26,5 +26,5 @@ extern int fpga_status_fn(int cookie); > extern int fpga_config_fn(int assert, int flush, int cookie); > extern int fpga_done_fn(int cookie); > extern int fpga_clk_fn(int assert_clk, int flush, int cookie); > -extern int fpga_wr_fn(void *buf, size_t len, int flush, int cookie); > +extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie); > extern int fpga_null_fn(int cookie); > diff --git a/board/matrix_vision/mvbc_p/fpga.c b/board/matrix_vision/mvbc_p/fpga.c > index 3ed46fe..6ce96ba 100644 > --- a/board/matrix_vision/mvbc_p/fpga.c > +++ b/board/matrix_vision/mvbc_p/fpga.c > @@ -160,7 +160,7 @@ static inline int _write_fpga(u8 val) > return 0; > } > > -int fpga_wr_fn(void *buf, size_t len, int flush, int cookie) > +int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie) > { > unsigned char *data = (unsigned char *) buf; > int i; > diff --git a/board/matrix_vision/mvbc_p/fpga.h b/board/matrix_vision/mvbc_p/fpga.h > index 3723073..8f74a00 100644 > --- a/board/matrix_vision/mvbc_p/fpga.h > +++ b/board/matrix_vision/mvbc_p/fpga.h > @@ -30,5 +30,5 @@ extern int fpga_status_fn(int cookie); > extern int fpga_config_fn(int assert, int flush, int cookie); > extern int fpga_done_fn(int cookie); > extern int fpga_clk_fn(int assert_clk, int flush, int cookie); > -extern int fpga_wr_fn(void *buf, size_t len, int flush, int cookie); > +extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie); > extern int fpga_null_fn(int cookie); > diff --git a/board/matrix_vision/mvblm7/fpga.c b/board/matrix_vision/mvblm7/fpga.c > index 7b03d6f..dc5a738 100644 > --- a/board/matrix_vision/mvblm7/fpga.c > +++ b/board/matrix_vision/mvblm7/fpga.c > @@ -172,7 +172,7 @@ static inline int _write_fpga(u8 val, int dump) > return 0; > } > > -int fpga_wr_fn(void *buf, size_t len, int flush, int cookie) > +int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie) > { > unsigned char *data = (unsigned char *) buf; > int i; > diff --git a/board/matrix_vision/mvblm7/fpga.h b/board/matrix_vision/mvblm7/fpga.h > index 19277eb..f422f20 100644 > --- a/board/matrix_vision/mvblm7/fpga.h > +++ b/board/matrix_vision/mvblm7/fpga.h > @@ -30,5 +30,5 @@ extern int fpga_status_fn(int cookie); > extern int fpga_config_fn(int assert, int flush, int cookie); > extern int fpga_done_fn(int cookie); > extern int fpga_clk_fn(int assert_clk, int flush, int cookie); > -extern int fpga_wr_fn(void *buf, size_t len, int flush, int cookie); > +extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie); > extern int fpga_null_fn(int cookie); > diff --git a/common/cmd_fpga.c b/common/cmd_fpga.c > index 0ad310f..8946345 100644 > --- a/common/cmd_fpga.c > +++ b/common/cmd_fpga.c > @@ -289,7 +289,7 @@ int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) > { > const void *fit_hdr = (const void *)fpga_data; > int noffset; > - void *fit_data; > + const void *fit_data; > > if (fit_uname == NULL) { > puts ("No FIT subimage unit name\n"); > diff --git a/drivers/fpga/ACEX1K.c b/drivers/fpga/ACEX1K.c > index 06b4247..fa3fb68 100644 > --- a/drivers/fpga/ACEX1K.c > +++ b/drivers/fpga/ACEX1K.c > @@ -48,13 +48,13 @@ > #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/10 /* 100 ms */ > #endif > > -static int ACEX1K_ps_load( Altera_desc *desc, void *buf, size_t bsize ); > -static int ACEX1K_ps_dump( Altera_desc *desc, void *buf, size_t bsize ); > -/* static int ACEX1K_ps_info( Altera_desc *desc ); */ > +static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize); > +static int ACEX1K_ps_dump(Altera_desc *desc, const void *buf, size_t bsize); > +/* static int ACEX1K_ps_info(Altera_desc *desc); */ > > /* ------------------------------------------------------------------------- */ > /* ACEX1K Generic Implementation */ > -int ACEX1K_load (Altera_desc * desc, void *buf, size_t bsize) > +int ACEX1K_load(Altera_desc *desc, const void *buf, size_t bsize) > { > int ret_val = FPGA_FAIL; > > @@ -74,7 +74,7 @@ int ACEX1K_load (Altera_desc * desc, void *buf, size_t bsize) > return ret_val; > } > > -int ACEX1K_dump (Altera_desc * desc, void *buf, size_t bsize) > +int ACEX1K_dump(Altera_desc *desc, const void *buf, size_t bsize) > { > int ret_val = FPGA_FAIL; > > @@ -103,7 +103,7 @@ int ACEX1K_info( Altera_desc *desc ) > /* ------------------------------------------------------------------------- */ > /* ACEX1K Passive Serial Generic Implementation */ > > -static int ACEX1K_ps_load (Altera_desc * desc, void *buf, size_t bsize) > +static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize) > { > int ret_val = FPGA_FAIL; /* assume the worst */ > Altera_ACEX1K_Passive_Serial_fns *fn = desc->iface_fns; > @@ -256,7 +256,7 @@ static int ACEX1K_ps_load (Altera_desc * desc, void *buf, size_t bsize) > return ret_val; > } > > -static int ACEX1K_ps_dump (Altera_desc * desc, void *buf, size_t bsize) > +static int ACEX1K_ps_dump(Altera_desc *desc, const void *buf, size_t bsize) > { > /* Readback is only available through the Slave Parallel and */ > /* boundary-scan interfaces. */ > diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c > index 103d81c..f087d01 100644 > --- a/drivers/fpga/altera.c > +++ b/drivers/fpga/altera.c > @@ -45,7 +45,7 @@ > static int altera_validate (Altera_desc * desc, const char *fn); > > /* ------------------------------------------------------------------------- */ > -int altera_load( Altera_desc *desc, void *buf, size_t bsize ) > +int altera_load(Altera_desc *desc, const void *buf, size_t bsize) > { > int ret_val = FPGA_FAIL; /* assume a failure */ > > @@ -85,7 +85,7 @@ int altera_load( Altera_desc *desc, void *buf, size_t bsize ) > return ret_val; > } > > -int altera_dump( Altera_desc *desc, void *buf, size_t bsize ) > +int altera_dump(Altera_desc *desc, const void *buf, size_t bsize) > { > int ret_val = FPGA_FAIL; /* assume a failure */ > > diff --git a/drivers/fpga/cyclon2.c b/drivers/fpga/cyclon2.c > index 567099e..eb05a32 100644 > --- a/drivers/fpga/cyclon2.c > +++ b/drivers/fpga/cyclon2.c > @@ -47,13 +47,13 @@ > #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/10 /* 100 ms */ > #endif > > -static int CYC2_ps_load( Altera_desc *desc, void *buf, size_t bsize ); > -static int CYC2_ps_dump( Altera_desc *desc, void *buf, size_t bsize ); > +static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize); > +static int CYC2_ps_dump(Altera_desc *desc, const void *buf, size_t bsize); > /* static int CYC2_ps_info( Altera_desc *desc ); */ > > /* ------------------------------------------------------------------------- */ > /* CYCLON2 Generic Implementation */ > -int CYC2_load (Altera_desc * desc, void *buf, size_t bsize) > +int CYC2_load(Altera_desc *desc, const void *buf, size_t bsize) > { > int ret_val = FPGA_FAIL; > > @@ -83,7 +83,7 @@ int CYC2_load (Altera_desc * desc, void *buf, size_t bsize) > return ret_val; > } > > -int CYC2_dump (Altera_desc * desc, void *buf, size_t bsize) > +int CYC2_dump(Altera_desc *desc, const void *buf, size_t bsize) > { > int ret_val = FPGA_FAIL; > > @@ -110,7 +110,7 @@ int CYC2_info( Altera_desc *desc ) > > /* ------------------------------------------------------------------------- */ > /* CYCLON2 Passive Serial Generic Implementation */ > -static int CYC2_ps_load (Altera_desc * desc, void *buf, size_t bsize) > +static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize) > { > int ret_val = FPGA_FAIL; /* assume the worst */ > Altera_CYC2_Passive_Serial_fns *fn = desc->iface_fns; > @@ -210,7 +210,7 @@ static int CYC2_ps_load (Altera_desc * desc, void *buf, size_t bsize) > return ret_val; > } > > -static int CYC2_ps_dump (Altera_desc * desc, void *buf, size_t bsize) > +static int CYC2_ps_dump(Altera_desc *desc, const void *buf, size_t bsize) > { > /* Readback is only available through the Slave Parallel and */ > /* boundary-scan interfaces. */ > diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c > index a669039..02a0796 100644 > --- a/drivers/fpga/fpga.c > +++ b/drivers/fpga/fpga.c > @@ -52,7 +52,7 @@ static fpga_desc desc_table[CONFIG_MAX_FPGA_DEVICES]; > > /* Local static functions */ > static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_get_desc( int devnum ); > -static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_validate( int devnum, void *buf, > +static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_validate(int devnum, const void *buf, > size_t bsize, char *fn ); > static int fpga_dev_info( int devnum ); > > @@ -94,7 +94,7 @@ static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_ge > /* fpga_validate > * generic parameter checking code > */ > -static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_validate( int devnum, void *buf, > +static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_validate(int devnum, const void *buf, > size_t bsize, char *fn ) > { > fpga_desc * desc = fpga_get_desc( devnum ); > @@ -212,7 +212,7 @@ int fpga_add( fpga_type devtype, void *desc ) > /* > * Generic multiplexing code > */ > -int fpga_load( int devnum, void *buf, size_t bsize ) > +int fpga_load(int devnum, const void *buf, size_t bsize) > { > int ret_val = FPGA_FAIL; /* assume failure */ > fpga_desc * desc = fpga_validate( devnum, buf, bsize, (char *)__FUNCTION__ ); > @@ -252,7 +252,7 @@ int fpga_load( int devnum, void *buf, size_t bsize ) > /* fpga_dump > * generic multiplexing code > */ > -int fpga_dump( int devnum, void *buf, size_t bsize ) > +int fpga_dump(int devnum, const void *buf, size_t bsize) > { > int ret_val = FPGA_FAIL; /* assume failure */ > fpga_desc * desc = fpga_validate( devnum, buf, bsize, (char *)__FUNCTION__ ); > diff --git a/drivers/fpga/spartan2.c b/drivers/fpga/spartan2.c > index cd16a9c..e72deee 100644 > --- a/drivers/fpga/spartan2.c > +++ b/drivers/fpga/spartan2.c > @@ -48,17 +48,17 @@ > #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ > #endif > > -static int Spartan2_sp_load( Xilinx_desc *desc, void *buf, size_t bsize ); > -static int Spartan2_sp_dump( Xilinx_desc *desc, void *buf, size_t bsize ); > -/* static int Spartan2_sp_info( Xilinx_desc *desc ); */ > +static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize); > +static int Spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize); > +/* static int Spartan2_sp_info(Xilinx_desc *desc ); */ > > -static int Spartan2_ss_load( Xilinx_desc *desc, void *buf, size_t bsize ); > -static int Spartan2_ss_dump( Xilinx_desc *desc, void *buf, size_t bsize ); > -/* static int Spartan2_ss_info( Xilinx_desc *desc ); */ > +static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize); > +static int Spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize); > +/* static int Spartan2_ss_info(Xilinx_desc *desc ); */ > > /* ------------------------------------------------------------------------- */ > /* Spartan-II Generic Implementation */ > -int Spartan2_load (Xilinx_desc * desc, void *buf, size_t bsize) > +int Spartan2_load(Xilinx_desc *desc, const void *buf, size_t bsize) > { > int ret_val = FPGA_FAIL; > > @@ -81,7 +81,7 @@ int Spartan2_load (Xilinx_desc * desc, void *buf, size_t bsize) > return ret_val; > } > > -int Spartan2_dump (Xilinx_desc * desc, void *buf, size_t bsize) > +int Spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize) > { > int ret_val = FPGA_FAIL; > > @@ -113,7 +113,7 @@ int Spartan2_info( Xilinx_desc *desc ) > /* ------------------------------------------------------------------------- */ > /* Spartan-II Slave Parallel Generic Implementation */ > > -static int Spartan2_sp_load (Xilinx_desc * desc, void *buf, size_t bsize) > +static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) > { > int ret_val = FPGA_FAIL; /* assume the worst */ > Xilinx_Spartan2_Slave_Parallel_fns *fn = desc->iface_fns; > @@ -265,7 +265,7 @@ static int Spartan2_sp_load (Xilinx_desc * desc, void *buf, size_t bsize) > return ret_val; > } > > -static int Spartan2_sp_dump (Xilinx_desc * desc, void *buf, size_t bsize) > +static int Spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) > { > int ret_val = FPGA_FAIL; /* assume the worst */ > Xilinx_Spartan2_Slave_Parallel_fns *fn = desc->iface_fns; > @@ -313,7 +313,7 @@ static int Spartan2_sp_dump (Xilinx_desc * desc, void *buf, size_t bsize) > > /* ------------------------------------------------------------------------- */ > > -static int Spartan2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) > +static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) > { > int ret_val = FPGA_FAIL; /* assume the worst */ > Xilinx_Spartan2_Slave_Serial_fns *fn = desc->iface_fns; > @@ -456,7 +456,7 @@ static int Spartan2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) > return ret_val; > } > > -static int Spartan2_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize) > +static int Spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize) > { > /* Readback is only available through the Slave Parallel and */ > /* boundary-scan interfaces. */ > diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c > index 1dd6f26..d2f8549 100644 > --- a/drivers/fpga/spartan3.c > +++ b/drivers/fpga/spartan3.c > @@ -53,17 +53,17 @@ > #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ > #endif > > -static int Spartan3_sp_load( Xilinx_desc *desc, void *buf, size_t bsize ); > -static int Spartan3_sp_dump( Xilinx_desc *desc, void *buf, size_t bsize ); > -/* static int Spartan3_sp_info( Xilinx_desc *desc ); */ > +static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize); > +static int Spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize); > +/* static int Spartan3_sp_info(Xilinx_desc *desc ); */ > > -static int Spartan3_ss_load( Xilinx_desc *desc, void *buf, size_t bsize ); > -static int Spartan3_ss_dump( Xilinx_desc *desc, void *buf, size_t bsize ); > -/* static int Spartan3_ss_info( Xilinx_desc *desc ); */ > +static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize); > +static int Spartan3_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize); > +/* static int Spartan3_ss_info(Xilinx_desc *desc); */ > > /* ------------------------------------------------------------------------- */ > /* Spartan-II Generic Implementation */ > -int Spartan3_load (Xilinx_desc * desc, void *buf, size_t bsize) > +int Spartan3_load(Xilinx_desc *desc, const void *buf, size_t bsize) > { > int ret_val = FPGA_FAIL; > > @@ -86,7 +86,7 @@ int Spartan3_load (Xilinx_desc * desc, void *buf, size_t bsize) > return ret_val; > } > > -int Spartan3_dump (Xilinx_desc * desc, void *buf, size_t bsize) > +int Spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize) > { > int ret_val = FPGA_FAIL; > > @@ -118,7 +118,7 @@ int Spartan3_info( Xilinx_desc *desc ) > /* ------------------------------------------------------------------------- */ > /* Spartan-II Slave Parallel Generic Implementation */ > > -static int Spartan3_sp_load (Xilinx_desc * desc, void *buf, size_t bsize) > +static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) > { > int ret_val = FPGA_FAIL; /* assume the worst */ > Xilinx_Spartan3_Slave_Parallel_fns *fn = desc->iface_fns; > @@ -272,7 +272,7 @@ static int Spartan3_sp_load (Xilinx_desc * desc, void *buf, size_t bsize) > return ret_val; > } > > -static int Spartan3_sp_dump (Xilinx_desc * desc, void *buf, size_t bsize) > +static int Spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) > { > int ret_val = FPGA_FAIL; /* assume the worst */ > Xilinx_Spartan3_Slave_Parallel_fns *fn = desc->iface_fns; > @@ -320,7 +320,7 @@ static int Spartan3_sp_dump (Xilinx_desc * desc, void *buf, size_t bsize) > > /* ------------------------------------------------------------------------- */ > > -static int Spartan3_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) > +static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) > { > int ret_val = FPGA_FAIL; /* assume the worst */ > Xilinx_Spartan3_Slave_Serial_fns *fn = desc->iface_fns; > @@ -475,7 +475,7 @@ static int Spartan3_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) > return ret_val; > } > > -static int Spartan3_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize) > +static int Spartan3_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize) > { > /* Readback is only available through the Slave Parallel and */ > /* boundary-scan interfaces. */ > diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c > index d1b4d15..9814d5e 100644 > --- a/drivers/fpga/virtex2.c > +++ b/drivers/fpga/virtex2.c > @@ -101,13 +101,13 @@ > #define CONFIG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ/5 /* 200 ms */ > #endif > > -static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize); > -static int Virtex2_ssm_dump (Xilinx_desc * desc, void *buf, size_t bsize); > +static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize); > +static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize); > > -static int Virtex2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize); > -static int Virtex2_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize); > +static int Virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize); > +static int Virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize); > > -int Virtex2_load (Xilinx_desc * desc, void *buf, size_t bsize) > +int Virtex2_load(Xilinx_desc *desc, const void *buf, size_t bsize) > { > int ret_val = FPGA_FAIL; > > @@ -129,7 +129,7 @@ int Virtex2_load (Xilinx_desc * desc, void *buf, size_t bsize) > return ret_val; > } > > -int Virtex2_dump (Xilinx_desc * desc, void *buf, size_t bsize) > +int Virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize) > { > int ret_val = FPGA_FAIL; > > @@ -170,7 +170,7 @@ int Virtex2_info (Xilinx_desc * desc) > * INIT_B and DONE lines. If both are high, configuration has > * succeeded. Congratulations! > */ > -static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize) > +static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize) > { > int ret_val = FPGA_FAIL; > Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc->iface_fns; > @@ -369,7 +369,7 @@ static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize) > /* > * Read the FPGA configuration data > */ > -static int Virtex2_ssm_dump (Xilinx_desc * desc, void *buf, size_t bsize) > +static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize) > { > int ret_val = FPGA_FAIL; > Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc->iface_fns; > @@ -421,13 +421,13 @@ static int Virtex2_ssm_dump (Xilinx_desc * desc, void *buf, size_t bsize) > return ret_val; > } > > -static int Virtex2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) > +static int Virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) > { > printf ("%s: Slave Serial Loading is unsupported\n", __FUNCTION__); > return FPGA_FAIL; > } > > -static int Virtex2_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize) > +static int Virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize) > { > printf ("%s: Slave Serial Dumping is unsupported\n", __FUNCTION__); > return FPGA_FAIL; > diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c > index 08dfdec..137916f 100644 > --- a/drivers/fpga/xilinx.c > +++ b/drivers/fpga/xilinx.c > @@ -48,7 +48,7 @@ static int xilinx_validate (Xilinx_desc * desc, char *fn); > > /* ------------------------------------------------------------------------- */ > > -int xilinx_load (Xilinx_desc * desc, void *buf, size_t bsize) > +int xilinx_load(Xilinx_desc *desc, const void *buf, size_t bsize) > { > int ret_val = FPGA_FAIL; /* assume a failure */ > > @@ -95,7 +95,7 @@ int xilinx_load (Xilinx_desc * desc, void *buf, size_t bsize) > return ret_val; > } > > -int xilinx_dump (Xilinx_desc * desc, void *buf, size_t bsize) > +int xilinx_dump(Xilinx_desc *desc, const void *buf, size_t bsize) > { > int ret_val = FPGA_FAIL; /* assume a failure */ > > diff --git a/include/ACEX1K.h b/include/ACEX1K.h > index 2bb9226..e2e96d2 100644 > --- a/include/ACEX1K.h > +++ b/include/ACEX1K.h > @@ -30,13 +30,13 @@ > > #include<altera.h> > > -extern int ACEX1K_load( Altera_desc *desc, void *image, size_t size ); > -extern int ACEX1K_dump( Altera_desc *desc, void *buf, size_t bsize ); > -extern int ACEX1K_info( Altera_desc *desc ); > +extern int ACEX1K_load(Altera_desc *desc, const void *image, size_t size); > +extern int ACEX1K_dump(Altera_desc *desc, const void *buf, size_t bsize); > +extern int ACEX1K_info(Altera_desc *desc); > > -extern int CYC2_load( Altera_desc *desc, void *image, size_t size ); > -extern int CYC2_dump( Altera_desc *desc, void *buf, size_t bsize ); > -extern int CYC2_info( Altera_desc *desc ); > +extern int CYC2_load(Altera_desc *desc, const void *image, size_t size); > +extern int CYC2_dump(Altera_desc *desc, const void *buf, size_t bsize); > +extern int CYC2_info(Altera_desc *desc); > > /* Slave Serial Implementation function table */ > typedef struct { > diff --git a/include/altera.h b/include/altera.h > index f28a6a8..686148f 100644 > --- a/include/altera.h > +++ b/include/altera.h > @@ -76,9 +76,9 @@ typedef struct { /* typedef Altera_desc */ > > /* Generic Altera Functions > *********************************************************************/ > -extern int altera_load( Altera_desc *desc, void *image, size_t size ); > -extern int altera_dump( Altera_desc *desc, void *buf, size_t bsize ); > -extern int altera_info( Altera_desc *desc ); > +extern int altera_load(Altera_desc *desc, const void *image, size_t size); > +extern int altera_dump(Altera_desc *desc, const void *buf, size_t bsize); > +extern int altera_info(Altera_desc *desc); > > /* Board specific implementation specific function types > *********************************************************************/ > @@ -88,7 +88,7 @@ typedef int (*Altera_status_fn)( int cookie ); > typedef int (*Altera_done_fn)( int cookie ); > typedef int (*Altera_clk_fn)( int assert_clk, int flush, int cookie ); > typedef int (*Altera_data_fn)( int assert_data, int flush, int cookie ); > -typedef int (*Altera_write_fn)(void *buf, size_t len, int flush, int cookie); > +typedef int(*Altera_write_fn)(const void *buf, size_t len, int flush, int cookie); > typedef int (*Altera_abort_fn)( int cookie ); > typedef int (*Altera_post_fn)( int cookie ); > > diff --git a/include/fpga.h b/include/fpga.h > index ac24f2b..e0b1fe7 100644 > --- a/include/fpga.h > +++ b/include/fpga.h > @@ -72,11 +72,11 @@ typedef struct { /* typedef fpga_desc */ > > > /* root function definitions */ > -extern void fpga_init( void ); > -extern int fpga_add( fpga_type devtype, void *desc ); > -extern int fpga_count( void ); > -extern int fpga_load( int devnum, void *buf, size_t bsize ); > -extern int fpga_dump( int devnum, void *buf, size_t bsize ); > -extern int fpga_info( int devnum ); > +extern void fpga_init(void); > +extern int fpga_add(fpga_type devtype, void *desc); > +extern int fpga_count(void); > +extern int fpga_load(int devnum, const void *buf, size_t bsize); > +extern int fpga_dump(int devnum, const void *buf, size_t bsize); > +extern int fpga_info(int devnum); > > #endif /* _FPGA_H_ */ > diff --git a/include/spartan2.h b/include/spartan2.h > index 8959f90..e257a67 100644 > --- a/include/spartan2.h > +++ b/include/spartan2.h > @@ -27,9 +27,9 @@ > > #include<xilinx.h> > > -extern int Spartan2_load( Xilinx_desc *desc, void *image, size_t size ); > -extern int Spartan2_dump( Xilinx_desc *desc, void *buf, size_t bsize ); > -extern int Spartan2_info( Xilinx_desc *desc ); > +extern int Spartan2_load(Xilinx_desc *desc, const void *image, size_t size); > +extern int Spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize); > +extern int Spartan2_info(Xilinx_desc *desc); > > /* Slave Parallel Implementation function table */ > typedef struct { > diff --git a/include/spartan3.h b/include/spartan3.h > index 0f0b400..67ede4b 100644 > --- a/include/spartan3.h > +++ b/include/spartan3.h > @@ -27,9 +27,9 @@ > > #include<xilinx.h> > > -extern int Spartan3_load( Xilinx_desc *desc, void *image, size_t size ); > -extern int Spartan3_dump( Xilinx_desc *desc, void *buf, size_t bsize ); > -extern int Spartan3_info( Xilinx_desc *desc ); > +extern int Spartan3_load(Xilinx_desc *desc, const void *image, size_t size); > +extern int Spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize); > +extern int Spartan3_info(Xilinx_desc *desc); > > /* Slave Parallel Implementation function table */ > typedef struct { > diff --git a/include/virtex2.h b/include/virtex2.h > index 89d7d76..4717e0c 100644 > --- a/include/virtex2.h > +++ b/include/virtex2.h > @@ -28,9 +28,9 @@ > > #include<xilinx.h> > > -extern int Virtex2_load( Xilinx_desc *desc, void *image, size_t size ); > -extern int Virtex2_dump( Xilinx_desc *desc, void *buf, size_t bsize ); > -extern int Virtex2_info( Xilinx_desc *desc ); > +extern int Virtex2_load(Xilinx_desc *desc, const void *image, size_t size); > +extern int Virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize); > +extern int Virtex2_info(Xilinx_desc *desc); > > /* > * Slave SelectMap Implementation function table. > diff --git a/include/xilinx.h b/include/xilinx.h > index 2cb2e5b..5f25b7a 100644 > --- a/include/xilinx.h > +++ b/include/xilinx.h > @@ -81,9 +81,9 @@ typedef struct { /* typedef Xilinx_desc */ > > /* Generic Xilinx Functions > *********************************************************************/ > -extern int xilinx_load( Xilinx_desc *desc, void *image, size_t size ); > -extern int xilinx_dump( Xilinx_desc *desc, void *buf, size_t bsize ); > -extern int xilinx_info( Xilinx_desc *desc ); > +extern int xilinx_load(Xilinx_desc *desc, const void *image, size_t size); > +extern int xilinx_dump(Xilinx_desc *desc, const void *buf, size_t bsize); > +extern int xilinx_info(Xilinx_desc *desc); > > /* Board specific implementation specific function types > *********************************************************************/
Dear Wolfgang Denk, In message <1312068829-8498-1-git-send-email-wd@denx.de> you wrote: > Fix compiler warning: > > cmd_fpga.c:318: warning: passing argument 3 of 'fit_image_get_data' > from incompatible pointer type > > Adding the needed 'const' here entails a whole bunch of additonal > changes all over the FPGA code. > > Signed-off-by: Wolfgang Denk <wd@denx.de> > Cc: Andre Schwarz <andre.schwarz@matrix-vision.de> > Cc: Murray Jensen <Murray.Jensen@csiro.au> > --- > board/hymod/bsp.c | 4 ++-- > board/matrix_vision/mergerbox/fpga.c | 2 +- > board/matrix_vision/mergerbox/fpga.h | 2 +- > board/matrix_vision/mvbc_p/fpga.c | 2 +- > board/matrix_vision/mvbc_p/fpga.h | 2 +- > board/matrix_vision/mvblm7/fpga.c | 2 +- > board/matrix_vision/mvblm7/fpga.h | 2 +- > common/cmd_fpga.c | 2 +- > drivers/fpga/ACEX1K.c | 14 +++++++------- > drivers/fpga/altera.c | 4 ++-- > drivers/fpga/cyclon2.c | 12 ++++++------ > drivers/fpga/fpga.c | 8 ++++---- > drivers/fpga/spartan2.c | 24 ++++++++++++------------ > drivers/fpga/spartan3.c | 24 ++++++++++++------------ > drivers/fpga/virtex2.c | 20 ++++++++++---------- > drivers/fpga/xilinx.c | 4 ++-- > include/ACEX1K.h | 12 ++++++------ > include/altera.h | 8 ++++---- > include/fpga.h | 12 ++++++------ > include/spartan2.h | 6 +++--- > include/spartan3.h | 6 +++--- > include/virtex2.h | 6 +++--- > include/xilinx.h | 6 +++--- > 23 files changed, 92 insertions(+), 92 deletions(-) Applied, thanks. Best regards, Wolfgang Denk
diff --git a/board/hymod/bsp.c b/board/hymod/bsp.c index 9a92941..9b5895d 100644 --- a/board/hymod/bsp.c +++ b/board/hymod/bsp.c @@ -75,14 +75,14 @@ DECLARE_GLOBAL_DATA_PTR; */ int -fpga_load (int mezz, uchar *addr, ulong size) +fpga_load(int mezz, const uchar *addr, ulong size) { hymod_conf_t *cp = &gd->bd->bi_hymod_conf; xlx_info_t *fp; xlx_iopins_t *fpgaio; volatile uchar *fpgabase; volatile uint cnt; - uchar *eaddr = addr + size; + const uchar *eaddr = addr + size; int result; if (mezz) diff --git a/board/matrix_vision/mergerbox/fpga.c b/board/matrix_vision/mergerbox/fpga.c index 673bc2c..021e9c4 100644 --- a/board/matrix_vision/mergerbox/fpga.c +++ b/board/matrix_vision/mergerbox/fpga.c @@ -161,7 +161,7 @@ static inline int _write_fpga(u8 val, int dump) return 0; } -int fpga_wr_fn(void *buf, size_t len, int flush, int cookie) +int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie) { unsigned char *data = (unsigned char *) buf; int i; diff --git a/board/matrix_vision/mergerbox/fpga.h b/board/matrix_vision/mergerbox/fpga.h index fccff9f..89f879a 100644 --- a/board/matrix_vision/mergerbox/fpga.h +++ b/board/matrix_vision/mergerbox/fpga.h @@ -26,5 +26,5 @@ extern int fpga_status_fn(int cookie); extern int fpga_config_fn(int assert, int flush, int cookie); extern int fpga_done_fn(int cookie); extern int fpga_clk_fn(int assert_clk, int flush, int cookie); -extern int fpga_wr_fn(void *buf, size_t len, int flush, int cookie); +extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie); extern int fpga_null_fn(int cookie); diff --git a/board/matrix_vision/mvbc_p/fpga.c b/board/matrix_vision/mvbc_p/fpga.c index 3ed46fe..6ce96ba 100644 --- a/board/matrix_vision/mvbc_p/fpga.c +++ b/board/matrix_vision/mvbc_p/fpga.c @@ -160,7 +160,7 @@ static inline int _write_fpga(u8 val) return 0; } -int fpga_wr_fn(void *buf, size_t len, int flush, int cookie) +int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie) { unsigned char *data = (unsigned char *) buf; int i; diff --git a/board/matrix_vision/mvbc_p/fpga.h b/board/matrix_vision/mvbc_p/fpga.h index 3723073..8f74a00 100644 --- a/board/matrix_vision/mvbc_p/fpga.h +++ b/board/matrix_vision/mvbc_p/fpga.h @@ -30,5 +30,5 @@ extern int fpga_status_fn(int cookie); extern int fpga_config_fn(int assert, int flush, int cookie); extern int fpga_done_fn(int cookie); extern int fpga_clk_fn(int assert_clk, int flush, int cookie); -extern int fpga_wr_fn(void *buf, size_t len, int flush, int cookie); +extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie); extern int fpga_null_fn(int cookie); diff --git a/board/matrix_vision/mvblm7/fpga.c b/board/matrix_vision/mvblm7/fpga.c index 7b03d6f..dc5a738 100644 --- a/board/matrix_vision/mvblm7/fpga.c +++ b/board/matrix_vision/mvblm7/fpga.c @@ -172,7 +172,7 @@ static inline int _write_fpga(u8 val, int dump) return 0; } -int fpga_wr_fn(void *buf, size_t len, int flush, int cookie) +int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie) { unsigned char *data = (unsigned char *) buf; int i; diff --git a/board/matrix_vision/mvblm7/fpga.h b/board/matrix_vision/mvblm7/fpga.h index 19277eb..f422f20 100644 --- a/board/matrix_vision/mvblm7/fpga.h +++ b/board/matrix_vision/mvblm7/fpga.h @@ -30,5 +30,5 @@ extern int fpga_status_fn(int cookie); extern int fpga_config_fn(int assert, int flush, int cookie); extern int fpga_done_fn(int cookie); extern int fpga_clk_fn(int assert_clk, int flush, int cookie); -extern int fpga_wr_fn(void *buf, size_t len, int flush, int cookie); +extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie); extern int fpga_null_fn(int cookie); diff --git a/common/cmd_fpga.c b/common/cmd_fpga.c index 0ad310f..8946345 100644 --- a/common/cmd_fpga.c +++ b/common/cmd_fpga.c @@ -289,7 +289,7 @@ int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) { const void *fit_hdr = (const void *)fpga_data; int noffset; - void *fit_data; + const void *fit_data; if (fit_uname == NULL) { puts ("No FIT subimage unit name\n"); diff --git a/drivers/fpga/ACEX1K.c b/drivers/fpga/ACEX1K.c index 06b4247..fa3fb68 100644 --- a/drivers/fpga/ACEX1K.c +++ b/drivers/fpga/ACEX1K.c @@ -48,13 +48,13 @@ #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/10 /* 100 ms */ #endif -static int ACEX1K_ps_load( Altera_desc *desc, void *buf, size_t bsize ); -static int ACEX1K_ps_dump( Altera_desc *desc, void *buf, size_t bsize ); -/* static int ACEX1K_ps_info( Altera_desc *desc ); */ +static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize); +static int ACEX1K_ps_dump(Altera_desc *desc, const void *buf, size_t bsize); +/* static int ACEX1K_ps_info(Altera_desc *desc); */ /* ------------------------------------------------------------------------- */ /* ACEX1K Generic Implementation */ -int ACEX1K_load (Altera_desc * desc, void *buf, size_t bsize) +int ACEX1K_load(Altera_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -74,7 +74,7 @@ int ACEX1K_load (Altera_desc * desc, void *buf, size_t bsize) return ret_val; } -int ACEX1K_dump (Altera_desc * desc, void *buf, size_t bsize) +int ACEX1K_dump(Altera_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -103,7 +103,7 @@ int ACEX1K_info( Altera_desc *desc ) /* ------------------------------------------------------------------------- */ /* ACEX1K Passive Serial Generic Implementation */ -static int ACEX1K_ps_load (Altera_desc * desc, void *buf, size_t bsize) +static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ Altera_ACEX1K_Passive_Serial_fns *fn = desc->iface_fns; @@ -256,7 +256,7 @@ static int ACEX1K_ps_load (Altera_desc * desc, void *buf, size_t bsize) return ret_val; } -static int ACEX1K_ps_dump (Altera_desc * desc, void *buf, size_t bsize) +static int ACEX1K_ps_dump(Altera_desc *desc, const void *buf, size_t bsize) { /* Readback is only available through the Slave Parallel and */ /* boundary-scan interfaces. */ diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c index 103d81c..f087d01 100644 --- a/drivers/fpga/altera.c +++ b/drivers/fpga/altera.c @@ -45,7 +45,7 @@ static int altera_validate (Altera_desc * desc, const char *fn); /* ------------------------------------------------------------------------- */ -int altera_load( Altera_desc *desc, void *buf, size_t bsize ) +int altera_load(Altera_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume a failure */ @@ -85,7 +85,7 @@ int altera_load( Altera_desc *desc, void *buf, size_t bsize ) return ret_val; } -int altera_dump( Altera_desc *desc, void *buf, size_t bsize ) +int altera_dump(Altera_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume a failure */ diff --git a/drivers/fpga/cyclon2.c b/drivers/fpga/cyclon2.c index 567099e..eb05a32 100644 --- a/drivers/fpga/cyclon2.c +++ b/drivers/fpga/cyclon2.c @@ -47,13 +47,13 @@ #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/10 /* 100 ms */ #endif -static int CYC2_ps_load( Altera_desc *desc, void *buf, size_t bsize ); -static int CYC2_ps_dump( Altera_desc *desc, void *buf, size_t bsize ); +static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize); +static int CYC2_ps_dump(Altera_desc *desc, const void *buf, size_t bsize); /* static int CYC2_ps_info( Altera_desc *desc ); */ /* ------------------------------------------------------------------------- */ /* CYCLON2 Generic Implementation */ -int CYC2_load (Altera_desc * desc, void *buf, size_t bsize) +int CYC2_load(Altera_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -83,7 +83,7 @@ int CYC2_load (Altera_desc * desc, void *buf, size_t bsize) return ret_val; } -int CYC2_dump (Altera_desc * desc, void *buf, size_t bsize) +int CYC2_dump(Altera_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -110,7 +110,7 @@ int CYC2_info( Altera_desc *desc ) /* ------------------------------------------------------------------------- */ /* CYCLON2 Passive Serial Generic Implementation */ -static int CYC2_ps_load (Altera_desc * desc, void *buf, size_t bsize) +static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ Altera_CYC2_Passive_Serial_fns *fn = desc->iface_fns; @@ -210,7 +210,7 @@ static int CYC2_ps_load (Altera_desc * desc, void *buf, size_t bsize) return ret_val; } -static int CYC2_ps_dump (Altera_desc * desc, void *buf, size_t bsize) +static int CYC2_ps_dump(Altera_desc *desc, const void *buf, size_t bsize) { /* Readback is only available through the Slave Parallel and */ /* boundary-scan interfaces. */ diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c index a669039..02a0796 100644 --- a/drivers/fpga/fpga.c +++ b/drivers/fpga/fpga.c @@ -52,7 +52,7 @@ static fpga_desc desc_table[CONFIG_MAX_FPGA_DEVICES]; /* Local static functions */ static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_get_desc( int devnum ); -static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_validate( int devnum, void *buf, +static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_validate(int devnum, const void *buf, size_t bsize, char *fn ); static int fpga_dev_info( int devnum ); @@ -94,7 +94,7 @@ static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_ge /* fpga_validate * generic parameter checking code */ -static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_validate( int devnum, void *buf, +static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_validate(int devnum, const void *buf, size_t bsize, char *fn ) { fpga_desc * desc = fpga_get_desc( devnum ); @@ -212,7 +212,7 @@ int fpga_add( fpga_type devtype, void *desc ) /* * Generic multiplexing code */ -int fpga_load( int devnum, void *buf, size_t bsize ) +int fpga_load(int devnum, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume failure */ fpga_desc * desc = fpga_validate( devnum, buf, bsize, (char *)__FUNCTION__ ); @@ -252,7 +252,7 @@ int fpga_load( int devnum, void *buf, size_t bsize ) /* fpga_dump * generic multiplexing code */ -int fpga_dump( int devnum, void *buf, size_t bsize ) +int fpga_dump(int devnum, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume failure */ fpga_desc * desc = fpga_validate( devnum, buf, bsize, (char *)__FUNCTION__ ); diff --git a/drivers/fpga/spartan2.c b/drivers/fpga/spartan2.c index cd16a9c..e72deee 100644 --- a/drivers/fpga/spartan2.c +++ b/drivers/fpga/spartan2.c @@ -48,17 +48,17 @@ #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ #endif -static int Spartan2_sp_load( Xilinx_desc *desc, void *buf, size_t bsize ); -static int Spartan2_sp_dump( Xilinx_desc *desc, void *buf, size_t bsize ); -/* static int Spartan2_sp_info( Xilinx_desc *desc ); */ +static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize); +static int Spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +/* static int Spartan2_sp_info(Xilinx_desc *desc ); */ -static int Spartan2_ss_load( Xilinx_desc *desc, void *buf, size_t bsize ); -static int Spartan2_ss_dump( Xilinx_desc *desc, void *buf, size_t bsize ); -/* static int Spartan2_ss_info( Xilinx_desc *desc ); */ +static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize); +static int Spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +/* static int Spartan2_ss_info(Xilinx_desc *desc ); */ /* ------------------------------------------------------------------------- */ /* Spartan-II Generic Implementation */ -int Spartan2_load (Xilinx_desc * desc, void *buf, size_t bsize) +int Spartan2_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -81,7 +81,7 @@ int Spartan2_load (Xilinx_desc * desc, void *buf, size_t bsize) return ret_val; } -int Spartan2_dump (Xilinx_desc * desc, void *buf, size_t bsize) +int Spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -113,7 +113,7 @@ int Spartan2_info( Xilinx_desc *desc ) /* ------------------------------------------------------------------------- */ /* Spartan-II Slave Parallel Generic Implementation */ -static int Spartan2_sp_load (Xilinx_desc * desc, void *buf, size_t bsize) +static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ Xilinx_Spartan2_Slave_Parallel_fns *fn = desc->iface_fns; @@ -265,7 +265,7 @@ static int Spartan2_sp_load (Xilinx_desc * desc, void *buf, size_t bsize) return ret_val; } -static int Spartan2_sp_dump (Xilinx_desc * desc, void *buf, size_t bsize) +static int Spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ Xilinx_Spartan2_Slave_Parallel_fns *fn = desc->iface_fns; @@ -313,7 +313,7 @@ static int Spartan2_sp_dump (Xilinx_desc * desc, void *buf, size_t bsize) /* ------------------------------------------------------------------------- */ -static int Spartan2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) +static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ Xilinx_Spartan2_Slave_Serial_fns *fn = desc->iface_fns; @@ -456,7 +456,7 @@ static int Spartan2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) return ret_val; } -static int Spartan2_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize) +static int Spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { /* Readback is only available through the Slave Parallel and */ /* boundary-scan interfaces. */ diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c index 1dd6f26..d2f8549 100644 --- a/drivers/fpga/spartan3.c +++ b/drivers/fpga/spartan3.c @@ -53,17 +53,17 @@ #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ #endif -static int Spartan3_sp_load( Xilinx_desc *desc, void *buf, size_t bsize ); -static int Spartan3_sp_dump( Xilinx_desc *desc, void *buf, size_t bsize ); -/* static int Spartan3_sp_info( Xilinx_desc *desc ); */ +static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize); +static int Spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +/* static int Spartan3_sp_info(Xilinx_desc *desc ); */ -static int Spartan3_ss_load( Xilinx_desc *desc, void *buf, size_t bsize ); -static int Spartan3_ss_dump( Xilinx_desc *desc, void *buf, size_t bsize ); -/* static int Spartan3_ss_info( Xilinx_desc *desc ); */ +static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize); +static int Spartan3_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +/* static int Spartan3_ss_info(Xilinx_desc *desc); */ /* ------------------------------------------------------------------------- */ /* Spartan-II Generic Implementation */ -int Spartan3_load (Xilinx_desc * desc, void *buf, size_t bsize) +int Spartan3_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -86,7 +86,7 @@ int Spartan3_load (Xilinx_desc * desc, void *buf, size_t bsize) return ret_val; } -int Spartan3_dump (Xilinx_desc * desc, void *buf, size_t bsize) +int Spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -118,7 +118,7 @@ int Spartan3_info( Xilinx_desc *desc ) /* ------------------------------------------------------------------------- */ /* Spartan-II Slave Parallel Generic Implementation */ -static int Spartan3_sp_load (Xilinx_desc * desc, void *buf, size_t bsize) +static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ Xilinx_Spartan3_Slave_Parallel_fns *fn = desc->iface_fns; @@ -272,7 +272,7 @@ static int Spartan3_sp_load (Xilinx_desc * desc, void *buf, size_t bsize) return ret_val; } -static int Spartan3_sp_dump (Xilinx_desc * desc, void *buf, size_t bsize) +static int Spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ Xilinx_Spartan3_Slave_Parallel_fns *fn = desc->iface_fns; @@ -320,7 +320,7 @@ static int Spartan3_sp_dump (Xilinx_desc * desc, void *buf, size_t bsize) /* ------------------------------------------------------------------------- */ -static int Spartan3_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) +static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ Xilinx_Spartan3_Slave_Serial_fns *fn = desc->iface_fns; @@ -475,7 +475,7 @@ static int Spartan3_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) return ret_val; } -static int Spartan3_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize) +static int Spartan3_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { /* Readback is only available through the Slave Parallel and */ /* boundary-scan interfaces. */ diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c index d1b4d15..9814d5e 100644 --- a/drivers/fpga/virtex2.c +++ b/drivers/fpga/virtex2.c @@ -101,13 +101,13 @@ #define CONFIG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ/5 /* 200 ms */ #endif -static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize); -static int Virtex2_ssm_dump (Xilinx_desc * desc, void *buf, size_t bsize); +static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize); +static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -static int Virtex2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize); -static int Virtex2_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize); +static int Virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize); +static int Virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -int Virtex2_load (Xilinx_desc * desc, void *buf, size_t bsize) +int Virtex2_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -129,7 +129,7 @@ int Virtex2_load (Xilinx_desc * desc, void *buf, size_t bsize) return ret_val; } -int Virtex2_dump (Xilinx_desc * desc, void *buf, size_t bsize) +int Virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -170,7 +170,7 @@ int Virtex2_info (Xilinx_desc * desc) * INIT_B and DONE lines. If both are high, configuration has * succeeded. Congratulations! */ -static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize) +static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc->iface_fns; @@ -369,7 +369,7 @@ static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize) /* * Read the FPGA configuration data */ -static int Virtex2_ssm_dump (Xilinx_desc * desc, void *buf, size_t bsize) +static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc->iface_fns; @@ -421,13 +421,13 @@ static int Virtex2_ssm_dump (Xilinx_desc * desc, void *buf, size_t bsize) return ret_val; } -static int Virtex2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) +static int Virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) { printf ("%s: Slave Serial Loading is unsupported\n", __FUNCTION__); return FPGA_FAIL; } -static int Virtex2_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize) +static int Virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { printf ("%s: Slave Serial Dumping is unsupported\n", __FUNCTION__); return FPGA_FAIL; diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c index 08dfdec..137916f 100644 --- a/drivers/fpga/xilinx.c +++ b/drivers/fpga/xilinx.c @@ -48,7 +48,7 @@ static int xilinx_validate (Xilinx_desc * desc, char *fn); /* ------------------------------------------------------------------------- */ -int xilinx_load (Xilinx_desc * desc, void *buf, size_t bsize) +int xilinx_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume a failure */ @@ -95,7 +95,7 @@ int xilinx_load (Xilinx_desc * desc, void *buf, size_t bsize) return ret_val; } -int xilinx_dump (Xilinx_desc * desc, void *buf, size_t bsize) +int xilinx_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume a failure */ diff --git a/include/ACEX1K.h b/include/ACEX1K.h index 2bb9226..e2e96d2 100644 --- a/include/ACEX1K.h +++ b/include/ACEX1K.h @@ -30,13 +30,13 @@ #include <altera.h> -extern int ACEX1K_load( Altera_desc *desc, void *image, size_t size ); -extern int ACEX1K_dump( Altera_desc *desc, void *buf, size_t bsize ); -extern int ACEX1K_info( Altera_desc *desc ); +extern int ACEX1K_load(Altera_desc *desc, const void *image, size_t size); +extern int ACEX1K_dump(Altera_desc *desc, const void *buf, size_t bsize); +extern int ACEX1K_info(Altera_desc *desc); -extern int CYC2_load( Altera_desc *desc, void *image, size_t size ); -extern int CYC2_dump( Altera_desc *desc, void *buf, size_t bsize ); -extern int CYC2_info( Altera_desc *desc ); +extern int CYC2_load(Altera_desc *desc, const void *image, size_t size); +extern int CYC2_dump(Altera_desc *desc, const void *buf, size_t bsize); +extern int CYC2_info(Altera_desc *desc); /* Slave Serial Implementation function table */ typedef struct { diff --git a/include/altera.h b/include/altera.h index f28a6a8..686148f 100644 --- a/include/altera.h +++ b/include/altera.h @@ -76,9 +76,9 @@ typedef struct { /* typedef Altera_desc */ /* Generic Altera Functions *********************************************************************/ -extern int altera_load( Altera_desc *desc, void *image, size_t size ); -extern int altera_dump( Altera_desc *desc, void *buf, size_t bsize ); -extern int altera_info( Altera_desc *desc ); +extern int altera_load(Altera_desc *desc, const void *image, size_t size); +extern int altera_dump(Altera_desc *desc, const void *buf, size_t bsize); +extern int altera_info(Altera_desc *desc); /* Board specific implementation specific function types *********************************************************************/ @@ -88,7 +88,7 @@ typedef int (*Altera_status_fn)( int cookie ); typedef int (*Altera_done_fn)( int cookie ); typedef int (*Altera_clk_fn)( int assert_clk, int flush, int cookie ); typedef int (*Altera_data_fn)( int assert_data, int flush, int cookie ); -typedef int (*Altera_write_fn)(void *buf, size_t len, int flush, int cookie); +typedef int(*Altera_write_fn)(const void *buf, size_t len, int flush, int cookie); typedef int (*Altera_abort_fn)( int cookie ); typedef int (*Altera_post_fn)( int cookie ); diff --git a/include/fpga.h b/include/fpga.h index ac24f2b..e0b1fe7 100644 --- a/include/fpga.h +++ b/include/fpga.h @@ -72,11 +72,11 @@ typedef struct { /* typedef fpga_desc */ /* root function definitions */ -extern void fpga_init( void ); -extern int fpga_add( fpga_type devtype, void *desc ); -extern int fpga_count( void ); -extern int fpga_load( int devnum, void *buf, size_t bsize ); -extern int fpga_dump( int devnum, void *buf, size_t bsize ); -extern int fpga_info( int devnum ); +extern void fpga_init(void); +extern int fpga_add(fpga_type devtype, void *desc); +extern int fpga_count(void); +extern int fpga_load(int devnum, const void *buf, size_t bsize); +extern int fpga_dump(int devnum, const void *buf, size_t bsize); +extern int fpga_info(int devnum); #endif /* _FPGA_H_ */ diff --git a/include/spartan2.h b/include/spartan2.h index 8959f90..e257a67 100644 --- a/include/spartan2.h +++ b/include/spartan2.h @@ -27,9 +27,9 @@ #include <xilinx.h> -extern int Spartan2_load( Xilinx_desc *desc, void *image, size_t size ); -extern int Spartan2_dump( Xilinx_desc *desc, void *buf, size_t bsize ); -extern int Spartan2_info( Xilinx_desc *desc ); +extern int Spartan2_load(Xilinx_desc *desc, const void *image, size_t size); +extern int Spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +extern int Spartan2_info(Xilinx_desc *desc); /* Slave Parallel Implementation function table */ typedef struct { diff --git a/include/spartan3.h b/include/spartan3.h index 0f0b400..67ede4b 100644 --- a/include/spartan3.h +++ b/include/spartan3.h @@ -27,9 +27,9 @@ #include <xilinx.h> -extern int Spartan3_load( Xilinx_desc *desc, void *image, size_t size ); -extern int Spartan3_dump( Xilinx_desc *desc, void *buf, size_t bsize ); -extern int Spartan3_info( Xilinx_desc *desc ); +extern int Spartan3_load(Xilinx_desc *desc, const void *image, size_t size); +extern int Spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +extern int Spartan3_info(Xilinx_desc *desc); /* Slave Parallel Implementation function table */ typedef struct { diff --git a/include/virtex2.h b/include/virtex2.h index 89d7d76..4717e0c 100644 --- a/include/virtex2.h +++ b/include/virtex2.h @@ -28,9 +28,9 @@ #include <xilinx.h> -extern int Virtex2_load( Xilinx_desc *desc, void *image, size_t size ); -extern int Virtex2_dump( Xilinx_desc *desc, void *buf, size_t bsize ); -extern int Virtex2_info( Xilinx_desc *desc ); +extern int Virtex2_load(Xilinx_desc *desc, const void *image, size_t size); +extern int Virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +extern int Virtex2_info(Xilinx_desc *desc); /* * Slave SelectMap Implementation function table. diff --git a/include/xilinx.h b/include/xilinx.h index 2cb2e5b..5f25b7a 100644 --- a/include/xilinx.h +++ b/include/xilinx.h @@ -81,9 +81,9 @@ typedef struct { /* typedef Xilinx_desc */ /* Generic Xilinx Functions *********************************************************************/ -extern int xilinx_load( Xilinx_desc *desc, void *image, size_t size ); -extern int xilinx_dump( Xilinx_desc *desc, void *buf, size_t bsize ); -extern int xilinx_info( Xilinx_desc *desc ); +extern int xilinx_load(Xilinx_desc *desc, const void *image, size_t size); +extern int xilinx_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +extern int xilinx_info(Xilinx_desc *desc); /* Board specific implementation specific function types *********************************************************************/
Fix compiler warning: cmd_fpga.c:318: warning: passing argument 3 of 'fit_image_get_data' from incompatible pointer type Adding the needed 'const' here entails a whole bunch of additonal changes all over the FPGA code. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Andre Schwarz <andre.schwarz@matrix-vision.de> Cc: Murray Jensen <Murray.Jensen@csiro.au> --- board/hymod/bsp.c | 4 ++-- board/matrix_vision/mergerbox/fpga.c | 2 +- board/matrix_vision/mergerbox/fpga.h | 2 +- board/matrix_vision/mvbc_p/fpga.c | 2 +- board/matrix_vision/mvbc_p/fpga.h | 2 +- board/matrix_vision/mvblm7/fpga.c | 2 +- board/matrix_vision/mvblm7/fpga.h | 2 +- common/cmd_fpga.c | 2 +- drivers/fpga/ACEX1K.c | 14 +++++++------- drivers/fpga/altera.c | 4 ++-- drivers/fpga/cyclon2.c | 12 ++++++------ drivers/fpga/fpga.c | 8 ++++---- drivers/fpga/spartan2.c | 24 ++++++++++++------------ drivers/fpga/spartan3.c | 24 ++++++++++++------------ drivers/fpga/virtex2.c | 20 ++++++++++---------- drivers/fpga/xilinx.c | 4 ++-- include/ACEX1K.h | 12 ++++++------ include/altera.h | 8 ++++---- include/fpga.h | 12 ++++++------ include/spartan2.h | 6 +++--- include/spartan3.h | 6 +++--- include/virtex2.h | 6 +++--- include/xilinx.h | 6 +++--- 23 files changed, 92 insertions(+), 92 deletions(-)