| Message ID | 20200730154545.3965-2-Sergey.Semin@baikalelectronics.ru |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | dmaengine: dw: Introduce non-mem peripherals optimizations | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success |
On Thu, 30 Jul 2020 18:45:41 +0300, Serge Semin wrote: > Each DW DMA controller channel can be synthesized with different > parameters like maximum burst-length, multi-block support, maximum data > width, etc. Most of these parameters determine the DW DMAC channels > performance in its own aspect. On the other hand these parameters can > be implicitly responsible for the channels performance degradation > (for instance multi-block support is a very useful feature, but having > it disabled during the DW DMAC synthesize will provide a more optimized > core). Since DMA slave devices may have critical dependency on the DMA > engine performance, let's provide a way for the slave devices to have > the DMA-channels allocated from a pool of the channels, which according > to the system engineer fulfill their performance requirements. > > The pool is determined by a mask optionally specified in the fifth > DMA-cell of the DMA DT-property. If the fifth cell is omitted from the > phandle arguments or the mask is zero, then the allocation will be > performed from a set of all channels provided by the DMA controller. > > Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> > --- > .../devicetree/bindings/dma/snps,dma-spear1340.yaml | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > Reviewed-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/dma/snps,dma-spear1340.yaml b/Documentation/devicetree/bindings/dma/snps,dma-spear1340.yaml index 20870f5c14dd..ef1d6879c158 100644 --- a/Documentation/devicetree/bindings/dma/snps,dma-spear1340.yaml +++ b/Documentation/devicetree/bindings/dma/snps,dma-spear1340.yaml @@ -18,12 +18,15 @@ properties: const: snps,dma-spear1340 "#dma-cells": - const: 3 + minimum: 3 + maximum: 4 description: | First cell is a phandle pointing to the DMA controller. Second one is the DMA request line number. Third cell is the memory master identifier for transfers on dynamically allocated channel. Fourth cell is the - peripheral master identifier for transfers on an allocated channel. + peripheral master identifier for transfers on an allocated channel. Fifth + cell is an optional mask of the DMA channels permitted to be allocated + for the corresponding client device. reg: maxItems: 1
Each DW DMA controller channel can be synthesized with different parameters like maximum burst-length, multi-block support, maximum data width, etc. Most of these parameters determine the DW DMAC channels performance in its own aspect. On the other hand these parameters can be implicitly responsible for the channels performance degradation (for instance multi-block support is a very useful feature, but having it disabled during the DW DMAC synthesize will provide a more optimized core). Since DMA slave devices may have critical dependency on the DMA engine performance, let's provide a way for the slave devices to have the DMA-channels allocated from a pool of the channels, which according to the system engineer fulfill their performance requirements. The pool is determined by a mask optionally specified in the fifth DMA-cell of the DMA DT-property. If the fifth cell is omitted from the phandle arguments or the mask is zero, then the allocation will be performed from a set of all channels provided by the DMA controller. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> --- .../devicetree/bindings/dma/snps,dma-spear1340.yaml | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)