| Message ID | 20200706143529.18306-3-geert+renesas@glider.be |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | ravb: Add support for explicit internal clock delay configuration | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/checkpatch | success |
Hello! On 06.07.2020 17:35, Geert Uytterhoeven wrote: > Some EtherAVB variants support internal clock delay configuration, which > can add larger delays than the delays that are typically supported by > the PHY (using an "rgmii-*id" PHY mode, and/or "[rt]xc-skew-ps" > properties). > > Add properties for configuring the internal MAC delays. > These properties are mandatory, even when specified as zero, to > distinguish between old and new DTBs. > > Update the (bogus) example accordingly. > > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> [...] MBR, Sergei
On 08.07.2020 13:03, Sergei Shtylyov wrote: >> Some EtherAVB variants support internal clock delay configuration, which >> can add larger delays than the delays that are typically supported by >> the PHY (using an "rgmii-*id" PHY mode, and/or "[rt]xc-skew-ps" >> properties). >> >> Add properties for configuring the internal MAC delays. >> These properties are mandatory, even when specified as zero, to >> distinguish between old and new DTBs. >> >> Update the (bogus) example accordingly. >> >> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> > > Reviewed-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Oops! Reviewed-by: Sergei Shtylyov <sergei.shtylyov@gmail.com> > [...] MBR, Sergei
On Mon, 06 Jul 2020 16:35:24 +0200, Geert Uytterhoeven wrote: > Some EtherAVB variants support internal clock delay configuration, which > can add larger delays than the delays that are typically supported by > the PHY (using an "rgmii-*id" PHY mode, and/or "[rt]xc-skew-ps" > properties). > > Add properties for configuring the internal MAC delays. > These properties are mandatory, even when specified as zero, to > distinguish between old and new DTBs. > > Update the (bogus) example accordingly. > > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> > --- > v2: > - Replace "renesas,[rt]xc-delay-ps" by "[rt]x-internal-delay-ps", > - Add "(bogus)" to the example update, to avoid people considering it > a one-to-one conversion. > --- > .../devicetree/bindings/net/renesas,ravb.txt | 29 ++++++++++--------- > 1 file changed, 16 insertions(+), 13 deletions(-) > Reviewed-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/net/renesas,ravb.txt b/Documentation/devicetree/bindings/net/renesas,ravb.txt index 032b76f14f4fdb38..4a62dd11d5c488f4 100644 --- a/Documentation/devicetree/bindings/net/renesas,ravb.txt +++ b/Documentation/devicetree/bindings/net/renesas,ravb.txt @@ -64,6 +64,18 @@ Optional properties: AVB_LINK signal. - renesas,ether-link-active-low: boolean, specify when the AVB_LINK signal is active-low instead of normal active-high. +- rx-internal-delay-ps: Internal RX clock delay. + This property is mandatory and valid only on R-Car Gen3 + and RZ/G2 SoCs. + Valid values are 0 and 1800. + A non-zero value is allowed only if phy-mode = "rgmii". + Zero is not supported on R-Car D3. +- tx-internal-delay-ps: Internal TX clock delay. + This property is mandatory and valid only on R-Car H3, + M3-W, M3-W+, M3-N, V3M, and V3H, and RZ/G2M and RZ/G2N. + Valid values are 0 and 2000. + A non-zero value is allowed only if phy-mode = "rgmii". + Zero is not supported on R-Car V3H. Example: @@ -105,8 +117,10 @@ Example: "ch24"; clocks = <&cpg CPG_MOD 812>; power-domains = <&cpg>; - phy-mode = "rgmii-id"; + phy-mode = "rgmii"; phy-handle = <&phy0>; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <2000>; pinctrl-0 = <ðer_pins>; pinctrl-names = "default"; @@ -115,18 +129,7 @@ Example: #size-cells = <0>; phy0: ethernet-phy@0 { - rxc-skew-ps = <900>; - rxdv-skew-ps = <0>; - rxd0-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd3-skew-ps = <0>; - txc-skew-ps = <900>; - txen-skew-ps = <0>; - txd0-skew-ps = <0>; - txd1-skew-ps = <0>; - txd2-skew-ps = <0>; - txd3-skew-ps = <0>; + rxc-skew-ps = <1500>; reg = <0>; interrupt-parent = <&gpio2>; interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
Some EtherAVB variants support internal clock delay configuration, which can add larger delays than the delays that are typically supported by the PHY (using an "rgmii-*id" PHY mode, and/or "[rt]xc-skew-ps" properties). Add properties for configuring the internal MAC delays. These properties are mandatory, even when specified as zero, to distinguish between old and new DTBs. Update the (bogus) example accordingly. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> --- v2: - Replace "renesas,[rt]xc-delay-ps" by "[rt]x-internal-delay-ps", - Add "(bogus)" to the example update, to avoid people considering it a one-to-one conversion. --- .../devicetree/bindings/net/renesas,ravb.txt | 29 ++++++++++--------- 1 file changed, 16 insertions(+), 13 deletions(-)