| Message ID | 1590737775-4798-5-git-send-email-masonccyang@mxic.com.tw |
|---|---|
| State | Changes Requested |
| Delegated to: | Ambarus Tudor |
| Headers | show |
| Series | mtd: spi-nor: add xSPI Octal DTR support | expand |
+ YC Lin in loop, -- > > Subject > > [PATCH v4 4/7] mtd: spi-nor: core: add configuration register 2 read & write support > > Configuration register 2 is to set the device operation condition like > STR or DTR mode at address offset 0 and DQS mode at address offset 0x200. > > Each device has various address offset for it's specific operatoin > setting. > > Signed-off-by: Mason Yang <masonccyang@mxic.com.tw> > --- CONFIDENTIALITY NOTE: This e-mail and any attachments may contain confidential information and/or personal data, which is protected by applicable laws. Please be reminded that duplication, disclosure, distribution, or use of this e-mail (and/or its attachments) or any part thereof is prohibited. If you receive this e-mail in error, please notify us immediately and delete this mail as well as its attachment(s) from your system. In addition, please be informed that collection, processing, and/or use of personal data is prohibited unless expressly permitted by personal data protection laws. Thank you for your attention and cooperation. Macronix International Co., Ltd. ===================================================================== ============================================================================ CONFIDENTIALITY NOTE: This e-mail and any attachments may contain confidential information and/or personal data, which is protected by applicable laws. Please be reminded that duplication, disclosure, distribution, or use of this e-mail (and/or its attachments) or any part thereof is prohibited. If you receive this e-mail in error, please notify us immediately and delete this mail as well as its attachment(s) from your system. In addition, please be informed that collection, processing, and/or use of personal data is prohibited unless expressly permitted by personal data protection laws. Thank you for your attention and cooperation. Macronix International Co., Ltd. =====================================================================
Hi, Mason, YC Lin, On 5/29/20 10:36 AM, Mason Yang wrote: > Configuration register 2 is to set the device operation condition like > STR or DTR mode at address offset 0 and DQS mode at address offset 0x200. > > Each device has various address offset for it's specific operatoin > setting. > > Signed-off-by: Mason Yang <masonccyang@mxic.com.tw> > --- > drivers/mtd/spi-nor/core.c | 78 ++++++++++++++++++++++++++++++++++++++++++++++ > drivers/mtd/spi-nor/core.h | 2 ++ > 2 files changed, 80 insertions(+) > > diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c > index 3799417..fed6236 100644 > --- a/drivers/mtd/spi-nor/core.c > +++ b/drivers/mtd/spi-nor/core.c > @@ -269,6 +269,84 @@ int spi_nor_write_disable(struct spi_nor *nor) > } > > /** > + * spi_nor_read_cr2() - Read the Configuration Register 2. > + * @nor: pointer to 'struct spi_nor'. > + * @addr: offset address to read. > + * @cr2: pointer to a DMA-able buffer where the value of the > + * Configuration Register 2 will be written. > + * > + * Return: 0 on success, -errno otherwise. > + */ > +int spi_nor_read_cr2(struct spi_nor *nor, u32 addr, u8 *cr2) spi_nor_read_volatile_reg() please do we need to pass len as an argument? s/cr2/buf why do we need addr for register interactions? > +{ > + int ret; > + u8 cmd = nor->params->rd_reg_cmd; you'll need to redefine to rd_vreg_cmd. > + > + if (nor->spimem) { > + struct spi_mem_op op = > + SPI_MEM_OP(SPI_MEM_OP_CMD(cmd, 1), > + SPI_MEM_OP_ADDR(4, addr, 1), nor->addr_width? > + SPI_MEM_OP_DUMMY(4, 1), nor->read_dummy? > + SPI_MEM_OP_DATA_IN(1, cr2, 1)); SPI_MEM_OP_DATA_IN(len, cr2, 0)? > + > + spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); > + > + ret = spi_mem_exec_op(nor->spimem, &op); > + } else { > + if (spi_nor_protocol_is_dtr(nor->reg_proto)) > + ret = -ENOTSUPP; > + else > + ret = nor->controller_ops->read_reg(nor, cmd, cr2, 1); > + } > + > + if (ret) > + dev_dbg(nor->dev, "error %d reading CR2\n", ret); > + > + return ret; > +} > + > +/** > + * spi_nor_write_cr2() - Write the Configuration Register 2. > + * @nor: pointer to 'struct spi_nor'. > + * @addr: offset address to write. > + * @cr2: pointer to a DMA-able buffer where the value of the > + * Configuratin Register 2 will be read. > + * > + * Return: 0 on success, -errno otherwise. > + */ > +int spi_nor_write_cr2(struct spi_nor *nor, u32 addr, u8 *cr2) spi_nor_write_volatile_reg() please Cheers, ta
diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 3799417..fed6236 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -269,6 +269,84 @@ int spi_nor_write_disable(struct spi_nor *nor) } /** + * spi_nor_read_cr2() - Read the Configuration Register 2. + * @nor: pointer to 'struct spi_nor'. + * @addr: offset address to read. + * @cr2: pointer to a DMA-able buffer where the value of the + * Configuration Register 2 will be written. + * + * Return: 0 on success, -errno otherwise. + */ +int spi_nor_read_cr2(struct spi_nor *nor, u32 addr, u8 *cr2) +{ + int ret; + u8 cmd = nor->params->rd_reg_cmd; + + if (nor->spimem) { + struct spi_mem_op op = + SPI_MEM_OP(SPI_MEM_OP_CMD(cmd, 1), + SPI_MEM_OP_ADDR(4, addr, 1), + SPI_MEM_OP_DUMMY(4, 1), + SPI_MEM_OP_DATA_IN(1, cr2, 1)); + + spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); + + ret = spi_mem_exec_op(nor->spimem, &op); + } else { + if (spi_nor_protocol_is_dtr(nor->reg_proto)) + ret = -ENOTSUPP; + else + ret = nor->controller_ops->read_reg(nor, cmd, cr2, 1); + } + + if (ret) + dev_dbg(nor->dev, "error %d reading CR2\n", ret); + + return ret; +} + +/** + * spi_nor_write_cr2() - Write the Configuration Register 2. + * @nor: pointer to 'struct spi_nor'. + * @addr: offset address to write. + * @cr2: pointer to a DMA-able buffer where the value of the + * Configuratin Register 2 will be read. + * + * Return: 0 on success, -errno otherwise. + */ +int spi_nor_write_cr2(struct spi_nor *nor, u32 addr, u8 *cr2) +{ + int ret; + u8 cmd = nor->params->wr_reg_cmd; + + ret = spi_nor_write_enable(nor); + if (ret) + return ret; + + if (nor->spimem) { + struct spi_mem_op op = + SPI_MEM_OP(SPI_MEM_OP_CMD(cmd, 1), + SPI_MEM_OP_ADDR(4, addr, 1), + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_DATA_OUT(1, cr2, 1)); + + spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); + + ret = spi_mem_exec_op(nor->spimem, &op); + } else { + if (spi_nor_protocol_is_dtr(nor->reg_proto)) + ret = -ENOTSUPP; + else + ret = nor->controller_ops->write_reg(nor, cmd, cr2, 1); + } + + if (ret) + dev_dbg(nor->dev, "error %d write CFG Reg 2\n", ret); + + return ret; +} + +/** * spi_nor_read_sr() - Read the Status Register. * @nor: pointer to 'struct spi_nor'. * @sr: pointer to a DMA-able buffer where the value of the diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 8de7f53..0eb07ca 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -434,6 +434,8 @@ struct spi_nor_manufacturer { int spi_nor_write_enable(struct spi_nor *nor); int spi_nor_write_disable(struct spi_nor *nor); +int spi_nor_read_cr2(struct spi_nor *nor, u32 addr, u8 *cr2); +int spi_nor_write_cr2(struct spi_nor *nor, u32 addr, u8 *cr2); int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable); int spi_nor_write_ear(struct spi_nor *nor, u8 ear); int spi_nor_wait_till_ready(struct spi_nor *nor);
Configuration register 2 is to set the device operation condition like STR or DTR mode at address offset 0 and DQS mode at address offset 0x200. Each device has various address offset for it's specific operatoin setting. Signed-off-by: Mason Yang <masonccyang@mxic.com.tw> --- drivers/mtd/spi-nor/core.c | 78 ++++++++++++++++++++++++++++++++++++++++++++++ drivers/mtd/spi-nor/core.h | 2 ++ 2 files changed, 80 insertions(+)