| Message ID | 1593087941-16872-2-git-send-email-sagar.kadam@sifive.com |
|---|---|
| State | Superseded |
| Delegated to: | Andes |
| Headers | show |
| Series | add DM based reset driver for SiFive SoC's | expand |
On Thu, Jun 25, 2020 at 5:56 PM Sagar Shrikant Kadam <sagar.kadam@sifive.com> wrote: > > Add bit indexes for reset signals within the PRCI module > on FU540-C000 SoC. > The DDR and ethernet sub-system's have reset signals > indicated by these reset indexes. > > Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> > Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com> > Reviewed-by: Bin Meng <bin.meng@windriver.com> > --- > include/dt-bindings/clock/sifive-fu540-prci.h | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/include/dt-bindings/clock/sifive-fu540-prci.h b/include/dt-bindings/clock/sifive-fu540-prci.h > index 6a0b70a..1c03b09 100644 > --- a/include/dt-bindings/clock/sifive-fu540-prci.h > +++ b/include/dt-bindings/clock/sifive-fu540-prci.h > @@ -15,4 +15,12 @@ > #define PRCI_CLK_GEMGXLPLL 2 > #define PRCI_CLK_TLCLK 3 > > +/* Reset bit indexes to be used by driver */ > +#define PRCI_RST_DDR_CTRL_N 0 > +#define PRCI_RST_DDR_AXI_N 1 > +#define PRCI_RST_DDR_AHB_N 2 > +#define PRCI_RST_DDR_PHY_N 3 > +/* bit 4 is reserved bit */ > +#define PRCI_RST_RSVD_N 4 > +#define PRCI_RST_GEMGXL_N 5 > #endif Do these bindings are synced from Linux? If Yes better to sync with a particular commit or tag rather than patch. Jagan.
Hi Jagan, > -----Original Message----- > From: Jagan Teki <jagan@amarulasolutions.com> > Sent: Thursday, June 25, 2020 11:13 PM > To: Sagar Kadam <sagar.kadam@sifive.com> > Cc: U-Boot-Denx <u-boot@lists.denx.de>; Rick Chen <rick@andestech.com>; > Paul Walmsley ( Sifive) <paul.walmsley@sifive.com>; Palmer Dabbelt > <palmer@dabbelt.com>; Anup Patel <anup.patel@wdc.com>; Atish Patra > <atish.patra@wdc.com>; Lukasz Majewski <lukma@denx.de>; Pragnesh > Patel <pragnesh.patel@sifive.com>; bin.meng@windriver.com; Simon Glass > <sjg@chromium.org>; Trevor Woerner <twoerner@gmail.com>; Eugeniy > Paltsev <Eugeniy.Paltsev@synopsys.com>; Patrick Wildt > <patrick@blueri.se>; Weijie Gao <weijie.gao@mediatek.com>; Fabio > Estevam <festevam@gmail.com> > Subject: Re: [PATCH v2 1/5] dt-bindings: prci: add indexes for reset signals > available in prci > > [External Email] Do not click links or attachments unless you recognize the > sender and know the content is safe > > On Thu, Jun 25, 2020 at 5:56 PM Sagar Shrikant Kadam > <sagar.kadam@sifive.com> wrote: > > > > Add bit indexes for reset signals within the PRCI module > > on FU540-C000 SoC. > > The DDR and ethernet sub-system's have reset signals > > indicated by these reset indexes. > > > > Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> > > Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com> > > Reviewed-by: Bin Meng <bin.meng@windriver.com> > > --- > > include/dt-bindings/clock/sifive-fu540-prci.h | 8 ++++++++ > > 1 file changed, 8 insertions(+) > > > > diff --git a/include/dt-bindings/clock/sifive-fu540-prci.h b/include/dt- > bindings/clock/sifive-fu540-prci.h > > index 6a0b70a..1c03b09 100644 > > --- a/include/dt-bindings/clock/sifive-fu540-prci.h > > +++ b/include/dt-bindings/clock/sifive-fu540-prci.h > > @@ -15,4 +15,12 @@ > > #define PRCI_CLK_GEMGXLPLL 2 > > #define PRCI_CLK_TLCLK 3 > > > > +/* Reset bit indexes to be used by driver */ > > +#define PRCI_RST_DDR_CTRL_N 0 > > +#define PRCI_RST_DDR_AXI_N 1 > > +#define PRCI_RST_DDR_AHB_N 2 > > +#define PRCI_RST_DDR_PHY_N 3 > > +/* bit 4 is reserved bit */ > > +#define PRCI_RST_RSVD_N 4 > > +#define PRCI_RST_GEMGXL_N 5 > > #endif > > Do these bindings are synced from Linux? If Yes better to sync with a > particular commit or tag rather than patch. > No, these reset bindings are not synced from Linux. Thanks & Regards, Sagar > Jagan.
On Fri, Jun 26, 2020 at 8:51 AM Sagar Kadam <sagar.kadam@sifive.com> wrote: > > Hi Jagan, > > > -----Original Message----- > > From: Jagan Teki <jagan@amarulasolutions.com> > > Sent: Thursday, June 25, 2020 11:13 PM > > To: Sagar Kadam <sagar.kadam@sifive.com> > > Cc: U-Boot-Denx <u-boot@lists.denx.de>; Rick Chen <rick@andestech.com>; > > Paul Walmsley ( Sifive) <paul.walmsley@sifive.com>; Palmer Dabbelt > > <palmer@dabbelt.com>; Anup Patel <anup.patel@wdc.com>; Atish Patra > > <atish.patra@wdc.com>; Lukasz Majewski <lukma@denx.de>; Pragnesh > > Patel <pragnesh.patel@sifive.com>; bin.meng@windriver.com; Simon Glass > > <sjg@chromium.org>; Trevor Woerner <twoerner@gmail.com>; Eugeniy > > Paltsev <Eugeniy.Paltsev@synopsys.com>; Patrick Wildt > > <patrick@blueri.se>; Weijie Gao <weijie.gao@mediatek.com>; Fabio > > Estevam <festevam@gmail.com> > > Subject: Re: [PATCH v2 1/5] dt-bindings: prci: add indexes for reset signals > > available in prci > > > > [External Email] Do not click links or attachments unless you recognize the > > sender and know the content is safe > > > > On Thu, Jun 25, 2020 at 5:56 PM Sagar Shrikant Kadam > > <sagar.kadam@sifive.com> wrote: > > > > > > Add bit indexes for reset signals within the PRCI module > > > on FU540-C000 SoC. > > > The DDR and ethernet sub-system's have reset signals > > > indicated by these reset indexes. > > > > > > Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> > > > Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com> > > > Reviewed-by: Bin Meng <bin.meng@windriver.com> > > > --- > > > include/dt-bindings/clock/sifive-fu540-prci.h | 8 ++++++++ > > > 1 file changed, 8 insertions(+) > > > > > > diff --git a/include/dt-bindings/clock/sifive-fu540-prci.h b/include/dt- > > bindings/clock/sifive-fu540-prci.h > > > index 6a0b70a..1c03b09 100644 > > > --- a/include/dt-bindings/clock/sifive-fu540-prci.h > > > +++ b/include/dt-bindings/clock/sifive-fu540-prci.h > > > @@ -15,4 +15,12 @@ > > > #define PRCI_CLK_GEMGXLPLL 2 > > > #define PRCI_CLK_TLCLK 3 > > > > > > +/* Reset bit indexes to be used by driver */ > > > +#define PRCI_RST_DDR_CTRL_N 0 > > > +#define PRCI_RST_DDR_AXI_N 1 > > > +#define PRCI_RST_DDR_AHB_N 2 > > > +#define PRCI_RST_DDR_PHY_N 3 > > > +/* bit 4 is reserved bit */ > > > +#define PRCI_RST_RSVD_N 4 > > > +#define PRCI_RST_GEMGXL_N 5 > > > #endif > > > > Do these bindings are synced from Linux? If Yes better to sync with a > > particular commit or tag rather than patch. > > > > No, these reset bindings are not synced from Linux. This is synced file from Linux, better to inline with Linux files always, if these bindings are not related to Linux then maintain it in a separate file or support it in Linux first if they do require for Linux. Jagan.
Hello Jagan, > -----Original Message----- > From: Jagan Teki <jagan@amarulasolutions.com> > Sent: Monday, June 29, 2020 9:00 PM > To: Sagar Kadam <sagar.kadam@sifive.com> > Cc: U-Boot-Denx <u-boot@lists.denx.de>; Rick Chen <rick@andestech.com>; > Paul Walmsley ( Sifive) <paul.walmsley@sifive.com>; Palmer Dabbelt > <palmer@dabbelt.com>; Anup Patel <anup.patel@wdc.com>; Atish Patra > <atish.patra@wdc.com>; Lukasz Majewski <lukma@denx.de>; Pragnesh > Patel <pragnesh.patel@sifive.com>; bin.meng@windriver.com; Simon Glass > <sjg@chromium.org>; Trevor Woerner <twoerner@gmail.com>; Eugeniy > Paltsev <Eugeniy.Paltsev@synopsys.com>; Patrick Wildt > <patrick@blueri.se>; Weijie Gao <weijie.gao@mediatek.com>; Fabio > Estevam <festevam@gmail.com> > Subject: Re: [PATCH v2 1/5] dt-bindings: prci: add indexes for reset signals > available in prci > > [External Email] Do not click links or attachments unless you recognize the > sender and know the content is safe > > On Fri, Jun 26, 2020 at 8:51 AM Sagar Kadam <sagar.kadam@sifive.com> > wrote: > > > > Hi Jagan, > > > > > -----Original Message----- > > > From: Jagan Teki <jagan@amarulasolutions.com> > > > Sent: Thursday, June 25, 2020 11:13 PM > > > To: Sagar Kadam <sagar.kadam@sifive.com> > > > Cc: U-Boot-Denx <u-boot@lists.denx.de>; Rick Chen > <rick@andestech.com>; > > > Paul Walmsley ( Sifive) <paul.walmsley@sifive.com>; Palmer Dabbelt > > > <palmer@dabbelt.com>; Anup Patel <anup.patel@wdc.com>; Atish > Patra > > > <atish.patra@wdc.com>; Lukasz Majewski <lukma@denx.de>; Pragnesh > > > Patel <pragnesh.patel@sifive.com>; bin.meng@windriver.com; Simon > Glass > > > <sjg@chromium.org>; Trevor Woerner <twoerner@gmail.com>; Eugeniy > > > Paltsev <Eugeniy.Paltsev@synopsys.com>; Patrick Wildt > > > <patrick@blueri.se>; Weijie Gao <weijie.gao@mediatek.com>; Fabio > > > Estevam <festevam@gmail.com> > > > Subject: Re: [PATCH v2 1/5] dt-bindings: prci: add indexes for reset > signals > > > available in prci > > > > > > [External Email] Do not click links or attachments unless you recognize > the > > > sender and know the content is safe > > > > > > On Thu, Jun 25, 2020 at 5:56 PM Sagar Shrikant Kadam > > > <sagar.kadam@sifive.com> wrote: > > > > > > > > Add bit indexes for reset signals within the PRCI module > > > > on FU540-C000 SoC. > > > > The DDR and ethernet sub-system's have reset signals > > > > indicated by these reset indexes. > > > > > > > > Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> > > > > Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com> > > > > Reviewed-by: Bin Meng <bin.meng@windriver.com> > > > > --- > > > > include/dt-bindings/clock/sifive-fu540-prci.h | 8 ++++++++ > > > > 1 file changed, 8 insertions(+) > > > > > > > > diff --git a/include/dt-bindings/clock/sifive-fu540-prci.h b/include/dt- > > > bindings/clock/sifive-fu540-prci.h > > > > index 6a0b70a..1c03b09 100644 > > > > --- a/include/dt-bindings/clock/sifive-fu540-prci.h > > > > +++ b/include/dt-bindings/clock/sifive-fu540-prci.h > > > > @@ -15,4 +15,12 @@ > > > > #define PRCI_CLK_GEMGXLPLL 2 > > > > #define PRCI_CLK_TLCLK 3 > > > > > > > > +/* Reset bit indexes to be used by driver */ > > > > +#define PRCI_RST_DDR_CTRL_N 0 > > > > +#define PRCI_RST_DDR_AXI_N 1 > > > > +#define PRCI_RST_DDR_AHB_N 2 > > > > +#define PRCI_RST_DDR_PHY_N 3 > > > > +/* bit 4 is reserved bit */ > > > > +#define PRCI_RST_RSVD_N 4 > > > > +#define PRCI_RST_GEMGXL_N 5 > > > > #endif > > > > > > Do these bindings are synced from Linux? If Yes better to sync with a > > > particular commit or tag rather than patch. > > > > > > > No, these reset bindings are not synced from Linux. > > This is synced file from Linux, better to inline with Linux files > always, if these bindings are not related to Linux then maintain it in > a separate file or support it in Linux first if they do require for > Linux. > Ohh. Sorry I thought you were asking if reset-bindings are from Linux. Yes this file is synced from Linux but these reset-bindings are not related to Linux. So I can split it and place reset bindings into another file: "include/dt-bindings/reset/sifive-fu540-reset.h" and include it wherever required. Please let me know if this sounds okay. Thanks & BR, Sagar Kadam > Jagan.
> -----Original Message----- > From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Sagar Kadam > Sent: Monday, June 29, 2020 9:37 PM > To: Jagan Teki <jagan@amarulasolutions.com> > Cc: U-Boot-Denx <u-boot@lists.denx.de>; Rick Chen <rick@andestech.com>; > Paul Walmsley ( Sifive) <paul.walmsley@sifive.com>; Palmer Dabbelt > <palmer@dabbelt.com>; Anup Patel <anup.patel@wdc.com>; Atish Patra > <atish.patra@wdc.com>; Lukasz Majewski <lukma@denx.de>; Pragnesh > Patel <pragnesh.patel@sifive.com>; bin.meng@windriver.com; Simon Glass > <sjg@chromium.org>; Trevor Woerner <twoerner@gmail.com>; Eugeniy > Paltsev <Eugeniy.Paltsev@synopsys.com>; Patrick Wildt > <patrick@blueri.se>; Weijie Gao <weijie.gao@mediatek.com>; Fabio > Estevam <festevam@gmail.com> > Subject: RE: [PATCH v2 1/5] dt-bindings: prci: add indexes for reset signals > available in prci > > Hello Jagan, > > -----Original Message----- > > From: Jagan Teki <jagan@amarulasolutions.com> > > Sent: Monday, June 29, 2020 9:00 PM > > To: Sagar Kadam <sagar.kadam@sifive.com> > > Cc: U-Boot-Denx <u-boot@lists.denx.de>; Rick Chen > > <rick@andestech.com>; Paul Walmsley ( Sifive) > > <paul.walmsley@sifive.com>; Palmer Dabbelt <palmer@dabbelt.com>; > Anup > > Patel <anup.patel@wdc.com>; Atish Patra <atish.patra@wdc.com>; Lukasz > > Majewski <lukma@denx.de>; Pragnesh Patel > <pragnesh.patel@sifive.com>; > > bin.meng@windriver.com; Simon Glass <sjg@chromium.org>; Trevor > Woerner > > <twoerner@gmail.com>; Eugeniy Paltsev > <Eugeniy.Paltsev@synopsys.com>; > > Patrick Wildt <patrick@blueri.se>; Weijie Gao > > <weijie.gao@mediatek.com>; Fabio Estevam <festevam@gmail.com> > > Subject: Re: [PATCH v2 1/5] dt-bindings: prci: add indexes for reset > > signals available in prci > > > > [External Email] Do not click links or attachments unless you > > recognize the sender and know the content is safe > > > > On Fri, Jun 26, 2020 at 8:51 AM Sagar Kadam <sagar.kadam@sifive.com> > > wrote: > > > > > > Hi Jagan, > > > > > > > -----Original Message----- > > > > From: Jagan Teki <jagan@amarulasolutions.com> > > > > Sent: Thursday, June 25, 2020 11:13 PM > > > > To: Sagar Kadam <sagar.kadam@sifive.com> > > > > Cc: U-Boot-Denx <u-boot@lists.denx.de>; Rick Chen > > <rick@andestech.com>; > > > > Paul Walmsley ( Sifive) <paul.walmsley@sifive.com>; Palmer Dabbelt > > > > <palmer@dabbelt.com>; Anup Patel <anup.patel@wdc.com>; Atish > > Patra > > > > <atish.patra@wdc.com>; Lukasz Majewski <lukma@denx.de>; > Pragnesh > > > > Patel <pragnesh.patel@sifive.com>; bin.meng@windriver.com; Simon > > Glass > > > > <sjg@chromium.org>; Trevor Woerner <twoerner@gmail.com>; > Eugeniy > > > > Paltsev <Eugeniy.Paltsev@synopsys.com>; Patrick Wildt > > > > <patrick@blueri.se>; Weijie Gao <weijie.gao@mediatek.com>; Fabio > > > > Estevam <festevam@gmail.com> > > > > Subject: Re: [PATCH v2 1/5] dt-bindings: prci: add indexes for > > > > reset > > signals > > > > available in prci > > > > > > > > [External Email] Do not click links or attachments unless you > > > > recognize > > the > > > > sender and know the content is safe > > > > > > > > On Thu, Jun 25, 2020 at 5:56 PM Sagar Shrikant Kadam > > > > <sagar.kadam@sifive.com> wrote: > > > > > > > > > > Add bit indexes for reset signals within the PRCI module on > > > > > FU540-C000 SoC. > > > > > The DDR and ethernet sub-system's have reset signals indicated > > > > > by these reset indexes. > > > > > > > > > > Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> > > > > > Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com> > > > > > Reviewed-by: Bin Meng <bin.meng@windriver.com> > > > > > --- > > > > > include/dt-bindings/clock/sifive-fu540-prci.h | 8 ++++++++ > > > > > 1 file changed, 8 insertions(+) > > > > > > > > > > diff --git a/include/dt-bindings/clock/sifive-fu540-prci.h > > > > > b/include/dt- > > > > bindings/clock/sifive-fu540-prci.h > > > > > index 6a0b70a..1c03b09 100644 > > > > > --- a/include/dt-bindings/clock/sifive-fu540-prci.h > > > > > +++ b/include/dt-bindings/clock/sifive-fu540-prci.h > > > > > @@ -15,4 +15,12 @@ > > > > > #define PRCI_CLK_GEMGXLPLL 2 > > > > > #define PRCI_CLK_TLCLK 3 > > > > > > > > > > +/* Reset bit indexes to be used by driver */ > > > > > +#define PRCI_RST_DDR_CTRL_N 0 > > > > > +#define PRCI_RST_DDR_AXI_N 1 > > > > > +#define PRCI_RST_DDR_AHB_N 2 > > > > > +#define PRCI_RST_DDR_PHY_N 3 > > > > > +/* bit 4 is reserved bit */ > > > > > +#define PRCI_RST_RSVD_N 4 > > > > > +#define PRCI_RST_GEMGXL_N 5 > > > > > #endif > > > > > > > > Do these bindings are synced from Linux? If Yes better to sync > > > > with a particular commit or tag rather than patch. > > > > > > > > > > No, these reset bindings are not synced from Linux. > > > > This is synced file from Linux, better to inline with Linux files > > always, if these bindings are not related to Linux then maintain it in > > a separate file or support it in Linux first if they do require for > > Linux. > > > Ohh. Sorry I thought you were asking if reset-bindings are from Linux. > Yes this file is synced from Linux but these reset-bindings are not related to > Linux. So I can split it and place reset bindings into another file: > "include/dt-bindings/reset/sifive-fu540-reset.h" It will be "include/dt-bindings/reset/sifive-fu540-prci.h" BR, Sagar > and include it wherever required. Please let me know if this sounds okay. > > Thanks & BR, > Sagar Kadam > > > Jagan.
On Fri, Jul 3, 2020 at 11:52 AM Sagar Kadam <sagar.kadam@sifive.com> wrote: > > > > -----Original Message----- > > From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Sagar Kadam > > Sent: Monday, June 29, 2020 9:37 PM > > To: Jagan Teki <jagan@amarulasolutions.com> > > Cc: U-Boot-Denx <u-boot@lists.denx.de>; Rick Chen <rick@andestech.com>; > > Paul Walmsley ( Sifive) <paul.walmsley@sifive.com>; Palmer Dabbelt > > <palmer@dabbelt.com>; Anup Patel <anup.patel@wdc.com>; Atish Patra > > <atish.patra@wdc.com>; Lukasz Majewski <lukma@denx.de>; Pragnesh > > Patel <pragnesh.patel@sifive.com>; bin.meng@windriver.com; Simon Glass > > <sjg@chromium.org>; Trevor Woerner <twoerner@gmail.com>; Eugeniy > > Paltsev <Eugeniy.Paltsev@synopsys.com>; Patrick Wildt > > <patrick@blueri.se>; Weijie Gao <weijie.gao@mediatek.com>; Fabio > > Estevam <festevam@gmail.com> > > Subject: RE: [PATCH v2 1/5] dt-bindings: prci: add indexes for reset signals > > available in prci > > > > Hello Jagan, > > > -----Original Message----- > > > From: Jagan Teki <jagan@amarulasolutions.com> > > > Sent: Monday, June 29, 2020 9:00 PM > > > To: Sagar Kadam <sagar.kadam@sifive.com> > > > Cc: U-Boot-Denx <u-boot@lists.denx.de>; Rick Chen > > > <rick@andestech.com>; Paul Walmsley ( Sifive) > > > <paul.walmsley@sifive.com>; Palmer Dabbelt <palmer@dabbelt.com>; > > Anup > > > Patel <anup.patel@wdc.com>; Atish Patra <atish.patra@wdc.com>; Lukasz > > > Majewski <lukma@denx.de>; Pragnesh Patel > > <pragnesh.patel@sifive.com>; > > > bin.meng@windriver.com; Simon Glass <sjg@chromium.org>; Trevor > > Woerner > > > <twoerner@gmail.com>; Eugeniy Paltsev > > <Eugeniy.Paltsev@synopsys.com>; > > > Patrick Wildt <patrick@blueri.se>; Weijie Gao > > > <weijie.gao@mediatek.com>; Fabio Estevam <festevam@gmail.com> > > > Subject: Re: [PATCH v2 1/5] dt-bindings: prci: add indexes for reset > > > signals available in prci > > > > > > [External Email] Do not click links or attachments unless you > > > recognize the sender and know the content is safe > > > > > > On Fri, Jun 26, 2020 at 8:51 AM Sagar Kadam <sagar.kadam@sifive.com> > > > wrote: > > > > > > > > Hi Jagan, > > > > > > > > > -----Original Message----- > > > > > From: Jagan Teki <jagan@amarulasolutions.com> > > > > > Sent: Thursday, June 25, 2020 11:13 PM > > > > > To: Sagar Kadam <sagar.kadam@sifive.com> > > > > > Cc: U-Boot-Denx <u-boot@lists.denx.de>; Rick Chen > > > <rick@andestech.com>; > > > > > Paul Walmsley ( Sifive) <paul.walmsley@sifive.com>; Palmer Dabbelt > > > > > <palmer@dabbelt.com>; Anup Patel <anup.patel@wdc.com>; Atish > > > Patra > > > > > <atish.patra@wdc.com>; Lukasz Majewski <lukma@denx.de>; > > Pragnesh > > > > > Patel <pragnesh.patel@sifive.com>; bin.meng@windriver.com; Simon > > > Glass > > > > > <sjg@chromium.org>; Trevor Woerner <twoerner@gmail.com>; > > Eugeniy > > > > > Paltsev <Eugeniy.Paltsev@synopsys.com>; Patrick Wildt > > > > > <patrick@blueri.se>; Weijie Gao <weijie.gao@mediatek.com>; Fabio > > > > > Estevam <festevam@gmail.com> > > > > > Subject: Re: [PATCH v2 1/5] dt-bindings: prci: add indexes for > > > > > reset > > > signals > > > > > available in prci > > > > > > > > > > [External Email] Do not click links or attachments unless you > > > > > recognize > > > the > > > > > sender and know the content is safe > > > > > > > > > > On Thu, Jun 25, 2020 at 5:56 PM Sagar Shrikant Kadam > > > > > <sagar.kadam@sifive.com> wrote: > > > > > > > > > > > > Add bit indexes for reset signals within the PRCI module on > > > > > > FU540-C000 SoC. > > > > > > The DDR and ethernet sub-system's have reset signals indicated > > > > > > by these reset indexes. > > > > > > > > > > > > Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> > > > > > > Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com> > > > > > > Reviewed-by: Bin Meng <bin.meng@windriver.com> > > > > > > --- > > > > > > include/dt-bindings/clock/sifive-fu540-prci.h | 8 ++++++++ > > > > > > 1 file changed, 8 insertions(+) > > > > > > > > > > > > diff --git a/include/dt-bindings/clock/sifive-fu540-prci.h > > > > > > b/include/dt- > > > > > bindings/clock/sifive-fu540-prci.h > > > > > > index 6a0b70a..1c03b09 100644 > > > > > > --- a/include/dt-bindings/clock/sifive-fu540-prci.h > > > > > > +++ b/include/dt-bindings/clock/sifive-fu540-prci.h > > > > > > @@ -15,4 +15,12 @@ > > > > > > #define PRCI_CLK_GEMGXLPLL 2 > > > > > > #define PRCI_CLK_TLCLK 3 > > > > > > > > > > > > +/* Reset bit indexes to be used by driver */ > > > > > > +#define PRCI_RST_DDR_CTRL_N 0 > > > > > > +#define PRCI_RST_DDR_AXI_N 1 > > > > > > +#define PRCI_RST_DDR_AHB_N 2 > > > > > > +#define PRCI_RST_DDR_PHY_N 3 > > > > > > +/* bit 4 is reserved bit */ > > > > > > +#define PRCI_RST_RSVD_N 4 > > > > > > +#define PRCI_RST_GEMGXL_N 5 > > > > > > #endif > > > > > > > > > > Do these bindings are synced from Linux? If Yes better to sync > > > > > with a particular commit or tag rather than patch. > > > > > > > > > > > > > No, these reset bindings are not synced from Linux. > > > > > > This is synced file from Linux, better to inline with Linux files > > > always, if these bindings are not related to Linux then maintain it in > > > a separate file or support it in Linux first if they do require for > > > Linux. > > > > > Ohh. Sorry I thought you were asking if reset-bindings are from Linux. > > Yes this file is synced from Linux but these reset-bindings are not related to > > Linux. So I can split it and place reset bindings into another file: > > "include/dt-bindings/reset/sifive-fu540-reset.h" > > It will be "include/dt-bindings/reset/sifive-fu540-prci.h" What if it would be the same directory structure and file name with -u-boot.h extension. This way we can identify these are u-boot related defines. Jagan.
Hi Jagan, > -----Original Message----- > From: Jagan Teki <jagan@amarulasolutions.com> > Sent: Friday, July 3, 2020 12:04 PM > To: Sagar Kadam <sagar.kadam@sifive.com> > Cc: U-Boot-Denx <u-boot@lists.denx.de>; Rick Chen <rick@andestech.com>; > Paul Walmsley ( Sifive) <paul.walmsley@sifive.com>; Palmer Dabbelt > <palmer@dabbelt.com>; Anup Patel <anup.patel@wdc.com>; Atish Patra > <atish.patra@wdc.com>; Lukasz Majewski <lukma@denx.de>; Pragnesh > Patel <pragnesh.patel@sifive.com>; bin.meng@windriver.com; Simon Glass > <sjg@chromium.org>; Trevor Woerner <twoerner@gmail.com>; Eugeniy > Paltsev <Eugeniy.Paltsev@synopsys.com>; Patrick Wildt > <patrick@blueri.se>; Weijie Gao <weijie.gao@mediatek.com>; Fabio > Estevam <festevam@gmail.com> > Subject: Re: [PATCH v2 1/5] dt-bindings: prci: add indexes for reset signals > available in prci > > [External Email] Do not click links or attachments unless you recognize the > sender and know the content is safe > > On Fri, Jul 3, 2020 at 11:52 AM Sagar Kadam <sagar.kadam@sifive.com> > wrote: > > > > > > > -----Original Message----- > > > From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Sagar > Kadam > > > Sent: Monday, June 29, 2020 9:37 PM > > > To: Jagan Teki <jagan@amarulasolutions.com> > > > Cc: U-Boot-Denx <u-boot@lists.denx.de>; Rick Chen > > > <rick@andestech.com>; Paul Walmsley ( Sifive) > > > <paul.walmsley@sifive.com>; Palmer Dabbelt <palmer@dabbelt.com>; > > > Anup Patel <anup.patel@wdc.com>; Atish Patra > <atish.patra@wdc.com>; > > > Lukasz Majewski <lukma@denx.de>; Pragnesh Patel > > > <pragnesh.patel@sifive.com>; bin.meng@windriver.com; Simon Glass > > > <sjg@chromium.org>; Trevor Woerner <twoerner@gmail.com>; Eugeniy > > > Paltsev <Eugeniy.Paltsev@synopsys.com>; Patrick Wildt > > > <patrick@blueri.se>; Weijie Gao <weijie.gao@mediatek.com>; Fabio > > > Estevam <festevam@gmail.com> > > > Subject: RE: [PATCH v2 1/5] dt-bindings: prci: add indexes for reset > > > signals available in prci > > > > > > Hello Jagan, > > > > -----Original Message----- > > > > From: Jagan Teki <jagan@amarulasolutions.com> > > > > Sent: Monday, June 29, 2020 9:00 PM > > > > To: Sagar Kadam <sagar.kadam@sifive.com> > > > > Cc: U-Boot-Denx <u-boot@lists.denx.de>; Rick Chen > > > > <rick@andestech.com>; Paul Walmsley ( Sifive) > > > > <paul.walmsley@sifive.com>; Palmer Dabbelt <palmer@dabbelt.com>; > > > Anup > > > > Patel <anup.patel@wdc.com>; Atish Patra <atish.patra@wdc.com>; > > > > Lukasz Majewski <lukma@denx.de>; Pragnesh Patel > > > <pragnesh.patel@sifive.com>; > > > > bin.meng@windriver.com; Simon Glass <sjg@chromium.org>; Trevor > > > Woerner > > > > <twoerner@gmail.com>; Eugeniy Paltsev > > > <Eugeniy.Paltsev@synopsys.com>; > > > > Patrick Wildt <patrick@blueri.se>; Weijie Gao > > > > <weijie.gao@mediatek.com>; Fabio Estevam <festevam@gmail.com> > > > > Subject: Re: [PATCH v2 1/5] dt-bindings: prci: add indexes for > > > > reset signals available in prci > > > > > > > > [External Email] Do not click links or attachments unless you > > > > recognize the sender and know the content is safe > > > > > > > > On Fri, Jun 26, 2020 at 8:51 AM Sagar Kadam > > > > <sagar.kadam@sifive.com> > > > > wrote: > > > > > > > > > > Hi Jagan, > > > > > > > > > > > -----Original Message----- > > > > > > From: Jagan Teki <jagan@amarulasolutions.com> > > > > > > Sent: Thursday, June 25, 2020 11:13 PM > > > > > > To: Sagar Kadam <sagar.kadam@sifive.com> > > > > > > Cc: U-Boot-Denx <u-boot@lists.denx.de>; Rick Chen > > > > <rick@andestech.com>; > > > > > > Paul Walmsley ( Sifive) <paul.walmsley@sifive.com>; Palmer > > > > > > Dabbelt <palmer@dabbelt.com>; Anup Patel > <anup.patel@wdc.com>; > > > > > > Atish > > > > Patra > > > > > > <atish.patra@wdc.com>; Lukasz Majewski <lukma@denx.de>; > > > Pragnesh > > > > > > Patel <pragnesh.patel@sifive.com>; bin.meng@windriver.com; > > > > > > Simon > > > > Glass > > > > > > <sjg@chromium.org>; Trevor Woerner <twoerner@gmail.com>; > > > Eugeniy > > > > > > Paltsev <Eugeniy.Paltsev@synopsys.com>; Patrick Wildt > > > > > > <patrick@blueri.se>; Weijie Gao <weijie.gao@mediatek.com>; > > > > > > Fabio Estevam <festevam@gmail.com> > > > > > > Subject: Re: [PATCH v2 1/5] dt-bindings: prci: add indexes for > > > > > > reset > > > > signals > > > > > > available in prci > > > > > > > > > > > > [External Email] Do not click links or attachments unless you > > > > > > recognize > > > > the > > > > > > sender and know the content is safe > > > > > > > > > > > > On Thu, Jun 25, 2020 at 5:56 PM Sagar Shrikant Kadam > > > > > > <sagar.kadam@sifive.com> wrote: > > > > > > > > > > > > > > Add bit indexes for reset signals within the PRCI module on > > > > > > > FU540-C000 SoC. > > > > > > > The DDR and ethernet sub-system's have reset signals > > > > > > > indicated by these reset indexes. > > > > > > > > > > > > > > Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> > > > > > > > Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com> > > > > > > > Reviewed-by: Bin Meng <bin.meng@windriver.com> > > > > > > > --- > > > > > > > include/dt-bindings/clock/sifive-fu540-prci.h | 8 ++++++++ > > > > > > > 1 file changed, 8 insertions(+) > > > > > > > > > > > > > > diff --git a/include/dt-bindings/clock/sifive-fu540-prci.h > > > > > > > b/include/dt- > > > > > > bindings/clock/sifive-fu540-prci.h > > > > > > > index 6a0b70a..1c03b09 100644 > > > > > > > --- a/include/dt-bindings/clock/sifive-fu540-prci.h > > > > > > > +++ b/include/dt-bindings/clock/sifive-fu540-prci.h > > > > > > > @@ -15,4 +15,12 @@ > > > > > > > #define PRCI_CLK_GEMGXLPLL 2 > > > > > > > #define PRCI_CLK_TLCLK 3 > > > > > > > > > > > > > > +/* Reset bit indexes to be used by driver */ > > > > > > > +#define PRCI_RST_DDR_CTRL_N 0 > > > > > > > +#define PRCI_RST_DDR_AXI_N 1 > > > > > > > +#define PRCI_RST_DDR_AHB_N 2 > > > > > > > +#define PRCI_RST_DDR_PHY_N 3 > > > > > > > +/* bit 4 is reserved bit */ > > > > > > > +#define PRCI_RST_RSVD_N 4 > > > > > > > +#define PRCI_RST_GEMGXL_N 5 > > > > > > > #endif > > > > > > > > > > > > Do these bindings are synced from Linux? If Yes better to sync > > > > > > with a particular commit or tag rather than patch. > > > > > > > > > > > > > > > > No, these reset bindings are not synced from Linux. > > > > > > > > This is synced file from Linux, better to inline with Linux files > > > > always, if these bindings are not related to Linux then maintain > > > > it in a separate file or support it in Linux first if they do > > > > require for Linux. > > > > > > > Ohh. Sorry I thought you were asking if reset-bindings are from Linux. > > > Yes this file is synced from Linux but these reset-bindings are not > > > related to Linux. So I can split it and place reset bindings into another > file: > > > "include/dt-bindings/reset/sifive-fu540-reset.h" > > > > It will be "include/dt-bindings/reset/sifive-fu540-prci.h" > > What if it would be the same directory structure and file name with -u- > boot.h extension. This way we can identify these are u-boot related > defines. > > Jagan. That's a good suggestion. Having an -u-boot.h extension will make the point that it is needed only for u-boot. Please correct me if I am wrong here, but I do see few references of similar clock / reset module's ( eg: sun5i-ccu.h or tegra124-car.h etc.) sharing header names in 1. Clock bindings in include/dt-bindings/clock/ 2. reset bindings in include/dt-bindings/reset/ These headers provide respective clock and reset indexes. So I was thinking similarly for prci to have clock indexes in dt-bindings/clock and reset indexes in dt-bindings/reset. Thanks & BR, Sagar
Hi Jagan, A gentle reminder here. > -----Original Message----- > From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Sagar Kadam > Sent: Friday, July 3, 2020 12:25 PM > To: Jagan Teki <jagan@amarulasolutions.com> > Cc: U-Boot-Denx <u-boot@lists.denx.de>; Rick Chen <rick@andestech.com>; > Paul Walmsley ( Sifive) <paul.walmsley@sifive.com>; Palmer Dabbelt > <palmer@dabbelt.com>; Anup Patel <anup.patel@wdc.com>; Atish Patra > <atish.patra@wdc.com>; Lukasz Majewski <lukma@denx.de>; Pragnesh > Patel <pragnesh.patel@sifive.com>; bin.meng@windriver.com; Simon Glass > <sjg@chromium.org>; Trevor Woerner <twoerner@gmail.com>; Eugeniy > Paltsev <Eugeniy.Paltsev@synopsys.com>; Patrick Wildt > <patrick@blueri.se>; Weijie Gao <weijie.gao@mediatek.com>; Fabio > Estevam <festevam@gmail.com> > Subject: RE: [PATCH v2 1/5] dt-bindings: prci: add indexes for reset signals > available in prci > > Hi Jagan, > > > -----Original Message----- > > From: Jagan Teki <jagan@amarulasolutions.com> > > Sent: Friday, July 3, 2020 12:04 PM > > To: Sagar Kadam <sagar.kadam@sifive.com> > > Cc: U-Boot-Denx <u-boot@lists.denx.de>; Rick Chen > <rick@andestech.com>; > > Paul Walmsley ( Sifive) <paul.walmsley@sifive.com>; Palmer Dabbelt > > <palmer@dabbelt.com>; Anup Patel <anup.patel@wdc.com>; Atish Patra > > <atish.patra@wdc.com>; Lukasz Majewski <lukma@denx.de>; Pragnesh > > Patel <pragnesh.patel@sifive.com>; bin.meng@windriver.com; Simon > Glass > > <sjg@chromium.org>; Trevor Woerner <twoerner@gmail.com>; Eugeniy > > Paltsev <Eugeniy.Paltsev@synopsys.com>; Patrick Wildt > > <patrick@blueri.se>; Weijie Gao <weijie.gao@mediatek.com>; Fabio > > Estevam <festevam@gmail.com> > > Subject: Re: [PATCH v2 1/5] dt-bindings: prci: add indexes for reset signals > > available in prci > > > > [External Email] Do not click links or attachments unless you recognize the > > sender and know the content is safe > > > > On Fri, Jul 3, 2020 at 11:52 AM Sagar Kadam <sagar.kadam@sifive.com> > > wrote: > > > > > > > > > > -----Original Message----- > > > > From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Sagar > > Kadam > > > > Sent: Monday, June 29, 2020 9:37 PM > > > > To: Jagan Teki <jagan@amarulasolutions.com> > > > > Cc: U-Boot-Denx <u-boot@lists.denx.de>; Rick Chen > > > > <rick@andestech.com>; Paul Walmsley ( Sifive) > > > > <paul.walmsley@sifive.com>; Palmer Dabbelt <palmer@dabbelt.com>; > > > > Anup Patel <anup.patel@wdc.com>; Atish Patra > > <atish.patra@wdc.com>; > > > > Lukasz Majewski <lukma@denx.de>; Pragnesh Patel > > > > <pragnesh.patel@sifive.com>; bin.meng@windriver.com; Simon Glass > > > > <sjg@chromium.org>; Trevor Woerner <twoerner@gmail.com>; > Eugeniy > > > > Paltsev <Eugeniy.Paltsev@synopsys.com>; Patrick Wildt > > > > <patrick@blueri.se>; Weijie Gao <weijie.gao@mediatek.com>; Fabio > > > > Estevam <festevam@gmail.com> > > > > Subject: RE: [PATCH v2 1/5] dt-bindings: prci: add indexes for reset > > > > signals available in prci > > > > > > > > Hello Jagan, > > > > > -----Original Message----- > > > > > From: Jagan Teki <jagan@amarulasolutions.com> > > > > > Sent: Monday, June 29, 2020 9:00 PM > > > > > To: Sagar Kadam <sagar.kadam@sifive.com> > > > > > Cc: U-Boot-Denx <u-boot@lists.denx.de>; Rick Chen > > > > > <rick@andestech.com>; Paul Walmsley ( Sifive) > > > > > <paul.walmsley@sifive.com>; Palmer Dabbelt > <palmer@dabbelt.com>; > > > > Anup > > > > > Patel <anup.patel@wdc.com>; Atish Patra <atish.patra@wdc.com>; > > > > > Lukasz Majewski <lukma@denx.de>; Pragnesh Patel > > > > <pragnesh.patel@sifive.com>; > > > > > bin.meng@windriver.com; Simon Glass <sjg@chromium.org>; Trevor > > > > Woerner > > > > > <twoerner@gmail.com>; Eugeniy Paltsev > > > > <Eugeniy.Paltsev@synopsys.com>; > > > > > Patrick Wildt <patrick@blueri.se>; Weijie Gao > > > > > <weijie.gao@mediatek.com>; Fabio Estevam <festevam@gmail.com> > > > > > Subject: Re: [PATCH v2 1/5] dt-bindings: prci: add indexes for > > > > > reset signals available in prci > > > > > > > > > > [External Email] Do not click links or attachments unless you > > > > > recognize the sender and know the content is safe > > > > > > > > > > On Fri, Jun 26, 2020 at 8:51 AM Sagar Kadam > > > > > <sagar.kadam@sifive.com> > > > > > wrote: > > > > > > > > > > > > Hi Jagan, > > > > > > > > > > > > > -----Original Message----- > > > > > > > From: Jagan Teki <jagan@amarulasolutions.com> > > > > > > > Sent: Thursday, June 25, 2020 11:13 PM > > > > > > > To: Sagar Kadam <sagar.kadam@sifive.com> > > > > > > > Cc: U-Boot-Denx <u-boot@lists.denx.de>; Rick Chen > > > > > <rick@andestech.com>; > > > > > > > Paul Walmsley ( Sifive) <paul.walmsley@sifive.com>; Palmer > > > > > > > Dabbelt <palmer@dabbelt.com>; Anup Patel > > <anup.patel@wdc.com>; > > > > > > > Atish > > > > > Patra > > > > > > > <atish.patra@wdc.com>; Lukasz Majewski <lukma@denx.de>; > > > > Pragnesh > > > > > > > Patel <pragnesh.patel@sifive.com>; bin.meng@windriver.com; > > > > > > > Simon > > > > > Glass > > > > > > > <sjg@chromium.org>; Trevor Woerner <twoerner@gmail.com>; > > > > Eugeniy > > > > > > > Paltsev <Eugeniy.Paltsev@synopsys.com>; Patrick Wildt > > > > > > > <patrick@blueri.se>; Weijie Gao <weijie.gao@mediatek.com>; > > > > > > > Fabio Estevam <festevam@gmail.com> > > > > > > > Subject: Re: [PATCH v2 1/5] dt-bindings: prci: add indexes for > > > > > > > reset > > > > > signals > > > > > > > available in prci > > > > > > > > > > > > > > [External Email] Do not click links or attachments unless you > > > > > > > recognize > > > > > the > > > > > > > sender and know the content is safe > > > > > > > > > > > > > > On Thu, Jun 25, 2020 at 5:56 PM Sagar Shrikant Kadam > > > > > > > <sagar.kadam@sifive.com> wrote: > > > > > > > > > > > > > > > > Add bit indexes for reset signals within the PRCI module on > > > > > > > > FU540-C000 SoC. > > > > > > > > The DDR and ethernet sub-system's have reset signals > > > > > > > > indicated by these reset indexes. > > > > > > > > > > > > > > > > Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> > > > > > > > > Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com> > > > > > > > > Reviewed-by: Bin Meng <bin.meng@windriver.com> > > > > > > > > --- > > > > > > > > include/dt-bindings/clock/sifive-fu540-prci.h | 8 ++++++++ > > > > > > > > 1 file changed, 8 insertions(+) > > > > > > > > > > > > > > > > diff --git a/include/dt-bindings/clock/sifive-fu540-prci.h > > > > > > > > b/include/dt- > > > > > > > bindings/clock/sifive-fu540-prci.h > > > > > > > > index 6a0b70a..1c03b09 100644 > > > > > > > > --- a/include/dt-bindings/clock/sifive-fu540-prci.h > > > > > > > > +++ b/include/dt-bindings/clock/sifive-fu540-prci.h > > > > > > > > @@ -15,4 +15,12 @@ > > > > > > > > #define PRCI_CLK_GEMGXLPLL 2 > > > > > > > > #define PRCI_CLK_TLCLK 3 > > > > > > > > > > > > > > > > +/* Reset bit indexes to be used by driver */ > > > > > > > > +#define PRCI_RST_DDR_CTRL_N 0 > > > > > > > > +#define PRCI_RST_DDR_AXI_N 1 > > > > > > > > +#define PRCI_RST_DDR_AHB_N 2 > > > > > > > > +#define PRCI_RST_DDR_PHY_N 3 > > > > > > > > +/* bit 4 is reserved bit */ > > > > > > > > +#define PRCI_RST_RSVD_N 4 > > > > > > > > +#define PRCI_RST_GEMGXL_N 5 > > > > > > > > #endif > > > > > > > > > > > > > > Do these bindings are synced from Linux? If Yes better to sync > > > > > > > with a particular commit or tag rather than patch. > > > > > > > > > > > > > > > > > > > No, these reset bindings are not synced from Linux. > > > > > > > > > > This is synced file from Linux, better to inline with Linux files > > > > > always, if these bindings are not related to Linux then maintain > > > > > it in a separate file or support it in Linux first if they do > > > > > require for Linux. > > > > > > > > > Ohh. Sorry I thought you were asking if reset-bindings are from Linux. > > > > Yes this file is synced from Linux but these reset-bindings are not > > > > related to Linux. So I can split it and place reset bindings into another > > file: > > > > "include/dt-bindings/reset/sifive-fu540-reset.h" > > > > > > It will be "include/dt-bindings/reset/sifive-fu540-prci.h" > > > > What if it would be the same directory structure and file name with -u- > > boot.h extension. This way we can identify these are u-boot related > > defines. > > > > Jagan. > > That's a good suggestion. Having an -u-boot.h extension will make the point > that it is needed only for u-boot. > Please correct me if I am wrong here, but I do see few references of similar > clock / reset module's ( eg: sun5i-ccu.h or tegra124-car.h etc.) sharing > header names in > 1. Clock bindings in include/dt-bindings/clock/ > 2. reset bindings in include/dt-bindings/reset/ > These headers provide respective clock and reset indexes. > So I was thinking similarly for prci to have clock indexes in dt- > bindings/clock and > reset indexes in dt-bindings/reset. > Due to above understanding I am in a bit of dilemma, which approach can be more suitable. > Thanks & BR, > Sagar Thanks & BR, Sagar
diff --git a/include/dt-bindings/clock/sifive-fu540-prci.h b/include/dt-bindings/clock/sifive-fu540-prci.h index 6a0b70a..1c03b09 100644 --- a/include/dt-bindings/clock/sifive-fu540-prci.h +++ b/include/dt-bindings/clock/sifive-fu540-prci.h @@ -15,4 +15,12 @@ #define PRCI_CLK_GEMGXLPLL 2 #define PRCI_CLK_TLCLK 3 +/* Reset bit indexes to be used by driver */ +#define PRCI_RST_DDR_CTRL_N 0 +#define PRCI_RST_DDR_AXI_N 1 +#define PRCI_RST_DDR_AHB_N 2 +#define PRCI_RST_DDR_PHY_N 3 +/* bit 4 is reserved bit */ +#define PRCI_RST_RSVD_N 4 +#define PRCI_RST_GEMGXL_N 5 #endif