| Message ID | 20200526144044.71413-5-zhouyanjie@wanyeetech.com |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | None | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success |
On Tue, 26 May 2020 22:40:41 +0800, 周琰杰 (Zhou Yanjie) wrote: > Add the clock bindings for the X1830 Soc from Ingenic. > > Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> > Reviewed-by: Rob Herring <robh@kernel.org> > --- > > Notes: > v2->v3: > Adjust order from [3/5] in v2 to [4/5] in v3. > > v3->v4: > Adjust order from [4/5] in v3 to [3/4] in v4. > > v4->v5: > Rebase on top of kernel 5.6-rc1. > > v5->v6: > Add missing part of X1830's CGU. > > v6->v7: > No change. > > v7->v8: > Rebase on top of linux-next. > > v8->v9: > No change. > > v9->v10: > Add missing "X1830_CLK_TCU". > > .../devicetree/bindings/clock/ingenic,cgu.yaml | 2 + > include/dt-bindings/clock/x1830-cgu.h | 55 ++++++++++++++++++++++ > 2 files changed, 57 insertions(+) > create mode 100644 include/dt-bindings/clock/x1830-cgu.h > Reviewed-by: Rob Herring <robh@kernel.org>
Hi Stephen, 在 2020/5/27 下午4:12, Stephen Boyd 写道: > Quoting 周琰杰 (Zhou Yanjie) (2020-05-26 07:40:41) >> Add the clock bindings for the X1830 Soc from Ingenic. >> >> Signed-off-by: \u5468\u7430\u6770 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> >> Reviewed-by: Rob Herring <robh@kernel.org> >> --- >> >> Notes: >> v2->v3: >> Adjust order from [3/5] in v2 to [4/5] in v3. >> >> v3->v4: >> Adjust order from [4/5] in v3 to [3/4] in v4. >> >> v4->v5: >> Rebase on top of kernel 5.6-rc1. >> >> v5->v6: >> Add missing part of X1830's CGU. >> >> v6->v7: >> No change. >> >> v7->v8: >> Rebase on top of linux-next. >> >> v8->v9: >> No change. >> >> v9->v10: >> Add missing "X1830_CLK_TCU". >> >> .../devicetree/bindings/clock/ingenic,cgu.yaml | 2 + >> include/dt-bindings/clock/x1830-cgu.h | 55 ++++++++++++++++++++++ >> 2 files changed, 57 insertions(+) >> create mode 100644 include/dt-bindings/clock/x1830-cgu.h >> >> diff --git a/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml b/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml > This file is in Rob's DT tree staged for the next release, not in the > clk tree. Can you split this patch into two, one for the compatible > update and another for the header file update and send again? Then Rob > can pick up the yaml file change and I can pick up the header file > change. OK, I will do it right away. Thansk and best regards! >> index 0281cd1d7e1b..a952d5811823 100644 >> --- a/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml >> +++ b/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml >> @@ -25,6 +25,7 @@ select: >> - ingenic,jz4770-cgu >> - ingenic,jz4780-cgu >> - ingenic,x1000-cgu >> + - ingenic,x1830-cgu >> required: >> - compatible >> >> @@ -51,6 +52,7 @@ properties: >> - ingenic,jz4770-cgu >> - ingenic,jz4780-cgu >> - ingenic,x1000-cgu >> + - ingenic,x1830-cgu >> - const: simple-mfd >> minItems: 1 >>
Hi Stephen, I may have misunderstood what you meant (I did not notice that you have taken other v10 patches, so I sent the entire v11 series by mistake), do I need to resend the split bindings patches separately again? Thanks and best regards! 在 2020/5/27 下午4:12, Stephen Boyd 写道: > Quoting 周琰杰 (Zhou Yanjie) (2020-05-26 07:40:41) >> Add the clock bindings for the X1830 Soc from Ingenic. >> >> Signed-off-by: \u5468\u7430\u6770 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> >> Reviewed-by: Rob Herring <robh@kernel.org> >> --- >> >> Notes: >> v2->v3: >> Adjust order from [3/5] in v2 to [4/5] in v3. >> >> v3->v4: >> Adjust order from [4/5] in v3 to [3/4] in v4. >> >> v4->v5: >> Rebase on top of kernel 5.6-rc1. >> >> v5->v6: >> Add missing part of X1830's CGU. >> >> v6->v7: >> No change. >> >> v7->v8: >> Rebase on top of linux-next. >> >> v8->v9: >> No change. >> >> v9->v10: >> Add missing "X1830_CLK_TCU". >> >> .../devicetree/bindings/clock/ingenic,cgu.yaml | 2 + >> include/dt-bindings/clock/x1830-cgu.h | 55 ++++++++++++++++++++++ >> 2 files changed, 57 insertions(+) >> create mode 100644 include/dt-bindings/clock/x1830-cgu.h >> >> diff --git a/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml b/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml > This file is in Rob's DT tree staged for the next release, not in the > clk tree. Can you split this patch into two, one for the compatible > update and another for the header file update and send again? Then Rob > can pick up the yaml file change and I can pick up the header file > change. > >> index 0281cd1d7e1b..a952d5811823 100644 >> --- a/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml >> +++ b/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml >> @@ -25,6 +25,7 @@ select: >> - ingenic,jz4770-cgu >> - ingenic,jz4780-cgu >> - ingenic,x1000-cgu >> + - ingenic,x1830-cgu >> required: >> - compatible >> >> @@ -51,6 +52,7 @@ properties: >> - ingenic,jz4770-cgu >> - ingenic,jz4780-cgu >> - ingenic,x1000-cgu >> + - ingenic,x1830-cgu >> - const: simple-mfd >> minItems: 1 >>
Hi Stephen, I'm very sorry, forgive my carelessness, communication with Paul Cercueil made me realize that the modification of "CLK_OF_DECLARE_DRIVER" mentioned in comments of [7/7] has never really existed in the patch, v12 has fixed this problem, and split the patch about bindings according to your requirements, it may be a good idea to retake [4/7] and [7/7] of v12. Thanks and best regards! 在 2020/5/27 下午4:12, Stephen Boyd 写道: > Quoting 周琰杰 (Zhou Yanjie) (2020-05-26 07:40:41) >> Add the clock bindings for the X1830 Soc from Ingenic. >> >> Signed-off-by: \u5468\u7430\u6770 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> >> Reviewed-by: Rob Herring <robh@kernel.org> >> --- >> >> Notes: >> v2->v3: >> Adjust order from [3/5] in v2 to [4/5] in v3. >> >> v3->v4: >> Adjust order from [4/5] in v3 to [3/4] in v4. >> >> v4->v5: >> Rebase on top of kernel 5.6-rc1. >> >> v5->v6: >> Add missing part of X1830's CGU. >> >> v6->v7: >> No change. >> >> v7->v8: >> Rebase on top of linux-next. >> >> v8->v9: >> No change. >> >> v9->v10: >> Add missing "X1830_CLK_TCU". >> >> .../devicetree/bindings/clock/ingenic,cgu.yaml | 2 + >> include/dt-bindings/clock/x1830-cgu.h | 55 ++++++++++++++++++++++ >> 2 files changed, 57 insertions(+) >> create mode 100644 include/dt-bindings/clock/x1830-cgu.h >> >> diff --git a/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml b/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml > This file is in Rob's DT tree staged for the next release, not in the > clk tree. Can you split this patch into two, one for the compatible > update and another for the header file update and send again? Then Rob > can pick up the yaml file change and I can pick up the header file > change. > >> index 0281cd1d7e1b..a952d5811823 100644 >> --- a/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml >> +++ b/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml >> @@ -25,6 +25,7 @@ select: >> - ingenic,jz4770-cgu >> - ingenic,jz4780-cgu >> - ingenic,x1000-cgu >> + - ingenic,x1830-cgu >> required: >> - compatible >> >> @@ -51,6 +52,7 @@ properties: >> - ingenic,jz4770-cgu >> - ingenic,jz4780-cgu >> - ingenic,x1000-cgu >> + - ingenic,x1830-cgu >> - const: simple-mfd >> minItems: 1 >>
diff --git a/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml b/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml index 0281cd1d7e1b..a952d5811823 100644 --- a/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml +++ b/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml @@ -25,6 +25,7 @@ select: - ingenic,jz4770-cgu - ingenic,jz4780-cgu - ingenic,x1000-cgu + - ingenic,x1830-cgu required: - compatible @@ -51,6 +52,7 @@ properties: - ingenic,jz4770-cgu - ingenic,jz4780-cgu - ingenic,x1000-cgu + - ingenic,x1830-cgu - const: simple-mfd minItems: 1 diff --git a/include/dt-bindings/clock/x1830-cgu.h b/include/dt-bindings/clock/x1830-cgu.h new file mode 100644 index 000000000000..801e1d09c881 --- /dev/null +++ b/include/dt-bindings/clock/x1830-cgu.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides clock numbers for the ingenic,x1830-cgu DT binding. + * + * They are roughly ordered as: + * - external clocks + * - PLLs + * - muxes/dividers in the order they appear in the x1830 programmers manual + * - gates in order of their bit in the CLKGR* registers + */ + +#ifndef __DT_BINDINGS_CLOCK_X1830_CGU_H__ +#define __DT_BINDINGS_CLOCK_X1830_CGU_H__ + +#define X1830_CLK_EXCLK 0 +#define X1830_CLK_RTCLK 1 +#define X1830_CLK_APLL 2 +#define X1830_CLK_MPLL 3 +#define X1830_CLK_EPLL 4 +#define X1830_CLK_VPLL 5 +#define X1830_CLK_OTGPHY 6 +#define X1830_CLK_SCLKA 7 +#define X1830_CLK_CPUMUX 8 +#define X1830_CLK_CPU 9 +#define X1830_CLK_L2CACHE 10 +#define X1830_CLK_AHB0 11 +#define X1830_CLK_AHB2PMUX 12 +#define X1830_CLK_AHB2 13 +#define X1830_CLK_PCLK 14 +#define X1830_CLK_DDR 15 +#define X1830_CLK_MAC 16 +#define X1830_CLK_LCD 17 +#define X1830_CLK_MSCMUX 18 +#define X1830_CLK_MSC0 19 +#define X1830_CLK_MSC1 20 +#define X1830_CLK_SSIPLL 21 +#define X1830_CLK_SSIPLL_DIV2 22 +#define X1830_CLK_SSIMUX 23 +#define X1830_CLK_EMC 24 +#define X1830_CLK_EFUSE 25 +#define X1830_CLK_OTG 26 +#define X1830_CLK_SSI0 27 +#define X1830_CLK_SMB0 28 +#define X1830_CLK_SMB1 29 +#define X1830_CLK_SMB2 30 +#define X1830_CLK_UART0 31 +#define X1830_CLK_UART1 32 +#define X1830_CLK_SSI1 33 +#define X1830_CLK_SFC 34 +#define X1830_CLK_PDMA 35 +#define X1830_CLK_TCU 36 +#define X1830_CLK_DTRNG 37 +#define X1830_CLK_OST 38 + +#endif /* __DT_BINDINGS_CLOCK_X1830_CGU_H__ */