Message ID | 20200520000621.49152-2-vadivel.muruganx.ramuthevar@linux.intel.com |
---|---|
State | Changes Requested |
Delegated to: | Miquel Raynal |
Headers | show |
Series | mtd: rawnand: Add NAND controller support on Intel LGM SoC | expand |
On Wed, May 20, 2020 at 08:06:20AM +0800, Ramuthevar,Vadivel MuruganX wrote: > From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> > > Add YAML file for dt-bindings to support NAND Flash Controller > on Intel's Lightning Mountain SoC. > > Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> > --- > .../devicetree/bindings/mtd/intel,lgm-nand.yaml | 91 ++++++++++++++++++++++ > 1 file changed, 91 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml > > diff --git a/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml b/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml > new file mode 100644 > index 000000000000..cd4e983a449e > --- /dev/null > +++ b/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml > @@ -0,0 +1,91 @@ > +# SPDX-License-Identifier: GPL-2.0 Still not dual licensed. > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/mtd/intel,lgm-nand.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Intel LGM SoC NAND Controller Device Tree Bindings > + > +allOf: > + - $ref: "nand-controller.yaml" > + > +maintainers: > + - Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> > + > +properties: > + compatible: > + const: intel,lgm-nand-controller Still doesn't match the example. And the example will fail when it does. > + > + reg: > + items: > + - description: ebunand registers > + - description: hsnand registers > + - description: nand_cs0 external flash access > + - description: nand_cs1 external flash access > + - description: addr_sel0 memory region enable and access > + - description: addr_sel1 memory region enable and access reg-names? > + > + clocks: > + maxItems: 1 > + > + dmas: > + maxItems: 2 > + > + dma-names: > + items: > + - const: tx > + - const: rx > + > +patternProperties: > + "^nand@[a-f0-9]+$": > + type: object > + properties: > + reg: > + minimum: 0 > + maximum: 7 > + > + nand-ecc-mode: true > + > + nand-ecc-algo: > + const: hw > + > + additionalProperties: false > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names Not documented or should be dropped. > + - dmas > + - dma-names > + > +additionalProperties: false > + > +examples: > + - | > + nand-controller@e0f00000 { > + compatible = "intel,lgm-nand"; > + reg = <0xe0f00000 0x100>, > + <0xe1000000 0x300>, > + <0xe1400000 0x8000>, > + <0xe1c00000 0x1000>, > + <0x17400000 0x4>, > + <0x17c00000 0x4>; > + reg-names = "ebunand", "hsnand", "nand_cs0", "nand_cs1", > + "addr_sel0","addr_sel1"; Not documented. And needs a space after the ','. > + clocks = <&cgu0 125>; > + dmas = <&dma0 8>, <&dma0 9>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + #clock-cells = <1>; Should be removed? > + > + nand@0 { > + reg = <0>; > + nand-on-flash-bbt; > + #address-cells = <1>; > + #size-cells = <1>; > + }; > + }; > + > +... > -- > 2.11.0 >
Hi Rob, Thank you very much for the review comments... On 27/5/2020 4:43 am, Rob Herring wrote: > On Wed, May 20, 2020 at 08:06:20AM +0800, Ramuthevar,Vadivel MuruganX wrote: >> From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> >> >> Add YAML file for dt-bindings to support NAND Flash Controller >> on Intel's Lightning Mountain SoC. >> >> Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> >> --- >> .../devicetree/bindings/mtd/intel,lgm-nand.yaml | 91 ++++++++++++++++++++++ >> 1 file changed, 91 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml >> >> diff --git a/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml b/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml >> new file mode 100644 >> index 000000000000..cd4e983a449e >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml >> @@ -0,0 +1,91 @@ >> +# SPDX-License-Identifier: GPL-2.0 > > Still not dual licensed. oh sorry, will update. > >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/mtd/intel,lgm-nand.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Intel LGM SoC NAND Controller Device Tree Bindings >> + >> +allOf: >> + - $ref: "nand-controller.yaml" >> + >> +maintainers: >> + - Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> >> + >> +properties: >> + compatible: >> + const: intel,lgm-nand-controller > > Still doesn't match the example. And the example will fail when it does. Noted, will change it. > >> + >> + reg: >> + items: >> + - description: ebunand registers >> + - description: hsnand registers >> + - description: nand_cs0 external flash access >> + - description: nand_cs1 external flash access >> + - description: addr_sel0 memory region enable and access >> + - description: addr_sel1 memory region enable and access > > reg-names? should be -const: ebunand instead added description with register name , will keep "-const: ebunand ..etc" > >> + >> + clocks: >> + maxItems: 1 >> + >> + dmas: >> + maxItems: 2 >> + >> + dma-names: >> + items: >> + - const: tx >> + - const: rx >> + >> +patternProperties: >> + "^nand@[a-f0-9]+$": >> + type: object >> + properties: >> + reg: >> + minimum: 0 >> + maximum: 7 >> + >> + nand-ecc-mode: true >> + >> + nand-ecc-algo: >> + const: hw >> + >> + additionalProperties: false >> + >> +required: >> + - compatible >> + - reg >> + - clocks >> + - clock-names > > Not documented or should be dropped. Yes, will drop it. > >> + - dmas >> + - dma-names >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + nand-controller@e0f00000 { >> + compatible = "intel,lgm-nand"; >> + reg = <0xe0f00000 0x100>, >> + <0xe1000000 0x300>, >> + <0xe1400000 0x8000>, >> + <0xe1c00000 0x1000>, >> + <0x17400000 0x4>, >> + <0x17c00000 0x4>; >> + reg-names = "ebunand", "hsnand", "nand_cs0", "nand_cs1", >> + "addr_sel0","addr_sel1"; > > Not documented. And needs a space after the ','. Good catch, Thanks > >> + clocks = <&cgu0 125>; >> + dmas = <&dma0 8>, <&dma0 9>; >> + dma-names = "tx", "rx"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + #clock-cells = <1>; > > Should be removed? sure, will remove it Regards Vadivel > >> + >> + nand@0 { >> + reg = <0>; >> + nand-on-flash-bbt; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + }; >> + }; >> + >> +... >> -- >> 2.11.0 >>
diff --git a/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml b/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml new file mode 100644 index 000000000000..cd4e983a449e --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/intel,lgm-nand.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel LGM SoC NAND Controller Device Tree Bindings + +allOf: + - $ref: "nand-controller.yaml" + +maintainers: + - Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> + +properties: + compatible: + const: intel,lgm-nand-controller + + reg: + items: + - description: ebunand registers + - description: hsnand registers + - description: nand_cs0 external flash access + - description: nand_cs1 external flash access + - description: addr_sel0 memory region enable and access + - description: addr_sel1 memory region enable and access + + clocks: + maxItems: 1 + + dmas: + maxItems: 2 + + dma-names: + items: + - const: tx + - const: rx + +patternProperties: + "^nand@[a-f0-9]+$": + type: object + properties: + reg: + minimum: 0 + maximum: 7 + + nand-ecc-mode: true + + nand-ecc-algo: + const: hw + + additionalProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + - dmas + - dma-names + +additionalProperties: false + +examples: + - | + nand-controller@e0f00000 { + compatible = "intel,lgm-nand"; + reg = <0xe0f00000 0x100>, + <0xe1000000 0x300>, + <0xe1400000 0x8000>, + <0xe1c00000 0x1000>, + <0x17400000 0x4>, + <0x17c00000 0x4>; + reg-names = "ebunand", "hsnand", "nand_cs0", "nand_cs1", + "addr_sel0","addr_sel1"; + clocks = <&cgu0 125>; + dmas = <&dma0 8>, <&dma0 9>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + + nand@0 { + reg = <0>; + nand-on-flash-bbt; + #address-cells = <1>; + #size-cells = <1>; + }; + }; + +...