| Message ID | 20200520121835.31190-4-dmurphy@ti.com |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | DP83869 Enhancements | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/checkpatch | success | |
| robh/dt-meta-schema | success | |
| robh/dt-meta-schema | success |
On Wed, May 20, 2020 at 07:18:34AM -0500, Dan Murphy wrote: > Add the internal delay values into the header and update the binding > with the internal delay properties. > > Signed-off-by: Dan Murphy <dmurphy@ti.com> > --- > .../devicetree/bindings/net/ti,dp83869.yaml | 16 ++++++++++++++++ > include/dt-bindings/net/ti-dp83869.h | 18 ++++++++++++++++++ > 2 files changed, 34 insertions(+) > > diff --git a/Documentation/devicetree/bindings/net/ti,dp83869.yaml b/Documentation/devicetree/bindings/net/ti,dp83869.yaml > index 5b69ef03bbf7..344015ab9081 100644 > --- a/Documentation/devicetree/bindings/net/ti,dp83869.yaml > +++ b/Documentation/devicetree/bindings/net/ti,dp83869.yaml > @@ -64,6 +64,20 @@ properties: > Operational mode for the PHY. If this is not set then the operational > mode is set by the straps. see dt-bindings/net/ti-dp83869.h for values > > + ti,rx-internal-delay: > + $ref: /schemas/types.yaml#definitions/uint32 > + description: | > + RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83869.h > + for applicable values. Required only if interface type is > + PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_RXID. Hi Dan Having it required with PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_RXID is pretty unusual. Normally these properties are used to fine tune the delay, if the default of 2ns does not work. Andrew
Andrew On 5/20/20 8:56 AM, Andrew Lunn wrote: > On Wed, May 20, 2020 at 07:18:34AM -0500, Dan Murphy wrote: >> Add the internal delay values into the header and update the binding >> with the internal delay properties. >> >> Signed-off-by: Dan Murphy <dmurphy@ti.com> >> --- >> .../devicetree/bindings/net/ti,dp83869.yaml | 16 ++++++++++++++++ >> include/dt-bindings/net/ti-dp83869.h | 18 ++++++++++++++++++ >> 2 files changed, 34 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/net/ti,dp83869.yaml b/Documentation/devicetree/bindings/net/ti,dp83869.yaml >> index 5b69ef03bbf7..344015ab9081 100644 >> --- a/Documentation/devicetree/bindings/net/ti,dp83869.yaml >> +++ b/Documentation/devicetree/bindings/net/ti,dp83869.yaml >> @@ -64,6 +64,20 @@ properties: >> Operational mode for the PHY. If this is not set then the operational >> mode is set by the straps. see dt-bindings/net/ti-dp83869.h for values >> >> + ti,rx-internal-delay: >> + $ref: /schemas/types.yaml#definitions/uint32 >> + description: | >> + RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83869.h >> + for applicable values. Required only if interface type is >> + PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_RXID. > Hi Dan > > Having it required with PHY_INTERFACE_MODE_RGMII_ID or > PHY_INTERFACE_MODE_RGMII_RXID is pretty unusual. Normally these > properties are used to fine tune the delay, if the default of 2ns does > not work. Also if the MAC phy-mode is configured with RGMII-ID and no internal delay values defined wouldn't that be counter intuitive? The driver will error out if the RGMII-ID is used and there was no internal delay defined for either rx or tx making either one required. The MAC node needs to indicate to use the internal delay for RGMII other wise the driver should ignore the internal delay programming as these internal delays are not applicable to SGMII or MII modes. The RGMII mode can be used if the default 2ns delay is acceptable. Thus why we are documenting in the binding when the internal delay is required as putting these under "required" is not correct. Dan > > Andrew
Andrew On 5/20/20 10:28 AM, Dan Murphy wrote: > Andrew > > On 5/20/20 8:56 AM, Andrew Lunn wrote: >> On Wed, May 20, 2020 at 07:18:34AM -0500, Dan Murphy wrote: >>> Add the internal delay values into the header and update the binding >>> with the internal delay properties. >>> >>> Signed-off-by: Dan Murphy <dmurphy@ti.com> >>> --- >>> .../devicetree/bindings/net/ti,dp83869.yaml | 16 ++++++++++++++++ >>> include/dt-bindings/net/ti-dp83869.h | 18 >>> ++++++++++++++++++ >>> 2 files changed, 34 insertions(+) >>> >>> diff --git a/Documentation/devicetree/bindings/net/ti,dp83869.yaml >>> b/Documentation/devicetree/bindings/net/ti,dp83869.yaml >>> index 5b69ef03bbf7..344015ab9081 100644 >>> --- a/Documentation/devicetree/bindings/net/ti,dp83869.yaml >>> +++ b/Documentation/devicetree/bindings/net/ti,dp83869.yaml >>> @@ -64,6 +64,20 @@ properties: >>> Operational mode for the PHY. If this is not set then the >>> operational >>> mode is set by the straps. see dt-bindings/net/ti-dp83869.h >>> for values >>> + ti,rx-internal-delay: >>> + $ref: /schemas/types.yaml#definitions/uint32 >>> + description: | >>> + RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83869.h >>> + for applicable values. Required only if interface type is >>> + PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_RXID. >> Hi Dan >> >> Having it required with PHY_INTERFACE_MODE_RGMII_ID or >> PHY_INTERFACE_MODE_RGMII_RXID is pretty unusual. Normally these >> properties are used to fine tune the delay, if the default of 2ns does >> not work. > > Also if the MAC phy-mode is configured with RGMII-ID and no internal > delay values defined wouldn't that be counter intuitive? > > The driver will error out if the RGMII-ID is used and there was no > internal delay defined for either rx or tx making either one required. > > The MAC node needs to indicate to use the internal delay for RGMII > other wise the driver should ignore the internal delay programming as > these internal delays are not applicable to SGMII or MII modes. The > RGMII mode can be used if the default 2ns delay is acceptable. > > Thus why we are documenting in the binding when the internal delay is > required as putting these under "required" is not correct. > > Dan > This is also the same for the DP83867 PHY as that PHY and the 83869 have a few identical features like internal delay, WoL and downshifting. Dan >> >> Andrew
> > Hi Dan > > > > Having it required with PHY_INTERFACE_MODE_RGMII_ID or > > PHY_INTERFACE_MODE_RGMII_RXID is pretty unusual. Normally these > > properties are used to fine tune the delay, if the default of 2ns does > > not work. > > Also if the MAC phy-mode is configured with RGMII-ID and no internal delay > values defined wouldn't that be counter intuitive? Most PHYs don't allow the delay to be fine tuned. You just pass for example PHY_INTERFACE_MODE_RGMII_ID to the PHY driver and it enables a 2ns delay. That is what people expect, and is documented. Being able to tune the delay is an optional extra, which some PHYs support, but that is always above and beyond PHY_INTERFACE_MODE_RGMII_ID. Andrew
Andrew On 5/20/20 10:36 AM, Andrew Lunn wrote: >>> Hi Dan >>> >>> Having it required with PHY_INTERFACE_MODE_RGMII_ID or >>> PHY_INTERFACE_MODE_RGMII_RXID is pretty unusual. Normally these >>> properties are used to fine tune the delay, if the default of 2ns does >>> not work. >> Also if the MAC phy-mode is configured with RGMII-ID and no internal delay >> values defined wouldn't that be counter intuitive? > Most PHYs don't allow the delay to be fine tuned. You just pass for > example PHY_INTERFACE_MODE_RGMII_ID to the PHY driver and it enables a > 2ns delay. That is what people expect, and is documented. > Being able to tune the delay is an optional extra, which some PHYs > support, but that is always above and beyond > PHY_INTERFACE_MODE_RGMII_ID. I am interested in knowing where that is documented. I want to RTM I grepped for a few different words but came up empty Since this is a tuneable phy we need to program the ID. 2ns is the default value Maybe I can change it from Required to Configurable or Used. Dan > Andrew
On 5/20/2020 8:56 AM, Dan Murphy wrote: > Andrew > > On 5/20/20 10:36 AM, Andrew Lunn wrote: >>>> Hi Dan >>>> >>>> Having it required with PHY_INTERFACE_MODE_RGMII_ID or >>>> PHY_INTERFACE_MODE_RGMII_RXID is pretty unusual. Normally these >>>> properties are used to fine tune the delay, if the default of 2ns does >>>> not work. >>> Also if the MAC phy-mode is configured with RGMII-ID and no internal >>> delay >>> values defined wouldn't that be counter intuitive? >> Most PHYs don't allow the delay to be fine tuned. You just pass for >> example PHY_INTERFACE_MODE_RGMII_ID to the PHY driver and it enables a >> 2ns delay. That is what people expect, and is documented. > >> Being able to tune the delay is an optional extra, which some PHYs >> support, but that is always above and beyond >> PHY_INTERFACE_MODE_RGMII_ID. > > I am interested in knowing where that is documented. I want to RTM I > grepped for a few different words but came up empty > > Since this is a tuneable phy we need to program the ID. 2ns is the > default value > > Maybe I can change it from Required to Configurable or Used. I do not think this is properly documented, it is an established practice, but it should be clearly documented somewhere, I do not know whether that belongs in the PHY Device Tree binding or if this belongs to the PHY documentation.
> I am interested in knowing where that is documented. I want to RTM I > grepped for a few different words but came up empty Hi Dan It probably is not well documented, but one example would be Documentation/devicetree/bindings/net/ethernet-controller.yaml says: # RX and TX delays are added by the MAC when required - rgmii # RGMII with internal RX and TX delays provided by the PHY, # the MAC should not add the RX or TX delays in this case - rgmii-id # RGMII with internal RX delay provided by the PHY, the MAC # should not add an RX delay in this case - rgmii-rxid # RGMII with internal TX delay provided by the PHY, the MAC # should not add an TX delay in this case Andrew
Andrew/Florian On 5/20/20 11:43 AM, Andrew Lunn wrote: >> I am interested in knowing where that is documented. I want to RTM I >> grepped for a few different words but came up empty > Hi Dan > > It probably is not well documented, but one example would be > > Documentation/devicetree/bindings/net/ethernet-controller.yaml > > says: > > # RX and TX delays are added by the MAC when required > - rgmii > > # RGMII with internal RX and TX delays provided by the PHY, > # the MAC should not add the RX or TX delays in this case > - rgmii-id > > # RGMII with internal RX delay provided by the PHY, the MAC > # should not add an RX delay in this case > - rgmii-rxid > > # RGMII with internal TX delay provided by the PHY, the MAC > # should not add an TX delay in this case > > Andrew OKI I read that. I also looked at a couple other drivers too. I am wondering if rx-internal-delay and tx-internal-delay should become a common property like tx/rx fifo-depth And properly document how to use it or at least the expectation on use. Dan
On 5/20/2020 10:20 AM, Dan Murphy wrote: > Andrew/Florian > > On 5/20/20 11:43 AM, Andrew Lunn wrote: >>> I am interested in knowing where that is documented. I want to RTM I >>> grepped for a few different words but came up empty >> Hi Dan >> >> It probably is not well documented, but one example would be >> >> Documentation/devicetree/bindings/net/ethernet-controller.yaml >> >> says: >> >> # RX and TX delays are added by the MAC when required >> - rgmii >> >> # RGMII with internal RX and TX delays provided by the PHY, >> # the MAC should not add the RX or TX delays in this case >> - rgmii-id >> >> # RGMII with internal RX delay provided by the PHY, the MAC >> # should not add an RX delay in this case >> - rgmii-rxid >> >> # RGMII with internal TX delay provided by the PHY, the MAC >> # should not add an TX delay in this case >> >> Andrew > > OKI I read that. I also looked at a couple other drivers too. > > I am wondering if rx-internal-delay and tx-internal-delay should become > a common property like tx/rx fifo-depth > > And properly document how to use it or at least the expectation on use. Yes they should, and they should have an unit associated with the name.
Florian On 5/20/20 12:45 PM, Florian Fainelli wrote: > > On 5/20/2020 10:20 AM, Dan Murphy wrote: >> Andrew/Florian >> >> On 5/20/20 11:43 AM, Andrew Lunn wrote: >>>> I am interested in knowing where that is documented. I want to RTM I >>>> grepped for a few different words but came up empty >>> Hi Dan >>> >>> It probably is not well documented, but one example would be >>> >>> Documentation/devicetree/bindings/net/ethernet-controller.yaml >>> >>> says: >>> >>> # RX and TX delays are added by the MAC when required >>> - rgmii >>> >>> # RGMII with internal RX and TX delays provided by the PHY, >>> # the MAC should not add the RX or TX delays in this case >>> - rgmii-id >>> >>> # RGMII with internal RX delay provided by the PHY, the MAC >>> # should not add an RX delay in this case >>> - rgmii-rxid >>> >>> # RGMII with internal TX delay provided by the PHY, the MAC >>> # should not add an TX delay in this case >>> >>> Andrew >> OKI I read that. I also looked at a couple other drivers too. >> >> I am wondering if rx-internal-delay and tx-internal-delay should become >> a common property like tx/rx fifo-depth >>> And properly document how to use it or at least the expectation on use. > Yes they should, and they should have an unit associated with the name. UGH I think I just got volunteered to do make them common. Dan
Hi Dan
> UGH I think I just got volunteered to do make them common.
There is code you can copy from PHY drivers. :-)
What would be kind of nice is if the validate was in the core as
well. Pass a list of possible delays in pS, and it will do a
phydev_err() if what is in DT does not match one of the listed
delays. Take a look around at what current drivers do and see if you
can find a nice abstraction which will work for a few drivers. We
cannot easily convert existing drivers without breaking DT, but a
design which works in theory for what we currently have has a good
chance of working for any new PHY driver.
Andrew
Andrew On 5/20/20 2:27 PM, Andrew Lunn wrote: > Hi Dan > >> UGH I think I just got volunteered to do make them common. > There is code you can copy from PHY drivers. :-) > > What would be kind of nice is if the validate was in the core as > well. Pass a list of possible delays in pS, and it will do a > phydev_err() if what is in DT does not match one of the listed > delays. Take a look around at what current drivers do and see if you > can find a nice abstraction which will work for a few drivers. We > cannot easily convert existing drivers without breaking DT, but a > design which works in theory for what we currently have has a good > chance of working for any new PHY driver. I think adding it in the core would be a bit of a challenge. I think each PHY driver needs to handle parsing and validating this property on its own (like fifo-depth). It is a PHY specific setting. Take the DP83867/9 and the ADIN1200/ADIN1300. The 8386X devices has a delta granularity of 250pS and the AD devices is 200pS per each setting And the 867/9 has 3x more values (15) vs only 5 for the AD PHY. And the Atheros AR803x PHY does use rgmii-id in the yaml, which I guess is what you were pointing out, that if set the PHY uses a default 2nS delay and it is not configurable. Same with the Broadcomm. Ack to not changing already existing drivers which is only 2 the AD PHY and the DP83867 PHY. But I can update the yaml for the 83867 and mark the TI specific properties as deprecated in favor of the new properties like I did with fifo-depth. Dan > Andrew
> I think adding it in the core would be a bit of a challenge. I think each > PHY driver needs to handle parsing and validating this property on its own > (like fifo-depth). It is a PHY specific setting. fifo-depth yes. But some delays follow a common pattern. e.g. Documentation/devicetree/bindings/net/micrel-ksz90x1.txt Device Tree Value Delay Pad Skew Register Value ----------------------------------------------------- 0 -840ps 0000 200 -720ps 0001 400 -600ps 0010 600 -480ps 0011 800 -360ps 0100 1000 -240ps 0101 1200 -120ps 0110 1400 0ps 0111 1600 120ps 1000 1800 240ps 1001 2000 360ps 1010 2200 480ps 1011 2400 600ps 1100 2600 720ps 1101 2800 840ps 1110 3000 960ps 1111 Documentation/devicetree/bindings/net/adi,adin.yaml adi,rx-internal-delay-ps: description: | RGMII RX Clock Delay used only when PHY operates in RGMII mode with internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds. enum: [ 1600, 1800, 2000, 2200, 2400 ] default: 2000 adi,tx-internal-delay-ps: description: | RGMII TX Clock Delay used only when PHY operates in RGMII mode with internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds. enum: [ 1600, 1800, 2000, 2200, 2400 ] default: 2000 Documentation/devicetree/bindings/net/apm-xgene-enet.txt - tx-delay: Delay value for RGMII bridge TX clock. Valid values are between 0 to 7, that maps to 417, 717, 1020, 1321, 1611, 1913, 2215, 2514 ps Default value is 4, which corresponds to 1611 ps - rx-delay: Delay value for RGMII bridge RX clock. Valid values are between 0 to 7, that maps to 273, 589, 899, 1222, 1480, 1806, 2147, 2464 ps Default value is 2, which corresponds to 899 ps You could implement checking against a table of valid values, which is something you need for your PHY. You could even consider making it a 2D table, and return the register value, not the delay? Andrew
Andrew On 5/20/20 3:44 PM, Andrew Lunn wrote: >> I think adding it in the core would be a bit of a challenge. I think each >> PHY driver needs to handle parsing and validating this property on its own >> (like fifo-depth). It is a PHY specific setting. > fifo-depth yes. But some delays follow a common pattern. > > e.g. > Documentation/devicetree/bindings/net/micrel-ksz90x1.txt > > Device Tree Value Delay Pad Skew Register Value > ----------------------------------------------------- > 0 -840ps 0000 > 200 -720ps 0001 > 400 -600ps 0010 > 600 -480ps 0011 > 800 -360ps 0100 > 1000 -240ps 0101 > 1200 -120ps 0110 > 1400 0ps 0111 > 1600 120ps 1000 > 1800 240ps 1001 > 2000 360ps 1010 > 2200 480ps 1011 > 2400 600ps 1100 > 2600 720ps 1101 > 2800 840ps 1110 > 3000 960ps 1111 > > Documentation/devicetree/bindings/net/adi,adin.yaml > > adi,rx-internal-delay-ps: > description: | > RGMII RX Clock Delay used only when PHY operates in RGMII mode with > internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds. > enum: [ 1600, 1800, 2000, 2200, 2400 ] > default: 2000 > > adi,tx-internal-delay-ps: > description: | > RGMII TX Clock Delay used only when PHY operates in RGMII mode with > internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds. > enum: [ 1600, 1800, 2000, 2200, 2400 ] > default: 2000 > > Documentation/devicetree/bindings/net/apm-xgene-enet.txt > > - tx-delay: Delay value for RGMII bridge TX clock. > Valid values are between 0 to 7, that maps to > 417, 717, 1020, 1321, 1611, 1913, 2215, 2514 ps > Default value is 4, which corresponds to 1611 ps > - rx-delay: Delay value for RGMII bridge RX clock. > Valid values are between 0 to 7, that maps to > 273, 589, 899, 1222, 1480, 1806, 2147, 2464 ps > Default value is 2, which corresponds to 899 ps > > You could implement checking against a table of valid values, which is > something you need for your PHY. You could even consider making it a > 2D table, and return the register value, not the delay? So provide a helper function that will just basically parse an array and return the indexed value. The outlier here is the AD device since the index to value is not 1-1 mapping. Not sure we need a 2D table like the AD driver. I actually implemented this in the dp83869 a bit ago and have done this in a few other non-PHY drivers. I guess I can look at making it a utility function in the networking space. Dan > > Andrew
diff --git a/Documentation/devicetree/bindings/net/ti,dp83869.yaml b/Documentation/devicetree/bindings/net/ti,dp83869.yaml index 5b69ef03bbf7..344015ab9081 100644 --- a/Documentation/devicetree/bindings/net/ti,dp83869.yaml +++ b/Documentation/devicetree/bindings/net/ti,dp83869.yaml @@ -64,6 +64,20 @@ properties: Operational mode for the PHY. If this is not set then the operational mode is set by the straps. see dt-bindings/net/ti-dp83869.h for values + ti,rx-internal-delay: + $ref: /schemas/types.yaml#definitions/uint32 + description: | + RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83869.h + for applicable values. Required only if interface type is + PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_RXID. + + ti,tx-internal-delay: + $ref: /schemas/types.yaml#definitions/uint32 + description: | + RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83869.h + for applicable values. Required only if interface type is + PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_TXID. + required: - reg @@ -80,5 +94,7 @@ examples: ti,op-mode = <DP83869_RGMII_COPPER_ETHERNET>; ti,max-output-impedance = "true"; ti,clk-output-sel = <DP83869_CLK_O_SEL_CHN_A_RCLK>; + ti,rx-internal-delay = <DP83869_RGMIIDCTL_2_25_NS>; + ti,tx-internal-delay = <DP83869_RGMIIDCTL_2_75_NS>; }; }; diff --git a/include/dt-bindings/net/ti-dp83869.h b/include/dt-bindings/net/ti-dp83869.h index 218b1a64e975..77d104a40f1f 100644 --- a/include/dt-bindings/net/ti-dp83869.h +++ b/include/dt-bindings/net/ti-dp83869.h @@ -16,6 +16,24 @@ #define DP83869_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 #define DP83869_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 +/* RGMIIDCTL internal delay for rx and tx */ +#define DP83869_RGMIIDCTL_250_PS 0x0 +#define DP83869_RGMIIDCTL_500_PS 0x1 +#define DP83869_RGMIIDCTL_750_PS 0x2 +#define DP83869_RGMIIDCTL_1_NS 0x3 +#define DP83869_RGMIIDCTL_1_25_NS 0x4 +#define DP83869_RGMIIDCTL_1_50_NS 0x5 +#define DP83869_RGMIIDCTL_1_75_NS 0x6 +#define DP83869_RGMIIDCTL_2_00_NS 0x7 +#define DP83869_RGMIIDCTL_2_25_NS 0x8 +#define DP83869_RGMIIDCTL_2_50_NS 0x9 +#define DP83869_RGMIIDCTL_2_75_NS 0xa +#define DP83869_RGMIIDCTL_3_00_NS 0xb +#define DP83869_RGMIIDCTL_3_25_NS 0xc +#define DP83869_RGMIIDCTL_3_50_NS 0xd +#define DP83869_RGMIIDCTL_3_75_NS 0xe +#define DP83869_RGMIIDCTL_4_00_NS 0xf + /* IO_MUX_CFG - Clock output selection */ #define DP83869_CLK_O_SEL_CHN_A_RCLK 0x0 #define DP83869_CLK_O_SEL_CHN_B_RCLK 0x1
Add the internal delay values into the header and update the binding with the internal delay properties. Signed-off-by: Dan Murphy <dmurphy@ti.com> --- .../devicetree/bindings/net/ti,dp83869.yaml | 16 ++++++++++++++++ include/dt-bindings/net/ti-dp83869.h | 18 ++++++++++++++++++ 2 files changed, 34 insertions(+)