diff mbox series

[v11,11/18] clk: sifive: fu540-prci: Release ethernet clock reset

Message ID 20200519070346.24479-12-pragnesh.patel@sifive.com
State Superseded
Delegated to: Andes
Headers show
Series RISC-V SiFive FU540 support SPL | expand

Commit Message

Pragnesh Patel May 19, 2020, 7:03 a.m. UTC 
Release ethernet clock reset once clock is initialized.
This is necessary to do as U-Boot proper needs ethernet
clock.

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
---
 drivers/clk/sifive/fu540-prci.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

Comments

Jagan Teki May 19, 2020, 4:17 p.m. UTC | #1 
On Tue, May 19, 2020 at 12:35 PM Pragnesh Patel
<pragnesh.patel@sifive.com> wrote:
>
> Release ethernet clock reset once clock is initialized.
> This is necessary to do as U-Boot proper needs ethernet
> clock.

Better write proper commit mesaage can clear the reason for phy reset here.

Sample "U-Boot ethernet phy work with FSBL flow where the phy reset is
part of FSBL itself, but since SPL not touching ant ethernet phy an
explicit ethernet phy required for U-Boot proper. With this change phy
reset code in FSBL might not be needed or unaffected."

Jagan.
diff mbox series

Patch

diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c
index f26a370a64..45491a77d5 100644
--- a/drivers/clk/sifive/fu540-prci.c
+++ b/drivers/clk/sifive/fu540-prci.c
@@ -559,6 +559,25 @@  static void __prci_ddr_release_reset(struct __prci_data *pd)
 		asm volatile ("nop");
 }
 
+/**
+ * __prci_ethernet_release_reset() - Release ethernet reset
+ * @pd: struct __prci_data * for the PRCI containing the Ethernet CLK mux reg
+ *
+ */
+static void __prci_ethernet_release_reset(struct __prci_data *pd)
+{
+	u32 v;
+
+	/* Release GEMGXL reset */
+	v = __prci_readl(pd, PRCI_DEVICESRESETREG_OFFSET);
+	v |= PRCI_DEVICESRESETREG_GEMGXL_RST_N_MASK;
+	__prci_writel(v, PRCI_DEVICESRESETREG_OFFSET, pd);
+
+	/* Procmon => core clock */
+	__prci_writel(PRCI_PROCMONCFG_CORE_CLOCK_MASK, PRCI_PROCMONCFG_OFFSET,
+		      pd);
+}
+
 /*
  * PRCI integration data for each WRPLL instance
  */
@@ -579,6 +598,7 @@  static struct __prci_wrpll_data __prci_ddrpll_data = {
 static struct __prci_wrpll_data __prci_gemgxlpll_data = {
 	.cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET,
 	.cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET,
+	.release_reset = __prci_ethernet_release_reset,
 };
 
 /*