| Message ID | 20200422050419.72957-3-svaidy@linux.ibm.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Initial fused-core support for POWER9 | expand |
| Context | Check | Description |
|---|---|---|
| snowpatch_ozlabs/apply_patch | success | Successfully applied on branch master (9547b3da44d546f0083dd3aeb5436226fccf81e3) |
| snowpatch_ozlabs/snowpatch_job_snowpatch-skiboot | success | Test snowpatch/job/snowpatch-skiboot on branch master |
| snowpatch_ozlabs/snowpatch_job_snowpatch-skiboot-dco | success | Signed-off-by present |
On 4/22/20 7:04 AM, Vaidyanathan Srinivasan wrote: > From: Benjamin Herrenschmidt <benh@kernel.crashing.org> > > Set or clear the fused core mode bit in the XIVE inits > properly. While HostBoot is supposed to do it, I prefer > not depending on it doing the right thing, since we already > configure that register ourselves anyway. > > Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> > Signed-off-by: Michael Neuling <mikey@neuling.org> I suppose that the thread enablement in the presenter is correct ? This was never tested AFAICT. C. > --- > hw/xive.c | 4 ++++ > include/xive-p9-regs.h | 1 + > 2 files changed, 5 insertions(+) > > diff --git a/hw/xive.c b/hw/xive.c > index b90bd351..ee93b172 100644 > --- a/hw/xive.c > +++ b/hw/xive.c > @@ -1509,6 +1509,10 @@ static bool xive_config_init(struct xive *x) > val |= PC_TCTXT_CFG_LGS_EN; > /* Disable pressure relief as we hijack the field in the VPs */ > val &= ~PC_TCTXT_CFG_STORE_ACK; > + if (this_cpu()->is_fused_core) > + val |= PC_TCTXT_CFG_FUSE_CORE_EN; > + else > + val &= ~PC_TCTXT_CFG_FUSE_CORE_EN; > xive_regw(x, PC_TCTXT_CFG, val); > xive_dbg(x, "PC_TCTXT_CFG=%016llx\n", val); > > diff --git a/include/xive-p9-regs.h b/include/xive-p9-regs.h > index 7d18a6bf..fff341cc 100644 > --- a/include/xive-p9-regs.h > +++ b/include/xive-p9-regs.h > @@ -80,6 +80,7 @@ > #define PC_TCTXT_CFG_TARGET_EN PPC_BIT(1) > #define PC_TCTXT_CFG_LGS_EN PPC_BIT(2) > #define PC_TCTXT_CFG_STORE_ACK PPC_BIT(3) > +#define PC_TCTXT_CFG_FUSE_CORE_EN PPC_BIT(4) > #define PC_TCTXT_CFG_HARD_CHIPID_BLK PPC_BIT(8) > #define PC_TCTXT_CHIPID_OVERRIDE PPC_BIT(9) > #define PC_TCTXT_CHIPID PPC_BITMASK(12,15) >
* C?dric Le Goater <clg@kaod.org> [2020-04-25 15:14:32]: > On 4/22/20 7:04 AM, Vaidyanathan Srinivasan wrote: > > From: Benjamin Herrenschmidt <benh@kernel.crashing.org> > > > > Set or clear the fused core mode bit in the XIVE inits > > properly. While HostBoot is supposed to do it, I prefer > > not depending on it doing the right thing, since we already > > configure that register ourselves anyway. > > > > Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> > > Signed-off-by: Michael Neuling <mikey@neuling.org> > > I suppose that the thread enablement in the presenter is correct ? > This was never tested AFAICT. Hi Cedric, General host stability with interrupts tested ok. KVM guests are also ok. Is there a specific test that we should run and observe to verify this enablement? --Vaidy
Hello Vaidy, On 5/6/20 1:49 PM, Vaidyanathan Srinivasan wrote: > * C?dric Le Goater <clg@kaod.org> [2020-04-25 15:14:32]: > >> On 4/22/20 7:04 AM, Vaidyanathan Srinivasan wrote: >>> From: Benjamin Herrenschmidt <benh@kernel.crashing.org> >>> >>> Set or clear the fused core mode bit in the XIVE inits >>> properly. While HostBoot is supposed to do it, I prefer >>> not depending on it doing the right thing, since we already >>> configure that register ourselves anyway. >>> >>> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> >>> Signed-off-by: Michael Neuling <mikey@neuling.org> >> >> I suppose that the thread enablement in the presenter is correct ? >> This was never tested AFAICT. > > Hi Cedric, > > General host stability with interrupts tested ok. KVM guests are also > ok. Great. We have done fixes recently to increase the maximum number of guests. We were limited to 128 in the past, so much less that the number of available HW threads. Have you tried to push the limits ? > Is there a specific test that we should run and observe to verify this > enablement? Nah. It's just that the fused cored initialization is not used very often in XIVE driver. It should be fine with the above. Thanks, C.
diff --git a/hw/xive.c b/hw/xive.c index b90bd351..ee93b172 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -1509,6 +1509,10 @@ static bool xive_config_init(struct xive *x) val |= PC_TCTXT_CFG_LGS_EN; /* Disable pressure relief as we hijack the field in the VPs */ val &= ~PC_TCTXT_CFG_STORE_ACK; + if (this_cpu()->is_fused_core) + val |= PC_TCTXT_CFG_FUSE_CORE_EN; + else + val &= ~PC_TCTXT_CFG_FUSE_CORE_EN; xive_regw(x, PC_TCTXT_CFG, val); xive_dbg(x, "PC_TCTXT_CFG=%016llx\n", val); diff --git a/include/xive-p9-regs.h b/include/xive-p9-regs.h index 7d18a6bf..fff341cc 100644 --- a/include/xive-p9-regs.h +++ b/include/xive-p9-regs.h @@ -80,6 +80,7 @@ #define PC_TCTXT_CFG_TARGET_EN PPC_BIT(1) #define PC_TCTXT_CFG_LGS_EN PPC_BIT(2) #define PC_TCTXT_CFG_STORE_ACK PPC_BIT(3) +#define PC_TCTXT_CFG_FUSE_CORE_EN PPC_BIT(4) #define PC_TCTXT_CFG_HARD_CHIPID_BLK PPC_BIT(8) #define PC_TCTXT_CHIPID_OVERRIDE PPC_BIT(9) #define PC_TCTXT_CHIPID PPC_BITMASK(12,15)