diff mbox series

[v6,14/17] sifive: dts: fu540: Enable L2 Cache in U-Boot

Message ID 20200329170538.25449-15-pragnesh.patel@sifive.com
State Superseded
Delegated to: Andes
Headers show
Series RISC-V SiFive FU540 support SPL | expand

Commit Message

Pragnesh Patel March 29, 2020, 5:05 p.m. UTC 
Add L2 cache node to enable cache ways from U-Boot

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
---
 arch/riscv/dts/fu540-c000-u-boot.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

Comments

Bin Meng April 20, 2020, 9:35 a.m. UTC | #1 
On Mon, Mar 30, 2020 at 1:07 AM Pragnesh Patel
<pragnesh.patel@sifive.com> wrote:
>
> Add L2 cache node to enable cache ways from U-Boot
>
> Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
> ---
>  arch/riscv/dts/fu540-c000-u-boot.dtsi | 4 ++++
>  1 file changed, 4 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
diff mbox series

Patch

diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi
index 56a45371d4..8f6c9f525d 100644
--- a/arch/riscv/dts/fu540-c000-u-boot.dtsi
+++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
@@ -73,3 +73,7 @@ 
 &qspi2 {
 	u-boot,dm-spl;
 };
+
+&l2cache {
+	status = "okay";
+};