| Message ID | 20200329170538.25449-11-pragnesh.patel@sifive.com |
|---|---|
| State | Superseded |
| Delegated to: | Andes |
| Headers | show |
| Series | RISC-V SiFive FU540 support SPL | expand |
On Sun, Mar 29, 2020 at 10:37 PM Pragnesh Patel <pragnesh.patel@sifive.com> wrote: > > This sync has changes required to use GPIO in U-Boot and > U-Boot SPL. > > Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> > --- > arch/riscv/dts/fu540-c000.dtsi | 37 ++++++++++++++++++++++++- > arch/riscv/dts/hifive-unleashed-a00.dts | 9 ++++++ > 2 files changed, 45 insertions(+), 1 deletion(-) Would be better to sync whole changes with specific sha1 from Linux instead of pulling required pieces, this would help for periodic sync and gets updated with Linux dts. Jagan.
Hi Jagan, >-----Original Message----- >From: Jagan Teki <jagan@amarulasolutions.com> >Sent: 07 April 2020 01:07 >To: Pragnesh Patel <pragnesh.patel@sifive.com> >Cc: U-Boot-Denx <u-boot@lists.denx.de>; Atish Patra ><atish.patra@wdc.com>; palmerdabbelt@google.com; Bin Meng ><bmeng.cn@gmail.com>; Paul Walmsley <paul.walmsley@sifive.com>; Troy >Benjegerdes <troy.benjegerdes@sifive.com>; Anup Patel ><anup.patel@wdc.com>; Sagar Kadam <sagar.kadam@sifive.com>; Rick Chen ><rick@andestech.com> >Subject: Re: [PATCH v6 10/17] riscv: dts: sifive: Sync hifive-unleashed-a00 dts >from linux > >[External Email] Do not click links or attachments unless you recognize the >sender and know the content is safe > >On Sun, Mar 29, 2020 at 10:37 PM Pragnesh Patel ><pragnesh.patel@sifive.com> wrote: >> >> This sync has changes required to use GPIO in U-Boot and U-Boot SPL. >> >> Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> >> --- >> arch/riscv/dts/fu540-c000.dtsi | 37 ++++++++++++++++++++++++- >> arch/riscv/dts/hifive-unleashed-a00.dts | 9 ++++++ >> 2 files changed, 45 insertions(+), 1 deletion(-) > >Would be better to sync whole changes with specific sha1 from Linux instead >of pulling required pieces, this would help for periodic sync and gets updated >with Linux dts. This DTS files are copy of Linux DTS but yes it's better to add sha1 in commit description. Will update description in v7. > >Jagan.
On Mon, Mar 30, 2020 at 1:07 AM Pragnesh Patel <pragnesh.patel@sifive.com> wrote: > > This sync has changes required to use GPIO in U-Boot and > U-Boot SPL. > > Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> > --- > arch/riscv/dts/fu540-c000.dtsi | 37 ++++++++++++++++++++++++- > arch/riscv/dts/hifive-unleashed-a00.dts | 9 ++++++ > 2 files changed, 45 insertions(+), 1 deletion(-) > Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
diff --git a/arch/riscv/dts/fu540-c000.dtsi b/arch/riscv/dts/fu540-c000.dtsi index afa43c7ea3..7db8610534 100644 --- a/arch/riscv/dts/fu540-c000.dtsi +++ b/arch/riscv/dts/fu540-c000.dtsi @@ -54,6 +54,7 @@ reg = <1>; riscv,isa = "rv64imafdc"; tlb-split; + next-level-cache = <&l2cache>; cpu1_intc: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; @@ -77,6 +78,7 @@ reg = <2>; riscv,isa = "rv64imafdc"; tlb-split; + next-level-cache = <&l2cache>; cpu2_intc: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; @@ -100,6 +102,7 @@ reg = <3>; riscv,isa = "rv64imafdc"; tlb-split; + next-level-cache = <&l2cache>; cpu3_intc: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; @@ -123,6 +126,7 @@ reg = <4>; riscv,isa = "rv64imafdc"; tlb-split; + next-level-cache = <&l2cache>; cpu4_intc: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; @@ -162,6 +166,13 @@ clocks = <&prci PRCI_CLK_TLCLK>; status = "disabled"; }; + dma: dma@3000000 { + compatible = "sifive,fu540-c000-pdma"; + reg = <0x0 0x3000000 0x0 0x8000>; + interrupt-parent = <&plic0>; + interrupts = <23 24 25 26 27 28 29 30>; + #dma-cells = <1>; + }; uart1: serial@10011000 { compatible = "sifive,fu540-c000-uart", "sifive,uart0"; reg = <0x0 0x10011000 0x0 0x1000>; @@ -246,6 +257,30 @@ #pwm-cells = <3>; status = "disabled"; }; - + l2cache: cache-controller@2010000 { + compatible = "sifive,fu540-c000-ccache", "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <1024>; + cache-size = <2097152>; + cache-unified; + interrupt-parent = <&plic0>; + interrupts = <1 2 3>; + reg = <0x0 0x2010000 0x0 0x1000>; + }; + gpio: gpio@10060000 { + compatible = "sifive,fu540-c000-gpio", "sifive,gpio0"; + interrupt-parent = <&plic0>; + interrupts = <7>, <8>, <9>, <10>, <11>, <12>, <13>, + <14>, <15>, <16>, <17>, <18>, <19>, <20>, + <21>, <22>; + reg = <0x0 0x10060000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&prci PRCI_CLK_TLCLK>; + status = "disabled"; + }; }; }; diff --git a/arch/riscv/dts/hifive-unleashed-a00.dts b/arch/riscv/dts/hifive-unleashed-a00.dts index 88cfcb96bf..4a2729f5ca 100644 --- a/arch/riscv/dts/hifive-unleashed-a00.dts +++ b/arch/riscv/dts/hifive-unleashed-a00.dts @@ -2,6 +2,7 @@ /* Copyright (c) 2018-2019 SiFive, Inc */ #include "fu540-c000.dtsi" +#include <dt-bindings/gpio/gpio.h> /* Clock frequency (in Hz) of the PCB crystal for rtcclk */ #define RTCCLK_FREQ 1000000 @@ -41,6 +42,10 @@ clock-frequency = <RTCCLK_FREQ>; clock-output-names = "rtcclk"; }; + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpio 10 GPIO_ACTIVE_LOW>; + }; }; &uart0 { @@ -94,3 +99,7 @@ &pwm1 { status = "okay"; }; + +&gpio { + status = "okay"; +};
This sync has changes required to use GPIO in U-Boot and U-Boot SPL. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> --- arch/riscv/dts/fu540-c000.dtsi | 37 ++++++++++++++++++++++++- arch/riscv/dts/hifive-unleashed-a00.dts | 9 ++++++ 2 files changed, 45 insertions(+), 1 deletion(-)