| Message ID | 1585856319-4380-8-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add support for PCIe controller to work in endpoint mode on R-Car SoCs | expand |
Hi Prabhakar-san, Thank you for your patch! > From: Lad Prabhakar, Sent: Friday, April 3, 2020 4:39 AM <snip> > diff --git a/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml > b/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml > new file mode 100644 > index 000000000000..07cd5a7325d0 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml > @@ -0,0 +1,76 @@ > +# SPDX-License-Identifier: GPL-2.0 I'm sorry I should have mentioned in the previous review. This is better like the following. # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) https://patchwork.kernel.org/patch/11459267/#23246825 <snip> > +examples: > + - | > + #include <dt-bindings/clock/r8a774c0-cpg-mssr.h> > + #include <dt-bindings/power/r8a774c0-sysc.h> > + > + pcie0_ep: pcie-ep@fe000000 { > + compatible = "renesas,r8a774c0-pcie-ep", > + "renesas,rcar-gen3-pcie-ep"; > + reg = <0 0xfe000000 0 0x80000>, > + <0x0 0xfe100000 0 0x100000>, > + <0x0 0xfe200000 0 0x200000>, > + <0x0 0x30000000 0 0x8000000>, > + <0x0 0x38000000 0 0x8000000>; Examples are built with #{address,size}-cells = <1>, so reg = <0xfe000000 0x80000>, <0xfe100000 0x100000>, <0xfe200000 0x200000>, <0x30000000 0x8000000>, <0x38000000 0x8000000>; https://patchwork.kernel.org/patch/11459267/#23246825 Best regards, Yoshihiro Shimoda
Hi Shimoda-san, Thank you for the review. > -----Original Message----- > From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> > Sent: 03 April 2020 09:28 > To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>; Bjorn Helgaas <bhelgaas@google.com>; Rob Herring > <robh+dt@kernel.org>; Mark Rutland <mark.rutland@arm.com>; Geert Uytterhoeven <geert+renesas@glider.be>; Magnus Damm > <magnus.damm@gmail.com>; Kishon Vijay Abraham I <kishon@ti.com>; Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>; Marek Vasut > <marek.vasut+renesas@gmail.com>; linux-pci@vger.kernel.org > Cc: Catalin Marinas <catalin.marinas@arm.com>; Will Deacon <will@kernel.org>; Arnd Bergmann <arnd@arndb.de>; Greg Kroah-Hartman > <gregkh@linuxfoundation.org>; Andrew Murray <andrew.murray@arm.com>; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; > linux-arm-kernel@lists.infradead.org; linux-renesas-soc@vger.kernel.org; Chris Paterson <Chris.Paterson2@renesas.com>; Frank Rowand > <frowand.list@gmail.com>; Gustavo Pimentel <gustavo.pimentel@synopsys.com>; Jingoo Han <jingoohan1@gmail.com>; Simon Horman > <horms@verge.net.au>; Shawn Lin <shawn.lin@rock-chips.com>; Tom Joseph <tjoseph@cadence.com>; Heiko Stuebner > <heiko@sntech.de>; linux-rockchip@lists.infradead.org; Lad Prabhakar <prabhakar.csengg@gmail.com>; Prabhakar Mahadev Lad > <prabhakar.mahadev-lad.rj@bp.renesas.com> > Subject: RE: [PATCH v6 07/11] dt-bindings: PCI: rcar: Add bindings for R-Car PCIe endpoint controller > > Hi Prabhakar-san, > > Thank you for your patch! > > > From: Lad Prabhakar, Sent: Friday, April 3, 2020 4:39 AM > <snip> > > diff --git a/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml > > b/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml > > new file mode 100644 > > index 000000000000..07cd5a7325d0 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml > > @@ -0,0 +1,76 @@ > > +# SPDX-License-Identifier: GPL-2.0 > > I'm sorry I should have mentioned in the previous review. > This is better like the following. > > # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > https://patchwork.kernel.org/patch/11459267/#23246825 > Argh my bad I should have noticed this too, usual tendency is to ignore the patch when its being Acked 😃 > <snip> > > +examples: > > + - | > > + #include <dt-bindings/clock/r8a774c0-cpg-mssr.h> > > + #include <dt-bindings/power/r8a774c0-sysc.h> > > + > > + pcie0_ep: pcie-ep@fe000000 { > > + compatible = "renesas,r8a774c0-pcie-ep", > > + "renesas,rcar-gen3-pcie-ep"; > > + reg = <0 0xfe000000 0 0x80000>, > > + <0x0 0xfe100000 0 0x100000>, > > + <0x0 0xfe200000 0 0x200000>, > > + <0x0 0x30000000 0 0x8000000>, > > + <0x0 0x38000000 0 0x8000000>; > > Examples are built with #{address,size}-cells = <1>, so > > reg = <0xfe000000 0x80000>, > <0xfe100000 0x100000>, > <0xfe200000 0x200000>, > <0x30000000 0x8000000>, > <0x38000000 0x8000000>; > > https://patchwork.kernel.org/patch/11459267/#23246825 > Will change this as above. Cheers, --Prabhakar > Best regards, > Yoshihiro Shimoda Renesas Electronics Europe GmbH, Geschaeftsfuehrer/President: Carsten Jauch, Sitz der Gesellschaft/Registered office: Duesseldorf, Arcadiastrasse 10, 40472 Duesseldorf, Germany, Handelsregister/Commercial Register: Duesseldorf, HRB 3708 USt-IDNr./Tax identification no.: DE 119353406 WEEE-Reg.-Nr./WEEE reg. no.: DE 14978647
diff --git a/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml b/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml new file mode 100644 index 000000000000..07cd5a7325d0 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: GPL-2.0 +# Copyright (C) 2020 Renesas Electronics Europe GmbH - https://www.renesas.com/eu/en/ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/rcar-pci-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas R-Car PCIe Endpoint + +maintainers: + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> + +properties: + compatible: + items: + - const: renesas,r8a774c0-pcie-ep + - const: renesas,rcar-gen3-pcie-ep + + reg: + maxItems: 5 + + reg-names: + items: + - const: apb-base + - const: memory0 + - const: memory1 + - const: memory2 + - const: memory3 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: pcie + + max-functions: + minimum: 1 + maximum: 6 + +required: + - compatible + - reg + - reg-names + - resets + - power-domains + - clocks + - clock-names + - max-functions + +examples: + - | + #include <dt-bindings/clock/r8a774c0-cpg-mssr.h> + #include <dt-bindings/power/r8a774c0-sysc.h> + + pcie0_ep: pcie-ep@fe000000 { + compatible = "renesas,r8a774c0-pcie-ep", + "renesas,rcar-gen3-pcie-ep"; + reg = <0 0xfe000000 0 0x80000>, + <0x0 0xfe100000 0 0x100000>, + <0x0 0xfe200000 0 0x200000>, + <0x0 0x30000000 0 0x8000000>, + <0x0 0x38000000 0 0x8000000>; + reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; + resets = <&cpg 319>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + clocks = <&cpg CPG_MOD 319>; + clock-names = "pcie"; + max-functions = /bits/ 8 <1>; + };