Message ID | 20200319122737.3063291-4-thierry.reding@gmail.com |
---|---|
State | Deferred |
Headers | show |
Series | pinctrl: tegra: Support SFIO/GPIO programming | expand |
On 3/19/2020 5:57 PM, Thierry Reding wrote: > External email: Use caution opening links or attachments > > > From: Thierry Reding <treding@nvidia.com> > > The GG.0 and GG.1 GPIOs serve as CLKREQ and RST pins, respectively, for > PCIe controller 5 on Tegra194. When this controller is configured in > endpoint mode, these pins need to be used as GPIOs by the PCIe endpoint > driver. Typically the mode programming of these pins (GPIO vs. SFIO) is > performed by early boot firmware to ensure that the configuration is > consistent. > > However, the GG.0 and GG.1 pins are part of a special power partition > that is not enabled during early boot, and hence the early boot firmware > cannot program these pins to be GPIOs (they are SFIO by default). Adding > them as pin ranges for the pin controller allows the pin controller to > be involved when these pins are requested as GPIOs and allows the proper > programming to take place. > > Signed-off-by: Thierry Reding <treding@nvidia.com> > --- > drivers/gpio/gpio-tegra186.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/gpio/gpio-tegra186.c b/drivers/gpio/gpio-tegra186.c > index 1086c1fcaf49..79b553dc39a3 100644 > --- a/drivers/gpio/gpio-tegra186.c > +++ b/drivers/gpio/gpio-tegra186.c > @@ -839,11 +839,19 @@ static const struct tegra_gpio_port tegra194_main_ports[] = { > TEGRA194_MAIN_GPIO_PORT(GG, 0, 0, 2) > }; > > +static const struct tegra186_pin_range tegra194_main_pin_ranges[] = { > + { TEGRA194_MAIN_GPIO(GG, 0), "pex_l5_clkreq_n_pgg0" }, > + { TEGRA194_MAIN_GPIO(GG, 1), "pex_l5_rst_n_pgg1" }, > +}; > + > static const struct tegra_gpio_soc tegra194_main_soc = { > .num_ports = ARRAY_SIZE(tegra194_main_ports), > .ports = tegra194_main_ports, > .name = "tegra194-gpio", > .instance = 0, > + .num_pin_ranges = ARRAY_SIZE(tegra194_main_pin_ranges), > + .pin_ranges = tegra194_main_pin_ranges, > + .pinmux = "nvidia,tegra194-pinmux", > }; > > #define TEGRA194_AON_GPIO_PORT(_name, _bank, _port, _pins) \ > -- > 2.24.1 > Tested-by: Vidya Sagar <vidyas@nvidia.com>
On Thu, Mar 19, 2020 at 1:27 PM Thierry Reding <thierry.reding@gmail.com> wrote: > From: Thierry Reding <treding@nvidia.com> > > The GG.0 and GG.1 GPIOs serve as CLKREQ and RST pins, respectively, for > PCIe controller 5 on Tegra194. When this controller is configured in > endpoint mode, these pins need to be used as GPIOs by the PCIe endpoint > driver. Typically the mode programming of these pins (GPIO vs. SFIO) is > performed by early boot firmware to ensure that the configuration is > consistent. > > However, the GG.0 and GG.1 pins are part of a special power partition > that is not enabled during early boot, and hence the early boot firmware > cannot program these pins to be GPIOs (they are SFIO by default). Adding > them as pin ranges for the pin controller allows the pin controller to > be involved when these pins are requested as GPIOs and allows the proper > programming to take place. > > Signed-off-by: Thierry Reding <treding@nvidia.com> Patch applied! Yours, Linus Walleij
diff --git a/drivers/gpio/gpio-tegra186.c b/drivers/gpio/gpio-tegra186.c index 1086c1fcaf49..79b553dc39a3 100644 --- a/drivers/gpio/gpio-tegra186.c +++ b/drivers/gpio/gpio-tegra186.c @@ -839,11 +839,19 @@ static const struct tegra_gpio_port tegra194_main_ports[] = { TEGRA194_MAIN_GPIO_PORT(GG, 0, 0, 2) }; +static const struct tegra186_pin_range tegra194_main_pin_ranges[] = { + { TEGRA194_MAIN_GPIO(GG, 0), "pex_l5_clkreq_n_pgg0" }, + { TEGRA194_MAIN_GPIO(GG, 1), "pex_l5_rst_n_pgg1" }, +}; + static const struct tegra_gpio_soc tegra194_main_soc = { .num_ports = ARRAY_SIZE(tegra194_main_ports), .ports = tegra194_main_ports, .name = "tegra194-gpio", .instance = 0, + .num_pin_ranges = ARRAY_SIZE(tegra194_main_pin_ranges), + .pin_ranges = tegra194_main_pin_ranges, + .pinmux = "nvidia,tegra194-pinmux", }; #define TEGRA194_AON_GPIO_PORT(_name, _bank, _port, _pins) \