@@ -70,6 +70,10 @@ Conn Clark <clark@esteem.com>
ESTEEM192E MPC8xx
+Jason Cooper <u-boot@lakedaemon.net>
+
+ dreamplug ARM926EJS (Kirkwood SoC)
+
Joe D'Abbraccio <ljd015@freescale.com>
MPC837xERDB MPC837x
@@ -335,6 +335,7 @@ LIST_ARM9=" \
cp966 \
da830evm \
da850evm \
+ dreamplug \
edb9301 \
edb9302 \
edb9302a \
new file mode 100644
@@ -0,0 +1,54 @@
+#
+# (C) Copyright 2011
+# Jason Cooper <u-boot@lakedaemon.net>
+#
+# Based on work by:
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Siddarth Gore <gores@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := dreamplug.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
new file mode 100644
@@ -0,0 +1,157 @@
+/*
+ * (C) Copyright 2011
+ * Jason Cooper <u-boot@lakedaemon.net>
+ *
+ * Based on work by:
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Siddarth Gore <gores@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/kirkwood.h>
+#include <asm/arch/mpp.h>
+#include "dreamplug.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ /*
+ * default gpio configuration
+ * There are maximum 64 gpios controlled through 2 sets of registers
+ * the below configuration configures mainly initial LED status
+ */
+ kw_config_gpio(DREAMPLUG_OE_VAL_LOW,
+ DREAMPLUG_OE_VAL_HIGH,
+ DREAMPLUG_OE_LOW, DREAMPLUG_OE_HIGH);
+
+ /* Multi-Purpose Pins Functionality configuration */
+ u32 kwmpp_config[] = {
+ MPP0_SPI_SCn, /* SPI Flash */
+ MPP1_SPI_MOSI,
+ MPP2_SPI_SCK,
+ MPP3_SPI_MISO,
+ MPP4_GPIO,
+ MPP5_GPO,
+ MPP6_SYSRST_OUTn,
+ MPP7_GP0,
+ MPP8_TW_SDA,
+ MPP9_TW_SCK,
+ MPP10_UART0_TXD, /* Serial */
+ MPP11_UART0_RXD,
+ MPP12_SD_CLK, /* SDIO Slot */
+ MPP13_SD_CMD,
+ MPP14_SD_D0,
+ MPP15_SD_D1,
+ MPP16_SD_D2,
+ MPP17_SD_D3,
+ MPP18_GPO,
+ MPP19_GPO,
+ MPP20_GE1_0, /* Gigabit Ethernet */
+ MPP21_GE1_1,
+ MPP22_GE1_2,
+ MPP23_GE1_3,
+ MPP24_GE1_4,
+ MPP25_GE1_5,
+ MPP26_GE1_6,
+ MPP27_GE1_7,
+ MPP28_GE1_8,
+ MPP29_GE1_9,
+ MPP30_GE1_10,
+ MPP31_GE1_11,
+ MPP32_GE1_12,
+ MPP33_GE1_13,
+ MPP34_GE1_14,
+ MPP35_GE1_15,
+ MPP36_GPIO,
+ MPP37_GPIO,
+ MPP38_GPIO,
+ MPP39_GPIO,
+ MPP40_TDM_SPI_SCK,
+ MPP41_TDM_SPI_MISO,
+ MPP42_TDM_SPI_MOSI,
+ MPP43_GPIO,
+ MPP44_GPIO,
+ MPP45_GPIO,
+ MPP46_GPIO, /* M_RLED */
+ MPP47_GPIO, /* M_GLED */
+ MPP48_GPIO, /* B_RLED */
+ MPP49_GPIO, /* B_GLED */
+ 0
+ };
+ kirkwood_mpp_conf(kwmpp_config);
+ return 0;
+}
+
+int board_init(void)
+{
+ /*
+ * arch number of board
+ * XXX: change to MACH_TYPE_DREAMPLUG once in Linux mainline.
+ */
+ gd->bd->bi_arch_number = MACH_TYPE_DREAMPLUG;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void mv_phy_88e1121_init(char *name)
+{
+ u16 reg;
+ u16 devadr;
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* command to read PHY dev address */
+ if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+ printf("Err..%s could not read PHY dev address\n",
+ __FUNCTION__);
+ return;
+ }
+
+ /*
+ * Enable RGMII delay on Tx and Rx for CPU port
+ * Ref: sec 4.7.2 of chip datasheet
+ */
+ miiphy_write(name, devadr, MV88E1121_PGADR_REG, 2);
+ miiphy_read(name, devadr, MV88E1121_MAC_CTRL2_REG, ®);
+ reg |= (MV88E1121_RGMII_RXTM_CTRL | MV88E1121_RGMII_TXTM_CTRL);
+ miiphy_write(name, devadr, MV88E1121_MAC_CTRL2_REG, reg);
+ miiphy_write(name, devadr, MV88E1121_PGADR_REG, 0);
+
+ /* reset the phy */
+ miiphy_reset(name, devadr);
+
+ printf("88E1121 Initialized on %s\n", name);
+}
+
+void reset_phy(void)
+{
+ /* configure and initialize both PHY's */
+ mv_phy_88e1121_init("egiga0");
+ mv_phy_88e1121_init("egiga1");
+}
+#endif /* CONFIG_RESET_PHY_R */
new file mode 100644
@@ -0,0 +1,42 @@
+/*
+ * (C) Copyright 2011
+ * Jason Cooper <u-boot@lakedaemon.net>
+ *
+ * Based on work by:
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Siddarth Gore <gores@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __DREAMPLUG_H
+#define __DREAMPLUG_H
+
+#define DREAMPLUG_OE_LOW (~(0))
+#define DREAMPLUG_OE_HIGH (~(0))
+#define DREAMPLUG_OE_VAL_LOW 0
+#define DREAMPLUG_OE_VAL_HIGH (0xf << 16) /* 4 LED Pins high */
+
+/* PHY related */
+#define MV88E1121_MAC_CTRL2_REG 21
+#define MV88E1121_PGADR_REG 22
+#define MV88E1121_RGMII_TXTM_CTRL (1 << 4)
+#define MV88E1121_RGMII_RXTM_CTRL (1 << 5)
+
+#endif /* __DREAMPLUG_H */
new file mode 100644
@@ -0,0 +1,163 @@
+#
+# (C) Copyright 2011
+# Jason Cooper <u-boot@lakedaemon.net>
+#
+# Based on work by:
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Siddarth Gore <gores@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM spi
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0/1 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b9b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000c30 # DDR Configuration register
+# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
+# bit 4: 0=addr/cmd in smame cycle
+# bit 5: 0=clk is driven during self refresh, we don't care for APX
+# bit 6: 0=use recommended falling edge of clk for addr/cmd
+# bit14: 0=input buffer always powered up
+# bit18: 1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31: 0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
+# bit3-0: TRAS lsbs
+# bit7-4: TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20: TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
+# bit6-0: TRFC
+# bit8-7: TR2R
+# bit10-9: TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x000000cc # DDR Address Control
+# bit1-0: 01, Cs0width=x8
+# bit3-2: 10, Cs0size=1Gb
+# bit5-4: 01, Cs1width=x8
+# bit7-6: 10, Cs1size=1Gb
+# bit9-8: 00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16: 0, Cs0AddrSel
+# bit17: 0, Cs1AddrSel
+# bit18: 0, Cs2AddrSel
+# bit19: 0, Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
+# bit0: 0, OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000 # DDR Operation
+# bit3-0: 0x0, DDR cmd
+# bit31-4: 0 required
+
+DATA 0xFFD0141C 0x00000C52 # DDR Mode
+# bit2-0: 2, BurstLen=2 required
+# bit3: 0, BurstType=0 required
+# bit6-4: 4, CL=5
+# bit7: 0, TestMode=0 normal
+# bit8: 0, DLL reset=0 normal
+# bit11-9: 6, auto-precharge write recovery ????????????
+# bit12: 0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000040 # DDR Extended Mode
+# bit0: 0, DDR DLL enabled
+# bit1: 0, DDR drive strenght normal
+# bit2: 0, DDR ODT control lsd (disabled)
+# bit5-3: 000, required
+# bit6: 1, DDR ODT control msb, (disabled)
+# bit9-7: 000, required
+# bit10: 0, differential DQS enabled
+# bit11: 0, required
+# bit12: 0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
+# bit2-0: 111, required
+# bit3 : 1 , MBUS Burst Chop disabled
+# bit6-4: 111, required
+# bit7 : 0
+# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9 : 0 , no half clock cycle addition to dataout
+# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0 required
+
+DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
+# bit0: 1, Window enabled
+# bit1: 0, Write Protect disabled
+# bit3-2: 00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x0F, Size (i.e. 256MB)
+
+DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
+DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
+
+DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
+DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
+# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
+# bit3-2: 01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
+DATA 0xFFD01480 0x00000001 # DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
@@ -109,6 +109,7 @@ davinci_sonata arm arm926ejs sonata davinci
suen3 arm arm926ejs km_arm keymile kirkwood
suen8 arm arm926ejs km_arm keymile kirkwood
mgcoge3un arm arm926ejs km_arm keymile kirkwood
+dreamplug arm arm926ejs - Marvell kirkwood
guruplug arm arm926ejs - Marvell kirkwood
mv88f6281gtw_ge arm arm926ejs - Marvell kirkwood
openrd_base arm arm926ejs openrd Marvell kirkwood openrd:BOARD_IS_OPENRD_BASE
new file mode 100644
@@ -0,0 +1,114 @@
+/*
+ * (C) Copyright 2011
+ * Jason Cooper <u-boot@lakedaemon.net>
+ *
+ * Based on work by:
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Siddarth Gore <gores@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _CONFIG_DREAMPLUG_H
+#define _CONFIG_DREAMPLUG_H
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING "\nMarvell-DreamPlug"
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */
+#define CONFIG_KIRKWOOD 1 /* SOC Family Name */
+#define CONFIG_KW88F6281 1 /* SOC Name */
+#define CONFIG_MACH_DREAMPLUG /* Machine type */
+#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_IDE
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/*
+ * Environment variables configurations
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_ENV_IS_IN_NAND 1
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */
+#else
+#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
+#endif
+/*
+ * max 4k env size is enough, but in case of nand
+ * it has to be rounded to sector size
+ */
+#define CONFIG_ENV_SIZE 0x20000 /* 128k */
+#define CONFIG_ENV_ADDR 0x60000
+#define CONFIG_ENV_OFFSET 0x60000 /* env starts here */
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND "setenv ethact egiga0; " \
+ "${x_bootcmd_ethernet}; setenv ethact egiga1; " \
+ "${x_bootcmd_ethernet}; ${x_bootcmd_usb}; ${x_bootcmd_kernel}; "\
+ "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \
+ "bootm 0x6400000;"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "x_bootcmd_ethernet=ping 192.168.2.1\0" \
+ "x_bootcmd_usb=usb start\0" \
+ "x_bootcmd_kernel=nand read.e 0x6400000 0x100000 0x400000\0" \
+ "x_bootargs=console=ttyS0,115200\0" \
+ "x_bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs\0"
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */
+#define CONFIG_PHY_BASE_ADR 0
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * SATA Driver configuration
+ */
+#ifdef CONFIG_MVSATA_IDE
+#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
+#endif /*CONFIG_MVSATA_IDE*/
+
+#define CONFIG_SYS_ALT_MEMTEST
+
+#endif /* _CONFIG_DREAMPLUG_H */