| Message ID | 20200116102548.GA14761@willie-the-truck |
|---|---|
| State | New |
| Headers | show |
| Series | [GIT,PULL] iommu/arm-smmu: Updates for 5.6 | expand |
On Thu, Jan 16, 2020 at 10:25:49AM +0000, Will Deacon wrote: > Hi Joerg, > > Please pull these Arm SMMU updates for 5.6. The branch is based on your > arm/smmu branch and includes a patch addressing the feedback from Greg > about setting the module 'owner' field in the 'iommu_ops'. > > I've used a signed tag this time, so you can see the summary of the > changes listed in there. The big deal is that we're laying the groundwork > for PCIe PASID support in SMMUv3, and I expect to hook that up for PCIe > masters in 5.7 once we've exported the necessary symbols to do so. > > Cheers, > > Will > > --->8 > > The following changes since commit 1ea27ee2f76e67f98b9942988f1336a70d351317: > > iommu/arm-smmu: Update my email address in MODULE_AUTHOR() (2019-12-23 14:06:06 +0100) > > are available in the Git repository at: > > git://git.kernel.org/pub/scm/linux/kernel/git/will/linux.git tags/arm-smmu-updates Pulled, thanks Will.
Hi Joerg, Please pull these Arm SMMU updates for 5.6. The branch is based on your arm/smmu branch and includes a patch addressing the feedback from Greg about setting the module 'owner' field in the 'iommu_ops'. I've used a signed tag this time, so you can see the summary of the changes listed in there. The big deal is that we're laying the groundwork for PCIe PASID support in SMMUv3, and I expect to hook that up for PCIe masters in 5.7 once we've exported the necessary symbols to do so. Cheers, Will --->8 The following changes since commit 1ea27ee2f76e67f98b9942988f1336a70d351317: iommu/arm-smmu: Update my email address in MODULE_AUTHOR() (2019-12-23 14:06:06 +0100) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/will/linux.git tags/arm-smmu-updates for you to fetch changes up to 5a4549fd790500d7db94b7d2af6d60cee42110c3: PCI/ATS: Add PASID stubs (2020-01-15 16:30:28 +0000) ---------------------------------------------------------------- Arm SMMU updates for 5.6 - Support for building, and {un,}loading the SMMU drivers as modules - Minor cleanups - SMMUv3: * Non-critical fix to encoding of TLBI_NH_VA invalidation command * Fix broken sanity check on size of MMIO resource during probe * Support for Substream IDs which will soon be provided by PCI PASIDs - io-pgtable: * Finish off the TTBR1 preparation work partially merged last cycle * Ensure correct memory attributes for non-cacheable mappings - SMMU: * Namespace public #defines to avoid collisions with arch/arm64/ * Avoid using valid SMR register when probing mask size ---------------------------------------------------------------- Jean-Philippe Brucker (12): iommu/arm-smmu-v3: Drop __GFP_ZERO flag from DMA allocation dt-bindings: document PASID property for IOMMU masters iommu/arm-smmu-v3: Parse PASID devicetree property of platform devices ACPI/IORT: Parse SSID property of named component node iommu/arm-smmu-v3: Prepare arm_smmu_s1_cfg for SSID support iommu/arm-smmu-v3: Add context descriptor tables allocators iommu/arm-smmu-v3: Add support for Substream IDs iommu/arm-smmu-v3: Propagate ssid_bits iommu/arm-smmu-v3: Prepare for handling arm_smmu_write_ctx_desc() failure iommu/arm-smmu-v3: Add second level of context descriptor table iommu/arm-smmu-v3: Improve add_device() error handling PCI/ATS: Add PASID stubs Masahiro Yamada (3): iommu/arm-smmu-v3: Fix resource_size check iommu/arm-smmu-v3: Remove useless of_match_ptr() iommu/arm-smmu: Fix -Wunused-const-variable warning Robin Murphy (5): iommu/io-pgtable-arm: Rationalise TTBRn handling iommu/io-pgtable-arm: Improve attribute handling iommu/io-pgtable-arm: Rationalise TCR handling iommu/io-pgtable-arm: Prepare for TTBR1 usage iommu/arm-smmu: Improve SMR mask test Shameer Kolothum (1): iommu/arm-smmu-v3: Populate VMID field for CMDQ_OP_TLBI_NH_VA Will Deacon (7): drivers/iommu: Initialise module 'owner' field in iommu_device_set_ops() iommu/io-pgtable-arm: Support non-coherent stage-2 page tables iommu/io-pgtable-arm: Ensure ARM_64_LPAE_S2_TCR_RES1 is unsigned iommu/arm-smmu: Rename public #defines under ARM_SMMU_ namespace iommu/io-pgtable-arm: Rationalise VTCR handling iommu/arm-smmu-v3: Use WRITE_ONCE() when changing validity of an STE iommu/arm-smmu-v3: Return -EBUSY when trying to re-add a device Documentation/devicetree/bindings/iommu/iommu.txt | 6 + drivers/acpi/arm64/iort.c | 18 + drivers/iommu/arm-smmu-impl.c | 2 +- drivers/iommu/arm-smmu-v3.c | 499 +++++++++++++++++----- drivers/iommu/arm-smmu.c | 197 +++++---- drivers/iommu/arm-smmu.h | 228 ++++++---- drivers/iommu/io-pgtable-arm-v7s.c | 22 +- drivers/iommu/io-pgtable-arm.c | 164 ++++--- drivers/iommu/io-pgtable.c | 2 +- drivers/iommu/ipmmu-vmsa.c | 2 +- drivers/iommu/msm_iommu.c | 4 +- drivers/iommu/mtk_iommu.c | 4 +- drivers/iommu/of_iommu.c | 6 +- drivers/iommu/qcom_iommu.c | 25 +- include/linux/io-pgtable.h | 27 +- include/linux/iommu.h | 13 +- include/linux/pci-ats.h | 3 + 17 files changed, 810 insertions(+), 412 deletions(-)